PSI-NSIM[3] [4][5][6][7] UPPAAL[8] PRISM[9] [10] [11] TDMA [12] TDMA [13][14] LOTTERYBUS [13][14] Slack-based Bus [12] [15] [16] [17] R

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1 1 2 A Performance prediction technique in consideration of utilization and memory band utilization NOBORU WAKABAYASHI 1 NOBUKAZU YOSHIOKA 2 Consumer products, such as Digital-TV, the consumer products have been becoming high functionality year by year. On the other hand, the cost reduction is required because of the competition intensification on the price side, without using rich specification hardware(, memory, etc). Thus, it is needed to draw current performance to the limit. After all, the performance prediction technique is required. This paper proposes a performance prediction technique in consideration of utilization and memory band utilization ( ) Hitachi Ltd. 2 National Institute of Informatics [1][2] c2014 Information Processing Society of Japan 1

2 PSI-NSIM[3] [4][5][6][7] UPPAAL[8] PRISM[9] [10] [11] TDMA [12] TDMA [13][14] LOTTERYBUS [13][14] Slack-based Bus [12] [15] [16] [17] RAM (Network Interface Controller : NIC) HDD SSD DDR2-SDRAM SDRAM c2014 Information Processing Society of Japan 2

3 DDR2-SDRAM (Network Interface Controller : NIC) HDD SSD DDR2-SDRAM 2 (ms) (MHz) 2 DDR F mean [MHz] F max R U m 1 U m = (F mean [MHz] + F max [MHz] R) / F max [MHz] DDR [a] 3 3 1% 1 1 a vmstat top c2014 Information Processing Society of Japan 3

4 使用率の増加比率 ( 倍 ) 近似曲線 Y = x x % 20.0% 40.0% 60.0% 80.0% 100.0% メモリ帯域使用率 (%) Y x 2 2 a = , b = , c = a,b,c a,b,c 2 Y = f(x) = ax 2 + bx + c % % U cb U cx U m U cp U cp = U cx / f(um) Ucb 3 U mb U mp 4 Ump = Um Umb 4 (1) 4.2 (2) 4.2 (3) (1)(2) 3 4 (4) (1)(3) (4) U cp1 U mp1 U cp2 U mp2 U cb U mb 1 2 U mt U ct 5 6 U mt = U mb U mp1 U mp2 5 c2014 Information Processing Society of Japan 4

5 U ct = (U cb U cp1 U cp2 ) f(u mt ) HDD 4 1 HDD 2 HDD HDD (DDR2-SDRAM) 1, 24.4 (4) 2 HDD 4 DDR2-SDRAM MPEG2 H.264 HDD HDD HDD 4.4 (1) (3) HDD HDD ( ) HDD HDD HDD HDD HDD HDD ~ 4.1% 10% c2014 Information Processing Society of Japan 5

6 SDRAM ( ) CT MRI M2M(Machine to Machine) IoT(Internet Of Things) % 100% HDD c2014 Information Processing Society of Japan 6

7 . Vol.1 pp.59-64(2008). 16),, DRAM/ LSI,, pp (1998).. 17) 49 pp (2008). 1) B. Juurlink, I. Antochi, D. Crisu, S. Cotofana, and S. Vassiliadis, GRAAL: A framework for low-power 3D graphics accelerators, IEEE Comput. Graph. Appl., vol.28, no.4, pp.63-73, ) D. Crisu, S. Cotofana, and S. Vassiliadis, A hardware / software co-simulation environment for graphics accelerator development in ARM-based SOCs, Proc. 13 th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC, ) PSI-NSIM: CPSY (2007). 4) Gerd Behrmann, Alexandre David, Kim Guldstrand Larsen, Paul Petterson and Wang Yi, Developping UPPAAL over 15 years, Software: Parctice and Experience, Vol. 41, Issue 2, pp , 2011.i 5) Sebastian Kupferschmid, Martin Wehrle, Bernhard Nebel and Andreas Podelski, Faster Than Uppaal?, CAV 2008, pp , ) Goran Frehse, Colas Le Guernic, Alexandre Donze, Scott Cotton, Rajarshi Ray, Olivier Lebeltel, Rodolfo Ripado, Antoine Girard, Thao Dang and Oded Maler, SpaceEx: Scalable Verification of Hybrid Systems, CAV 2011, pp , ) NS-2. SS 109(170) pp37-42, ) Alexandre David, Kim Guldstrand, Larsen, Axel Legay, Marius Mikucionis and Zheng Wang, Time for Statistical Model Checking of Realtime Systems, Proceedings of the 23rd International Conference on Computer Aided Verification (CAV 11), ) M. Kwiatkowska, G. Norman and D. Parker, PRISM 4.0: Verification of Probabilistic Real-Time Systems, CAV, pp , ) A.S. OS DOS OS Amoeda ) C.L. Liu and J.W. Layland, Scheduling algorithms for multiprogramming in a hard-real-time environment, J. Association for Computing Machinery, vol.20, no.1, pp.46-61, Jan ) M. Jun, K. Bang, H. Lee, N. Chang, and E. Chung, Slack-based bus arbitration scheme for soft real-time constrained embedded system, Proc. 12th Asia and South Pacific Design Automation Conference(ASPDAC2007), pp , ) K. Lahiri, A. Raghunathan, and G. Lakshminarayana, LOTTERYBUS: A new high-performance communication architecture for system-on-chip designs, Proc. 38th Design Automation Conference(DAC2001), pp.15-20, ) C.H. Pyoun, C.H. Lin, H.S. Kim, and J.W. Chong, The efficient bus arbitration scheme in SoC environment, Proc. 3rd IEEE International Workshop, pp , June-July ) / CMP c2014 Information Processing Society of Japan 7

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2. CABAC CABAC CABAC 1 1 CABAC Figure 1 Overview of CABAC 2 DCT 2 0/ /1 CABAC [3] 3. 2 値化部コンテキスト計算部 2 値算術符号化部 CABAC CABAC H.264 CABAC 1 1 1 1 1 2, CABAC(Context-based Adaptive Binary Arithmetic Coding) H.264, CABAC, A Parallelization Technology of H.264 CABAC For Real Time Encoder of Moving Picture YUSUKE YATABE 1 HIRONORI