設計現場からの課題抽出と提言なぜ開発は遅れるか？その解決策は？

Size: px

Start display at page:

Download "設計現場からの課題抽出と提言なぜ開発は遅れるか？その解決策は？"

きのこつまがみ
6 years ago
Views:

1 Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 1

2 WG1: NEC STARC STARC Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 2

3 WG1 ITRS Design System Drivers SoC EDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 3

4 Design System Drivers Design WG1 Design process, System-level design, Logical/physical/circuit design, Design verification, Design for test System Drivers System Drivers ORTC ITRS ORTC =Overall Roadmap Technology Characteristic LSI SoC SoC Multi-Technology High-Performance, Cost-Driven Processor Mixed-Signal Memory SoC Low Power PDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 4

5 Canonical Design Flow ITRS US/EU Canonical Design Flow SoC WG ITRS ITRS» Canonical Design Flow» RTL SW/HW Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 5

6 Full/Semi-Automated Handcraft Files, Documents System Requirement Analysis System Requirement Specification System Function Design System Architecture Design HW Specification SW Specification Micro Architecture Design(Block Partition) Block Level Specification RTL Design Software Development Modeling Verification RTL Models & Constraints Logic synthesis & Place-and-Route Mask Data Hardware Development Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 6

7 RTL System Requirement Analysis System Requirement Specification Full/Semi-Automated Handcraft Files, Documents System Function Design System Architecture Design HW Specification SW Specification Micro Architecture Design(Block Partition) Modeling Verification Changed Behavior Models & Constraints RTL Synthesis RTL Models & Constraints Software Development Logic synthesis & Place-and-Route Hardware Development Mask Data Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 7

8 HW/SW System Requirement Analysis Full/Semi-Automated Handcraft Files, Documents System Requirement Specification System Function Design Modeling Verification Changed System Behavior Model Design Constraint HW/SW Co-Synthesis Behavior Models & Constraints RTL Synthesis RTL Models & Constraints SW Source Code Software Development Logic synthesis & Place-and-Route Mask Data Hardware Development Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 8

9 WG1 WG1 SoC SoC 2003 ITRS SoC Time-To-Market Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 9

10 WG1 ITRS Design System Drivers SoC EDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 10

11 Time-To-Market SoC IP EDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 11

12 SoC SoC SoC R. Collett, Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 12

13 SoC Source: Aart de Geus, Chairman & CEO of Synopsys, Boston SNUG keynote address Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 13

14 WG1 SoC SoC Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 14

15 85 EDA CAD Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 15

16 Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 16

17 WG1 ITRS Design System Drivers SoC EDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 17

18 IP Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 18

19 Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 19

20 LSI Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 20

21 IP Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 21

22 EDA CAD EDA EDA RTL Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 22

23 EDA 100% = Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 23

24 EDA LSI LSI EDA LSI Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 24

25 Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 25

26 : Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 26

27 WG1 ITRS Design System Drivers SoC EDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 27

28 SoC SoC SoC CMM 1 SoC CMM = The Capability Maturity Model SoC Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 28

29 EDA CAD EDA EDA Next Next EDAEDA EDA EDA EDA EDA EDA ASIC EDA EDA EDA EDA ESD EDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 29

30 CMOS IR A B C A B SoC C Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 30 D

31 WG1 ITRS WG1 SoC EDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 31

スライド 1

スライド 1 SoC -SWG ATE -SWG 2004 2005 1 SEAJ 2 VLSI 3 How can we improve manageability of the divergence between validation and manufacturing equipment? What is the cost and capability optimal SOC test approach?

設計現場からの課題抽出と提言 なぜ開発は遅れるか？その解決策は？

設計現場からの課題抽出と提言なぜ開発は遅れるか？その解決策は？