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1 MPEG Applications HDTV HDTV: High Definition TV 1000 SDTV: SDTV Standard Definition TV 100 DVD DVD: Digital Video Decoder VP VP: 10 Video Phone Memory Capacity (Mbit) Data Rate (MB/s)

2 µ

3 256b IOR pairs Redundancy 256b IOW pairs Fuse Elements Bank0 Bank1 Bank2 Bank3 16M bit Memory Array Center Row/Col. Row/Col. Decoder Decoder Control 16M bit Memory Array Redundancy 256b IOR pairs Fuse Elements 2Mbit Array Unit 256b IOW pairs 32MbitSDRAM I/O I/F I/O I/F Voltage Generator

4 Write Port Read Port CSLW CSLR BL /BL BL /IOW IOW /BL /IOR IOR a : Write P ort : Read Port SA Band Cross Portion EQ /EQ EQ EQ EQ EQ Shared Gate LCS W LS An GCSW GSAn SA Driver GSAp LS Ap GCSR Shared LCS R Gate EQ EQ EQ EQ /EQ EQ 128Kb 128Kb Array Arra y Sense Amplifier Sens e Amplifier 128Kb 128Kb Array Arra y b Sub-word Driv. Sub-word Driv

5 Cross Portion Sub-block15 LCS R7-4 Sub-block14 LCS W SA 128 SA 128Kb 128Kb Arra y Arra y Row & Col. Sub-block1 Decoder 128 SA 128 SA Sub-block LCS R0-3 2-way LCS W0-3 Select Center Control Test & Interface 256/128/64/32 D 256/128/64/32 Q User Logic IO Sub-word Driv. 8Kb Array Spare IOR Spare IOW IOR 0-31 IOW 0-31 Sub-word Driv. IOR IOW Sub-word Driv

6 Vdd Read Data PAE YA-odd YA-eve n Reset a /Write Data YA-o d d IOW<0 > /IOW<0> IOW<1 > Write Data /IOW<1> YA-eve n WDE b /IOW<0> /IOW<1> IOW<0 > IOW<1 >

7 V pp P2 P1 A V pp OUT V dd IN a (A) This Work (V) Conv. IN 27% Time (s) b I pp Voltage

8 V ref Act Ext. V dd P1 /BE Int. V dd Decouple C Ext. V dd

9 (V) SWL BL Pair Sense Enable /BE Pre -boost Int. Vdd2 25% non -boost (s) Ext.Vdd1=2.5V Int.Vdd1=1.5V Ext.Vdd2=1.0V Int.Vdd2=1.0V Voltage Generator Memory Array 16Mbit Read/Write I/O I/F Row/Col. Decoder Memory Array 16Mbit Read/Write I/O I/F Center Control a PDE Ext.V dd1 =2.5V VDC Int.Vdd1 =1.5V Ext.V dd2 =1.0V N2 N1 Int.V dd2 =1.0V b

11 µa V(Vol. Gen) V(IO&IF) (ua) µa 1.0V(control) 100 Vpp(Row/Col.) V(Row/Col.) 0 normal power-down stand-by stand-by Current (µa)

12 Block Select Int. Row Add. Spare Enable Normal Enable etc. Right/Left simultaneously External Row Address Judgment Circuit Spare enable internal row addess Fuse Box Redundant Capable Region (4-Sub Block Array) Defective WL (512WL + 1Spare WL) x 4 Spare WL Sub-Block Array Unit Yield (Arb. unit) This Work Previous Generation Bit defect model Defect Number (Arb. unit) b

13 130GIO = (64GIO + 1 Spare GIO) x 2 Redundant Capable Region (4-Sub Array Block) Defective GIO Spare GIO Shift Pre-Amplifier Switch Switch Redundancy Signals Decoder 64I/O = 32I/O x 2 DRAM Memory Array Periphery

15 Scan out<0> Scan out<1> Scan out<2> Scan in<0> Scan in<1> I/O(Up) Scan in<2> Scan in<3> Memor Control y Scan in<4> Array Scan in<5> Scan in<6> Scan out<4> Scan out<5> Scan out<6> I/O(Down) SCAN CLK(master) CLKQ Data-Out Data(0) Data(1) CLK(master) CLKQ Data-Out Data(0) Data(1) CLKT Latch CLKT Latch Data-Out Data(0) Data(1) Data-Out Data(0) (DMA) tac (DMA) tac Pass Error

16 Category Design Rule µ µ µ µ

17 DRAM Logic 4th Cu 3rd Cu 3rd Cu 2nd Cu 2nd Cu Storage Node 1st Cu 1st Cu BL (W) Stacked Contact WL Trench Isolation Poly-Metal Gate µ

19 CLK /RAS /CAS Dout Act Read 3 CLKs (latency) + 2 CLKs (DMA) Time (5ns/div.) 1.0V/div. 0.5V/div. (VCC) V +**************************+ 1.4V +. ************************+ 1.3V +. ***********************+ 1.2V +. **********************+ 1.1V +..********************+ 1.0V +...******************+ 0.9V +... **************+ 0.8V ****+ 0.7V V V ns 21.0ns 17.5ns (trac)

20 Technology 0.13 um 4-level Cu embedded DRAM technology Supply Voltage 1.0V, 2.5V Maximum Core size 64Mb (Granularity size : 2Mb) Core Size 18.9 mm 32Mb, 33.4 mm 64Mb Cell Efficiency 32Mb, 64Mb Column Access 230 burst operation, 32Mb capacity Number of Banks 1 / 2 / 4 Number of I/Os 32b / 64b / 128b / 256b, separated / common I/O Interface common SDRAM / SDRAM-Like DFT DMA with TACM mode / SCAN / Auto-BI

21 µ D30V Audio Host Audio signal media-processor I/F I/F core Video Bit-stream Video signal video processing Bit-stream I/F I/F core DRAM I/F Dual communication 32b 32b port 32Mbit 32Mbit DRAM DRAM

23 1500 * 64Mbit DRAM x 2 DRAM 1000 I/O DRAM 500 Logic Logic & & SRAM SRAM 0 Encoder LSI + External DRAM* This work Power (mw)

24 Technology 0.13µm triple-well 4-level copper embedded DRAM Die size 10.71mm x 9.26mm ( 99.17mm 2 ) Number of transistors Cell size DRAM : 0.29µm 2 Power supply 12 million (3Mgates) and 64Mbit DRAM SRAM : 2.77µm 2 Internal I/O : 1.5V : 3.3V Clock frequency Power consumption Package 27MHz / 54MHz / 81MHz / 162MHz Clock input : 27MHz 0.7W (estimated) 256-pin BGA µ

25 µ

26 1) K. Nagata, IMT-2000 terminal and its requirements for device technologies, in Symp. VLSI Circuits Dig. Tech. Papers, June 2000, pp ) T. Nishikawa et al., A 60MHz 240mW MPEG-4 Video-Phone LSI with 16Mb Embedded DRAM, in ISSCC Dig. Tech. Papers, Feb. 2000, pp ) T. Hashimoto, et al., A 90mW MPEG4 Video Codec LSI with the Capability for Core Profile, in ISSCC Dig. Tech. Papers, Feb. 2001, pp ) C W. Yoon et al., An 80/20-MHz 160-mW Multimedia Processor Integrated with Embedded DRAM, MPEG-4 Accelerator, and 3-D Rendering Engine for Mobile Applications, IEEE J. Solid-State Circuits, vol. 36, No. 11, Nov. 2001, pp ) T. Namekawa, et al., Dynamically Shift-Switched Dataline Redundancy Suitable for DRAM Macro with Wide Data Bus, Symp. On VLSI Tech. Dig. Tech. Papers, June 1999, pp ) A. Yamazaki et al., A 56.8GB/s 0.18µm Embedded DRAM Macro with Dual Port Sense Amplifier for 3D Graphic Controller, in ISSCC Dig. Tech. Papers, Feb. 2000, pp ) A. Yamazaki, et al., A 5.3-GB/s 32Mb Embedded SDRAM Core with Slight-Boost Scheme, Symp. On VLSI Tech. Dig. Tech. Papers, pp , ) A. Yamazaki, et al., A 5.3-GB/s Embedded SDRAM Core with Slight-Boost Scheme, IEEE J. Solid-State Circuits, vol. 34, No. 5, May 1999, pp ) S. Tomishima et al., A 1.0V 230MHz column access embedded DRAM for portable MPEG applications, in ISSCC Dig. Tech. Papers, Feb. 2001, pp ) S. Tomishima et al., A 1.0V 230MHz column access embedded DRAM for portable MPEG applications, IEEE J. Solid-State Circuits, vol. 36, no. 11, Nov. 2001, pp ) H. Kikukawa, et al., 0.13µm 32M/64M embedded DRAM core with high efficient redundancy and enhanced testability, in Proc. 27 th European Solid-State Circuits Conference, Villach, Austria, Sept. 2001, pp ) H. Kikukawa, et al., 0.13µm 32Mb/64Mb embedded DRAM Core with High Efficient Redundancy and Enhanced Testability, IEEE Journal of Solid-State Circuits, Vol.37, NO.7, July ) N. Takenaka et al., High density embedded DRAM technology with 0.38µm pitch in DRAM and 0.42µm pitch in LOGIC by W/PolySi gate and Cu dual damascene metallization, in Symp. VLSI Technology Dig. Tech. Papers, June 2000, pp ) T. Yabe, et al., A Configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator, in ISSCC Dig. Tech. Papers, Feb. 1998, pp ) T. Kimura, et al., 64Mb 6.8ns Random Row Access DRAM Macro for ASICs, in ISSCC Dig. Tech. Papers, Feb. 1999, pp ) S. Kumaki et al., A 99-mm 2, 0.7-W, single-chip MPEG-2 422@ML video, audio and system

27 encoder with a 64Mb embedded DRAM macro for portable 422P@HL encoder system, in IEEE CICC Dig. Tech. Papers, pp , May ) M. Mizuno et al., A 1.5-W single-chip MPEG2 MP@ML encoder with low power motion estimation and clocking, in ISSCC Dig. Tech. Papers, Feb. 1997, pp ) E. Ogura et al., A 1.2W single-chip MPEG2 MP@ML video encoder LSI including wide search rage motion estimation and 81MOPS controller, in ISSCC Dig. Tech. Papers, Feb. 1998, pp ) E. Miyanaga et al., A 100-mm 2, 0.95-W, single-chip MOPEG2 MP@ML video encoder with a 128 GOPS motion estimator and a multi-tasking RISC-type controller, in ISSCC Dig. Tech. Papers, Feb. 1998, pp ) T. Minami et al., A single-chip MPEG2 MP@ML video encoder LSI with multi-chip configuration for a single board MP@HL encoder, in proc. Hot Chips X, Aug. 1998, pp ) S. Kumaki et al., A single-chip MPEG2 422@ML video, audio and system encoder with a 162MHz media-processor and dual motion estimation cores, in IEEE CICC Dig. Tech. Papers, pp , May ) M. Mizuno et al., A 1.5W single-chip MPEG-2 encoder with low power motion estimation and clocking," IEEE J. Solid-State Circuits, vol. 32, no. 11, Nov. 1997, pp ) E. Ogura et al., A 1.2W single-chip MPEG-2 MP@ML video encoder LSI including wide search range motion estimation and 81-MOPS controller, IEEE J. Solid-State Circuits, vol. 33, no. 11, Nov. 1998, pp ) E. Miyagoshi et al., A 100mm W single chip MPEG-2 MP@ML video encoder with 128 GOPS Motion Estimation and a multi-tasking RISC-type controller, in ISSCC Dig. Tech. Papers, Feb. 1998, pp ) M. Ikeda et al., Super ENC: MPEG-2 422@ML video. audio, and system encoder with a 162MHz media-processor and dual motion estimation cores, in IEEE CICC Dig. Tech. Papers, pp , May ) S. Kumaki et al., A single-chip MPEG2 422@ML video, audio and system encoder with a 162MHz media-processor and dual motion estimation cores, in IEEE CICC Dig. Tech. Papers, pp , May ) N. Takenaka et al., High Density Embedded DRAM Technology with 0.38um Pitch in DRAM and 0.42um Pitch in LOGIC by W/Poly-Si Gate and Cu Dual Damascene Metallization, Symp. VLSI Tech. Dig. Papers, pp.62-63, June ) S. Kumaki et al., A 99-mm 2, 0.7-W, single-chip MPEG-2 422@ML video, audio and system encoder with a 64Mb embedded DRAM macro for portable 422P@HL encoder system, in IEEE CICC Dig. Tech. Papers, pp , May ) S. Tomishima et al., A 1.0V 230MHz column access embedded DRAM for portable MPEG applications, in ISSCC Dig. Tech. Papers, Feb. 2001, pp

28 ) T. Matsumura et al., A single-chip MPEG-2 422P@ML video, audio and system encoder with a 162MHz media-processor and dual motion estimation cores, IEICE Trans. Electronics, vol.e84-c, no.1, pp , Jan.2001.

I/F Memory Array Control Row/Column Decoder I/F Memory Array DRAM Voltage Generator

- - 18 I/F Memory Array Control Row/Column Decoder I/F Memory Array DRAM Voltage Generator - - 19 - - 20 N P P - - 21 - - 22 DRAM - - 23 a b MC-Tr avcc=2.5vvbb=-1.5vvpp=4.0v bvcc=1.7vvbb=-1.0vvpp=3.0v