Mixed Signal SOC Circuit Design
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1 1 STRJ WS: March 4, 2004
2 STRJ WS: March 4,
3 STRJ WS: March 4,
4 STRJ WS: March 4, DVD TV 12 LSI ()
5 STRJ WS: March 4,
6 PC, Flash, CCD pp STRJ WS: March 4,
7 PC = Analog base Digital base PC WideTV Internet TV Digital TV PC STRJ WS: March 4,
8 STRJ WS: March 4, Conventional semiconductor makers semiconductor technology base CPU Maker DRAM Maker ASIC Maker Analog Maker PC CPU CPU DRAM DRAM Logic Logic (ASIC) (ASIC) Network Network Analog Analog Not appeared yet System, Application DVD CPU CPU DRAM DRAM Logic Logic (ASIC) (ASIC) Network Network Analog Analog Future semiconductor makers Application base DTV CPU CPU DRAM DRAM Logic Logic (ASIC) (ASIC) Network Network Analog Analog
9 STRJ WS: March 4,
10 STRJ WS: March 4, TV / DVD,
11 STRJ WS: March 4,
12 STRJ WS: March 4, HDTV M. Nakajima, et al., A 400MHz 32b Embedded Microprocessor Core AM34-1 with 4.0GB/S Cross-Bar Switch for HDD Flash SDRAM, ISSCC, Dig. of Tech. Papers, pp , RDRAM 0.13um CMOS, 6Cu 35M Trs. CLK: 400MHz
13 10, Audio Video Virtual Reality Pentium III 0. 1 Voice Recognition MPEG-1 Encoder MPEG-2 Decoder MPEG-2 Encoder HDTV Decoder Performance (GOPS) Performance (GOPS) 0.01 FAX/Modem Sound TV-Conference MPEG-1 Decoder HDTV Encoder HDTV Encoder 3D D Graphics Real time 3D Graphics STRJ WS: March 4,
14 Architecture optimization based on system analysis is a key. Dedicated parallel bus Short period interruption Cash optimization FLASH SDRAM Ext. bus Cont. SDRAM Cont. SRAM 8KB Instruction buss Data bus DMA cont. I/O bus for digital TV Crossbar switch I-Cache 4way,8KB D-Cache 4way,4KB MCU (AM33) 121MHz Front End Transport Decoder Stream bus STB peripheral I/O AV Decoder (Media PU) Video Audio A. Matsuzawa, System On a Chip and low Power Technologies for Digital Consumer Electronics, Cool Chips, Proceedings, pp , 2000 SDRAM STRJ WS: March 4,
15 Occupation of external bus (%)Occupation of external bus (%) PC AV 70% MCU Inst. access MCU Data access Bus-master A. Matsuzawa, System On a Chip and low Power Technologies for Digital Consumer Electronics, Cool Chips, Proceedings, pp , 2000 Crossbar switch STRJ WS: March 4,
16 STRJ WS: March 4,
17 STRJ WS: March 4, MPEG4 Codec 0.18um e-dram 31M Tr 90 T. Hashimoto, et al., A 90mW MPEG4 Video Codec LSI with the Capability for Core Profile, ISSCC, Dig. of Tech. Papers, pp , MPEG4 Decoder 0.18um CMOS 11M Tr 11 mw@27/54mhz 15fps (Core@L1 decode) 30 fps (Simple@L3 decode) 15fps (Core@L1 decode) M. Ohashi, et al., A 27MHz 11.1 mw MPEG4 Video Decoder LSI for Mobile Application, ISSCC, Dig. of Tech. Papers, pp , 2002.
18 VCE (Video Codec Engines) 1.5 GOPS: 12 GOPS: 6 GOPS: T. Hashimoto, et al., A 90mW MPEG4 Video Codec LSI with the Capability for Core Profile, ISSCC, Dig. of Tech. Papers, pp , ME VLC DCT VLD PNR PAD CAD COMP LM LM IDCT LM LM LM CAD HW Engine 6.1% Software Programmable DSP PAD 26.5% DSP Core Inst.Mem DataMem MIF (Memory I/F) DRAM (2Mb) Main Sub Graph. Filter DRAM (2Mb) Video Input Video Output HIF (Host I/F) DRAM (16Mb) COMP Texture Decoding Core@L1 Decoding 6.8% 63% Kcycles WITH the EnginesWITHOUT the Engines 24% Mcycles STRJ WS: March 4,
19 STRJ WS: March 4,
20 STRJ WS: March 4, LSI MPU DSP Dedicated LSI 16 Parallelism 2 96 GOPS Pd (mw) Pd (mw)/gops order s difference 12 Courtesy, Prof. Brodersen, UCB
21 MPU/MCU Trend of Performance/Power on 32-bit MPU/MCU Performance (MIPS) AM32 Core/ MIPS/W AM30 /33 Embedded 100 MIPS/W AM31 /66 AM33 /200 AM33 /150 AM34 / MIPS/W PPC750/400 PPC750/266 Game Oriented MobileOriented Alpha/600 UltraSPARCII/300 MobilePentium II/300 MMX Pentium/233 EWS/PC Pentium II/450 Celeron/400 1 MIPS/W Controller Oriented PC/EWS Oriented Power Consumption (W) STRJ WS: March 4,
22 LSI Centralized: Current general purpose MPU Memory Command ALU Data Bus MIPS=( 2 or 3) x Clock needs higher clock frequency needs longer wire line needs high speed devices Long wires Distributed: Parallel computing M M M M M M M M Large power dissipation Tough timing skew, yet low processing ability L L L L L L L L Change the LSI architecture!! Locate every needed circuits in the neighborhood STRJ WS: March 4,
23 STRJ WS: March 4, TAT CPU SiP DTV DTV DVD DVD DTV DTV DTV DTV DTV DTV DVD DVD DVD DVD DVD DVD DTV DTV DVD DVD SiP) SiP)
24 STRJ WS: March 4,
25 STRJ WS: March 4, (DTV, ADSL, Ethernet, USB HDD, DVD, DVC Variable Variable Gain Gain Amp. Amp. Analog Analog Filter Filter A A to to D D Converter Converter Digital Digital FIR FIR Filter Filter Viterbi Viterbi Error Error Correction Correction Data Out Data In (Erroneous) Pickup signal Voltage Voltage Controlled Controlled Oscillator Oscillator Clock Clock Recovery Recovery Analog circuit Data Out (No error) Digital circuit
26 STRJ WS: March 4, DVD DVD 0.13um 0.13um, Cu 6Layer, 24MTr Okamoto, et al., ISSCC 2003
27 STRJ WS: March 4, RF DAB IEEE 1394, USB, Blue tooth, Wireless LAN CS/BS Digital TV ITS ADSL, FTTH Network HII Station Home network Digital TV Ethenet W-CDMA Home Server DVC DVD
28 CMOS MOS Frequency (Hz) 100G 50G 20G 10G 5G 2G 0.35 um Cellular Phone 0.25 um 0.18 um CDMA 0.13 um f T 5GHz W-LAN f T : CMOS f T : Bipolar (w/o SiGe) /10 (CMOS ) RF circuits f T /60 (CMOS ) Digital circuits Performance (Log) Integration Speed 1 2 L 1 L 1.5 1G 500M 200M 100M Year IEEE 1394 D R/C for HDD Scaling 1 Design Rule (Log) Dynamic range 1.5 L STRJ WS: March 4,
29 STRJ WS: March 4, V 0.13um Technology node (0.1um) Supply voltage (V) Digital Upper Technology node Analog (Upper) Analog (Lower) Digital (Lower) ITRS 99
30 STRJ WS: March 4, SNR (db) ( ) 1, 2, ( ) 2, 2, ( ) 3, 2, ( ) 5, 2, bit 12bit N=2 10bit (pf) V FS =5V V FS =3V V FS =2V V FS =1V kt/c 2 V n = nkt C n V FS SNR( db) 2 CV FS = 10log 8nkT
31 STRJ WS: March 4, I/O I/O 1.A. Matsuzawa, RF-: Expectations and required condition, IEEE Transaction on Microwave Theory and Techniques, Vol.50, No.1, pp , Jan I/O Analog Digital 0.35um : 1 Wafer cost increases 1.3x for one generation Chip area Chip cost
32 STRJ WS: March 4,
33 STRJ WS: March 4, Mon 12 Mon 12 Mon 6 Mon 6 Mon 3 Mon Sales (A.U) 6x DVD ROM 8x DVD ROM 16x 12x DVD ROM DVD ROM 2 nd G 2.6G RAM Combo Combo First DVD ROM 2.6G RAM 4.7G RAM 97 Time 00
34 STRJ WS: March 4, Process dev. Conventional System target. Cell Lib. Dev. Design modif. Process modif. System target Advanced System driven! Process dev. Cell Lib. Dev. Collaboration design Unconformity Spec. Cost and Time MP to solve boundary problems A. Matsuzawa, 26.2 How to Make Efficient Communication, Collaboration, and Optimization from System to Chip [p. 417], DAC 2003 design MP Shorten dev. TAT
35 STRJ WS: March 4, Reliability High Idd Low Ioff Low-k Cu STI Analog Cell height HP Analog HP I/O Cell Lib. Device Process High yield Quick ramp-up Analog control Mixed signal Clocking Power routing Design 技術ロードマップの作成 Fab Package A. Matsuzawa, 26.2 How to Make Efficient Communication, Collaboration, and Optimization from System to Chip [p. 417], DAC 2003 Mixed signal Large system s verification System EDA Test POE Low inductance Future demands, issues, and solutions EMI sim Cross-talk sim Mixed signal sim Iddq test Wafer burn-in Mixed signal
36 STRJ WS: March 4,
37 STRJ WS: March 4, CPU CPU
38 STRJ WS: March 4, CPU CPU CPU CPU Low-K CPU
39 70% CPU ITRS 2001 Edition, pp , pp.26 STRJ WS: March 4,
40 STRJ WS: March 4, TV 90nm 1V 1.2V 1.5V 1.8V 2.5V 3V 5V Operating Voltage (V) Delay time (Arbitral) 50 Low leak (3pA/um) 10 5 Middle leak (1nA/um) Constant Vt/VDD Constant VT Scaled VT Design rule (um) Current (A) 0.13um (1.5V) Generic Leak current Active current 0.1um (1.0V) Generic Leak current Active current
41 STRJ WS: March 4, TV LSI Ion IoffVDD Vt Low-k
42 STRJ WS: March 4, MRAM, PRAM, DRAM Chip On Chip FeRAM
43 STRJ WS: March 4, Chip On Chip CPU 30um 60um CoC 1mm SRAM, DRAM T. Ezaki, et al., ISSCC 2004, pp.140
44 STRJ WS: March 4, ADC, DAC, Low Noise Amp, VCO MIM V T 1/f f T, fmax RF MEMS
45 STRJ WS: March 4, CMOS Wireless LAN, a/b/g 0.25um, 2.5V, 23mm 2, 5GHz Discrete-time Bluetooth 0.13um, 1.5V, 2.4GHz M. Zargari (Atheros), et al., ISSCC 2004, pp.96 K. Muhammad (TI), et al., ISSCC2004, pp.268
46 Analog Architecture: Super Heterodyne Larger power, cost RF IRF LNA RF IRF 1 st Mixer IF SAW VGA 2 nd Mixer LPF ADC To Digital 1-2 GHz GHz 250 MHz 20 MHz 1 st Synthesizer 2 nd Synthesizer Digital architecture: Direct conversion with discrete-time processing LNA 1-2 GHz Sampled data LPF ADC LPF Quantizer Digital processing Mixer OSC LPF Bluetooth receiver 0.13um CMOS 1.5V Synthesizer 1-2 GHz K. Muhammad (TI), et al., ISSCC2004, pp.268 STRJ WS: March 4,
47 STRJ WS: March 4, RF RF Future cellular phone needs 11 wireless standard!! Multi-standards and multi chips IMT-2000 RF GSM RF IMT-2000 BB GSM BB Current Bluetooth RF GPS RF Unification Bluetoth BB GPS BB MCU Power Future Yrjo Neuvo, ISSCC 2004, pp.32 Reconfigurable RF DSP Unified wireless system
48 STRJ WS: March 4, RF MEMS switch MEMS Select or change inductance and capacitance Select signals and circuits; As a result, enables reconfigurable RF circuits J. DeNatale, ISSCC 2004, pp. 310
49 Y. Yokoyama, et al., JJAP, Vol. 42, No. 4B, pp , Sliding plate can vary inductance by 50%. Wide tunable range VCO (2.4GHz to 5.1GHz) has been realized. Sliding 20µm 4µm Conductor plate h=10µm x 450µm 2.4GHz to 5.1GHz TITech. Masu Lab. 50% STRJ WS: March 4,
50 Size (µm), Voltage(V) MPU Lg Junction depth Gate oxide thickness Min. V supply V Analog limit 0.6V Error Rate limit (Digital) Electric energy vs. Thermal energy 10 nm Wave length of electron 3 nmdirect-tunneling limit in SiO nmdistance between Si atoms Year STRJ WS: March 4,
51 STRJ WS: March 4, PC CPU PC I/O
52 STRJ WS: March 4, ,PC CPU SiP RF MEMS
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2008/1/15 (12) 1 2008/1/15 (12) 2 (12) http://ssc.pe.titech.ac.jp 2008/1/15 (12) 3 VLSI 100W P d f clk C V 2 dd I I I leak sub g = I sub + I g qv exp nkt exp ( 5. 6V 10T 2. 5) gd T V T ox Gordon E. Moore,
Mixed Signal SOC Circuit Design
デジタル情報家電用 SoC 技術の動向とテクノロジーへのインパクト 松澤昭 東京工業大学 大学院理工学研究科 電子物理工学専攻 1 内容 デジタル情報家電の時代 デジタル情報家電用 SoC メディアプロセッサー技術 ローパワー技術 アーキテクチャと消費電力 アナログ デジタル混載技術 SoC の開発体系 テクノロジーへのインパクト STRJ WS: March 4, 2004, WG6 2 内容 デジタル情報家電の時代
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STRJ WS: March 4, 2003, 設計 TF/PIDS/FEP クロスカット 設計 TF/PIDS/FEP クロスカット報告 低電力 SoC のロードマップ - モバイルマルチメディアへのアプローチ - 設計 TF 主査日立製作所内山邦男
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