- - 18
I/F Memory Array Control Row/Column Decoder I/F Memory Array DRAM Voltage Generator - - 19
- - 20
N P P - - 21
- - 22
DRAM - - 23
a b MC-Tr avcc=2.5vvbb=-1.5vvpp=4.0v bvcc=1.7vvbb=-1.0vvpp=3.0v µ - - 24
a b - - 25
BSG a b Vcc=1.7VVsi=0.2VVbb=-0.8VVpp=3.0V) BSG - - 26
Word Line Line BSG Conv. BL Pair Sense GND GND - - 27
µ µ - - 28
I-leak avcc b - - 29
MC-Tr - - 30
a b - - 31
a b - - 32
- - 33
BSG a bdms - - 34
avcc b c - - 35
- - 36
- - 37
CDS a b - - 38
A 1/2-VCC DRAM 1/2-VCC, MOS 1/2-VCC / DRAM / 1.0V a b - - 39
- - 40
- - 41
µ - - 42
- - 43
- - - 44
- - 45
C - - 46
- - 47
D - - 48
agnd bvbb c - - 49
- - 50
- - 51
a bgnd-well c - - 52
- - 53
A StretchableMemoryMatrix DRAM 16M STDRAM - - 54
DRAM DRAM 16M X Y 12 40964096 1 4096 13X/11Y 2048 2 14X/10Y 1024 1/4 15X/9Y 512 1/8 X STretchableMemory Matrix) DRAM STDRAM, B16M-STDRAM IO 16Mb-STDRAM 32k 256 128 - - 55
15X/9Y 4 128k 1/128 / X Y I/O I/O N MOS I/O I/O I/O X /Y =15/9 16us/ 512ms IO - - 56
C 16M DRAM 16M STDRAM X /Y X X /Y 15/9 X /Y 12/12 1/2 1/4 8 2 16M DRAM 1/2 16M STDRAM 512 1/8 - - 57
V pp A V pp OUT V dd IN µ - - 58
V pp IN L P2 A H P1 V A pp OUT B L V dd IN C H OUT H a b a b - - 59
V pp V pp OUT V dd IN - - 60
VDC a - - 61
VDC a b - - 62
VDC VDC - - 63
VDC - - 64
VDC - - 65
- - 66
- - 67
VDC a b - - 68
VDC a VDC bmm-vdc cmm-vdc - - 69
a b - - 70
VCI - - 71
Ext. V dd Ext. V dd P1 /BE V ref Int. V dd Act Decouple C ACT SE BE Ext.Vdd Int.Vdd GND - - 72
- - 73
- - 74
1) K. Itoh et al., An experimental 1Mb DRAM with on-chip voltage limiter, in ISSCC Dig. Tech. Papers, Feb. 1984, pp. 282-283. 2) T. Furuyama et al., A new on-chip voltage converter for submicrometer high-density DRAM s, IEEE J. Solid-State Circuits, vol. 24, June 1986, pp. 473-441. 3) H. Hidaka et al., A 34ns 16Mb DRAM with controllable voltage down-converter, IEEE J. Solid-State Circuits, vol. 27, No. 7, July 1992, pp. 1020-1027. 4) M. Horiguchi, et al., Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-scale LSI s, Symp. VLSI Circuits Digest of Tech. Papers, pp. 47-48, June 1993. 5) T. Yamagata et al., Circuit design techniques for low voltage operating and/or giga-scale DRAMs, in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 248-249. 6) T. Yamagata et al., Low voltage circuit design techniques for battery-operated and/or giga-scale DRAM s, IEEE J. Solid-State Circuits, vol. 30, Nov. 1995, pp. 1183-1188. 7) M. Asakura et al., A 34ns 256Mb DRAM with boosted sense-ground scheme, in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 140-141. 8) M. Asakura et al., An experimental 256-Mb DRAM with boosted sense-ground scheme, IEEE J. Solid-State Circuits, vol. 29, Nov. 1994, pp. 1303-1309. 9) S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981. 12) Y. Tsukikawa et al., An efficient back-bias generator with hybrid pumping circuit for 1.5 V DRAM s, Symp. On VLSI circuit Dig. Tech. Papers, pp. 85-86, June 1993. 13) T. Sakurai et al. Hot-carrier generation in submicrometer VLSI environment, IEEE J. Solid-State Circuits, vol. SC-21, Feb. 1986. 14) T. Tsuruda et al., High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI, in IEEE CICC Dig. Tech. Papers, pp. 265-268, May 1996. 15) T. Tsuruda et al., High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI s, IEEE J. Solid-State Circuits, vol. 32, March 1997, pp. 477-482. 16) S. Miyano et al., Embedded DRAM SOCs and Its Application for MPEG4 Codec LSIs, in Proc. of VLSI Circuits Short Course, June 2001, pp. 101-121. 17) C-L. Hwang, et al., A 2.9ns Random Access Cycle Embedded DRAM with a Destructive Read Architecture, Symp. On VLSI circuit Dig. Tech. Papers, June 2002, pp. 174-175. 18) S.Tomishima, et al., A 1.0V 230MHz column access embedded DRAM for portable MPEG - - 75
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