MAX DS J

19-233; Rev ; 1/2 µ µ µ µ µ µ PART TEMP RANGE PIN- PACKAGE INL (LSB) AEUB -4 C to +85 C 1 µmax ±.5 BEUB -4 C to +85 C 1 µmax ±1 AEUB -4 C to +85 C 1 µmax ±.5 BEUB -4 C to +85 C 1 µmax ±1 TOP VIEW OUTA 1 1 OUTB REFA GND LDAC 2 3 4 9 8 7 REFB 5 µmax 6 Maxim Integrated Products 1

ABSOLUTE MAXIMUM RATINGS to GND...-.3V to +6V Digital Inputs to GND...-.3V to +6V REF_, to GND...-.3V to ( +.3V) Maximum Current into Any Pin...5mA ELECTRICAL CHARACTERISTI Continuous Power Dissipation (T A = +7 C) 1-Pin µmax (derate 5.6mW/ C above +7 C)...444mW Operating Temperature Range...-4 C to +85 C Storage Temperature Range...-65 C to +15 C Lead Temperature (soldering, 1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ( = +4.5V to +5.5V, GND =, V REFA = V REFB = +2.5V, R L = 5kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 12 Bits Integral Nonlinearity INL A (Note 1) ±.5 B (Note 1) ±1 Differential Nonlinearity DNL ±1 LSB Offset Error V OS (Note 2) ±5 mv Gain Error ±3 LSB Full-Scale Voltage V FS Code = FFF hex, T A = +25 C (Note 3) 4.87 4.95 4.13 V Full-Scale Temperature Coefficient TCV FS Normalized to 4.95V 2 ppm/ C Offset Temperature Coefficient TCV OS ±8 µv/ C Power-Supply Rejection PSR 4.5V 5.5V 15 2 µv DC Crosstalk (Note 4) 1 µv REFERENCE INPUT Reference Input Range V REF (Note 5).25 2.6 V Reference Input Resistance R REF Minimum with code 555 hex and AAA hex 28 37 kω Reference Current in Shutdown I REF ±1 µa MULTIPLYING MODE PERFORMANCE Reference -3dB Bandwidth, Slew-Rate Limited Input code = FFF hex, V REF _ =.5V P-P + 1.5V DC 35 khz LSB Reference Feedthrough Input code = hex, V REF _ = 3.6V P-P + 1.8V DC, f = 1kHz -8 db Signal-to-Noise plus Distortion Ratio SINAD Input code = FFF hex, V REF _ = 2V P-P + 1.5V DC, f = 1kHz 79 db 2

ELECTRICAL CHARACTERISTI (continued) ( = +4.5V to +5.5V, GND =, V REFA = V REFB = +2.5V, R L = 5kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) DIGITAL INPUT PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage V IH.7 x.3 x Input Low Voltage V IL V Input Hysteresis V HYS 2 mv Input Leakage Current Digital inputs = or ±1 µa Input Capacitance 8 pf DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR.6 V/µs Voltage-Output Settling Time To ±.5LSB, V STEP = ±4V,.25V < V OUT < ( -.25V) V 1 µs Output-Voltage Swing (Note 6) to V Ti m e Req ui r ed for Outp ut to S ettl e After Tur ni ng on V D D ( N ote 7) 7 µs Time Required for Output to Settle After Exiting Full Power- Down Time Required for Output to Settle After Exiting DAC Power- Down (Note 7) 7 µs (Note 7) 6 µs Digital Feedthrough =, f = 1kHz, V = 5V P-P 5 nv-s Major-Carry Glitch Energy 4 nv-s POWER SUPPLIES Power-Supply Voltage 4.5 5.5 V Power-Supply Current I DD (Note 8) 36 45 µa Power-Supply Current in Power- Down and Shutdown Modes Full power-down mode 1 5 I SHDN One DAC shutdown mode 19 215 Both DACs shutdown mode 26 42 µa 3

ELECTRICAL CHARACTERISTI ( = +2.7V to +3.6V, GND =, V REFA = V REFB = +1.25V, R L = 5kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 12 Bits Integral Nonlinearity INL A (Note 1) ±.5 B (Note 1) ±1 Differential Nonlinearity DNL ±1 LSB Offset Error V OS (Note 2) ±5 mv Gain Error GE ±6 LSB Full-Scale Voltage V FS Code = FFF hex, T A = +25 C (Note 3) 2.41 2.475 2.54 V Temperature Coefficient TCV FS Normalized to 2.475V 4 ppm/ C Offset Temperature Coefficient TCV OS ±8 µv/ C Power-Supply Rejection PSR 2.7V 3.6V 18 28 µv DC Crosstalk (Note 4) 1 µv REFERENCE INPUT Reference Input Range V REF (Note 5).25 1.5 V Reference Input Resistance R REF Minimum with code 555 hex and AAA hex 28 37 kω Reference Current in Shutdown I REF ±1 µa MULTIPLYING MODE PERFORMANCE Reference -3dB Bandwidth, Slew- Rate Limited Input code = FFF hex, V REF _ =.5V P-P +.75V DC 35 khz LSB Reference Feedthrough Input code = hex, V REF _ = 1.6V P-P +.8V DC, f = 1kHz -8 db Signal-to-Noise plus Distortion Ratio DIGITAL INPUTS SINAD Input code = FFF hex, V REF _ =.6V P-P +.9V DC, f = 1kHz Input High Voltage V IH.7 x 79 db V Input Low Voltage V IL.3 x V Input Hysteresis V HYS 2 mv Input Leakage Current Digital inputs = or ±1 µa Input Capacitance 8 pf DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR.6 V/µs Voltage-Output Settling Time To ±.5LSB, V STEP = ±2V,.25V < V OUT < ( -.25V) 1 µs Output-Voltage Swing (Note 6) to V 4

ELECTRICAL CHARACTERISTI (continued) ( = +2.7V to +3.6V, GND =, V REFA = V REFB = +1.25V, R L = 5kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Ti m e Req ui r ed for Outp ut to S ettl e After Tur ni ng on V D D ( N ote 7) 6 µs Time Required for Output to Settle After Exiting Full Power- Down Time Required for Output to Settle After Exiting DAC Power- Down (Note 7) 6 µs (Note 7) 5 µs Digital Feedthrough =, f = 1kHz, V = 3V P-P 5 nv-s Major Carry Glitch Energy 115 nv-s POWER SUPPLIES Power-Supply Voltage 2.7 3.6 V Power-Supply Current I DD (Note 8) 325 43 µa Power-Supply Current in Power- Down and Shutdown Modes Full power-down mode.4 5 I SHDN One DAC shutdown mode 175 2 Both DACs shutdown mode 25 4 µa TIMING CHARACTERISTI (FIGURES 1 AND 2) ( = +4.5V to +5.5V, GND =, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Clock Period t CP 74 ns Pulse Width High t CH 3 ns Pulse Width Low t CL 3 ns Fall to Rise Setup Time t S 3 ns Rise to Rise Hold Time t H ns Setup Time t DS 3 ns Hold Time t DH ns Rise to Fall Delay t 1 ns Rise to Rise Hold Time t 1 3 ns Pulse Width High t W 75 ns LDAC Pulse Width Low t LDL 3 ns Rise to LDAC Rise Hold Time t LD (Note 9) 4 ns 5

TIMING CHARACTERISTI (FIGURES 1 AND 2) ( = +2.7V to +3.6V, GND =, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Clock Period t CP 74 ns Pulse Width High t CH 3 ns Pulse Width Low t CL 3 ns Fall to Rise Setup Time t S 3 ns Rise to Rise Hold Time t H ns Setup Time t DS 3 ns Hold Time t DH ns Rise to Fall Delay t 1 ns Rise to Rise Hold Time t 1 3 ns Pulse Width High t W 75 ns LDAC Pulse Width Low t LDL 3 ns Rise to LDAC Rise Hold Time t LD (Note 9) 75 ns Note 1: Accuracy is guaranteed in the following way: V REF _ ACCURACY GUARANTEED FROM CODE TO CODE 3 1.25 2 495 5 2.5 1 495 Note 2: Offset is measured at the code closest to 1mV. Note 3: Gain from V REF _ to V OUT _ is typically 1.638 x CODE/496. Note 4: DC crosstalk is measured as follows: set DAC A to midscale, and DAC B to zero, and measure DAC A output; then change DAC B to full scale and measure V OUT for DAC A. Repeat the same measurement with DAC A and DAC B interchanged. DC crosstalk is the maximum V OUT measured. Note 5: The DAC output voltage is derived by gaining up V REF by 1.638 x CODE/496. This gain factor may cause V OUT to try to exceed the supplies. The maximum value of V REF in the reference input range spec prevents this from happening at full scale. The minimum V REF value of.25v is determined by linearity constraints, not DAC functionality. Note 6: Accuracy is better than 1LSB for V OUT = 1mV to - 18mV. Note 7: Guaranteed by design. Not production tested. Note 8: R LOAD = and digital inputs are at either or GND. V OUT = full-scale output voltage. Note 9: This timing requirement applies only to rising edges, which execute commands modifying the DAC input register contents. 6

( = +5V () = +3V (), R L = 5kΩ, C L = 1pF, V REF = +1.25V (), V REF = +2.5V (), C REF =.1µF ceramic 2.2µF electrolytic, both DACs on, V OUT = full scale, T A = +25 C, unless otherwise noted.) INL (LSB) DNL (LSB).5.4.3.2.1 -.1 -.2 -.3 -.4 -.5.25.2.15.1.5 -.5 -.1 -.15 -.2 -.25 4 35 3 25 2 15 1 5 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE () 5 1 15 2 25 3 35 4 DIGITAL INPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE () 5 1 15 2 25 3 35 4 DIGITAL INPUT CODE SUPPLY CURRENT vs. SUPPLY VOLTAGE 2.7 2.8 2.9 3. 3.1 3.2 3.3 SUPPLY VOLTAGE (V) toc1 toc4 toc7 INL (LSB).25.2.15.1.5 -.5 -.1 -.15 -.2 -.25 4 35 3 25 2 15 1 INTEGRAL NONLINEARITY vs. DIGITAL CODE () 5 1 15 2 25 3 35 4 DIGITAL INPUT CODE SUPPLY CURRENT vs. TEMPERATURE 5-4 -15 1 35 6 85 4 35 3 25 2 15 1 5 SUPPLY CURRENT vs. SUPPLY VOLTAGE 4.5 4.6 4.7 4.8 4.9 5. 5.1 5.2 5.3 5.4 5.5 SUPPLY VOLTAGE (V) toc2 toc5 toc8 DNL (LSB).4.3.2.1 -.1 -.2 -.3 -.4 4 35 3 25 2 15 1 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE () 5 1 15 2 25 3 35 4 DIGITAL INPUT CODE SUPPLY CURRENT vs. TEMPERATURE 5-4 -15 1 35 6 85.5.45.4.35.3.25.2.15.1.5 FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE -4-15 1 35 6 85 toc3 toc6 toc9 7

( = +5V () = +3V (), R L = 5kΩ, C L = 1pF, V REF = +1.25V (), V REF = +2.5V (), C REF =.1µF ceramic 2.2µF electrolytic, both DACs on, V OUT = full scale, T A = +25 C, unless otherwise noted.) VOUT (V) 3 29 28 27 26 25 24 23 22 21 2 3 29 28 27 26 25 24 23 22 4.97 4.965 4.96 4.955 4.95 4.945 4.94 BOTH DACs SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE -4-15 1 35 6 85 BOTH DACs SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE 21 2-4 -15 1 35 6 85 FULL-SCALE OUTPUT vs. TEMPERATURE toc1 toc13 toc16 FULL-SCALE ERROR (LSB) 18 179 178 177 176 175 174 173 172 ONE DAC SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE 171 17-4 -15 1 35 6 85 19 18 17 16 15 14 13 12 11 ONE DAC SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE 1 9-4 -15 1 35 6 85 2. 1.75 1.5 1.25 1..75.5 FULL-SCALE ERROR vs. RESISTIVE LOAD toc11 toc14 toc17 VOUT (V) 1..9.8.7.6.5.4.3.2 FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE.1-4 -15 1 35 6 85 2.455 2.454 2.453 2.452 2.451 2.45 FULL-SCALE OUTPUT vs. TEMPERATURE 2.449-4 -15 1 35 6 85 FULL-SCALE ERROR (LSB) 4. 3.5 3. 2.5 2. 1.5 1. FULL-SCALE ERROR vs. RESISTIVE LOAD toc12 toc15 toc18 4.935 4.93-4 -15 1 35 6 85.25 2.5 3. 3.5 4. 4.5 5. 5.5 6. 6.5 7. 7.5 R L (kω).5 2.5 3. 3.5 4. 4.5 5. 5.5 6. 6.5 7. 7.5 R L (kω) 8

( = +5V () = +3V (), R L = 5kΩ, C L = 1pF, V REF = +1.25V (), V REF = +2.5V (), C REF =.1µF ceramic 2.2µF electrolytic, both DACs on, V OUT = full scale, T A = +25 C, unless otherwise noted.) 1V/div 1V/div DYNAMIC RESPONSE RISE TIME 2µs/div toc19 2V/div 2V/div DYNAMIC RESPONSE RISE TIME 4µs/div toc2 1V/div 1V/div DYNAMIC RESPONSE FALL TIME 2µs/div toc21 DYNAMIC RESPONSE FALL TIME toc22 CROSSTALK toc23 CROSSTALK toc24 2V/div OUTB 2V/div OUTB 5V/div 2V/div OUTA 1mV/div SHUTDOWN OUTA 1mV/div SHUTDOWN 2µs/div 2ms/div 4µs/div DIGITAL FEEDTHROUGH toc25 DIGITAL FEEDTHROUGH toc26 MAJOR-CARRY GLITCH toc27 2V/div 5V/div 1V/div 1mV/div 1mV/div 5mV/div AC -COUPLED 4µs/div 4µs/div 1µs/div 9

( = +5V () = +3V (), R L = 5kΩ, C L = 1pF, V REF = +1.25V (), V REF = +2.5V (), C REF =.1µF ceramic 2.2µF electrolytic, both DACs on, V OUT = full scale, T A = +25 C, unless otherwise noted.) 2V/div 5mV/div AC-COUPLED MAJOR-CARRY GLITCH 2µs/div toc28 VOUT (V) 2.25 2. 1.75 1.5 1.25 1..75.5.25 FULL-SCALE OUTPUT VOLTAGE vs. REFERENCE VOLTAGE.25.5.75 1. 1.25 V REF (V) toc29 VOUT (V) 4.5 4. 3.5 3. 2.5 2. 1.5 1..5 FULL-SCALE OUTPUT VOLTAGE vs. REFERENCE VOLTAGE.5 1. 1.5 2. 2.5 V REF (V) toc3 PIN NAME FUNCTION 1 OUTA DAC A Output 2 REFA Reference for DAC A 3 GND Ground 4 LDAC Load DACs A and B 5 Chip Select Input 6 Shift Register Serial Clock Input 7 Serial Data Input 8 Positive Supply 9 REFB Reference for DAC B 1 OUTB DAC B Output V OUT _ = (V REF _ x NB / 496) x 1.6384V/V µ µ 1

LDAC C2 1 C1 COMMAND EXECUTED 8 9 16 (1) C D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D t LDL t LD S t W t O t S t H t 1 t CH t CP t CL t DS t DH 11

MSB <----------- 16 bits of serial data -----------> LSB 3 Control Bits MSB...12 Data Bits...LSB Sub Bit C2...C D11...D S µ µ µ µ µ LDAC LDAC LDAC LDAC LDAC 12

16-BIT SERIAL WORD C2 C1 C D11...D S* FUNCTION 1 12-bit DAC data Load input register A; DAC registers are unchanged. 1 12-bit DAC data Load input register A; all DAC registers are updated. 1 1 12-bit DAC data 1 X X X X X X X X X X X X Load all DAC registers from the shift register (start up both DACs with new data, and load the input registers). Update both DAC registers from their respective input registers (start up both DACs with data previously stored in the input registers). 1 1 12-bit DAC data Load input register B; DAC registers are unchanged. 1 1 12-bit DAC data Load input register B; all DAC registers are updated. 1 1 1 P1A P1B X X X X X X X X X X 1 X X X X X X X X X Power down both DACs respectively according to bits P1A and P1B (see Table 3). Internal bias remains active. Update DAC register A from input register A (start up DAC A with data previously stored in input register A). 1 1 P1A P1B X X X X X X X Full power-down. Power down the main bias generator and power down both DACs respectively according to bits P1A and P1B (see Table 3). 1 1 X X X X X X X X X Update DAC register B from input register B (start up DAC B with data previously stored in input register B). 1 1 P1A X X X X X X X X Power down DAC A according to bit P1A (see Table 3). 1 1 1 P1B X X X X X X X X Power down DAC B according to bit P1B (see Table 3). X = Don t care. * = S must be zero for proper operation. V OUT = V REF [((1.6348 x NB) / 496) - 1] P1(A/B) SHUTDOWN MODE Shut down with internal 1kΩ load to GND 1 Shut down with internal 2kΩ load to GND µ µ 13

DAC CONTENTS MSB LSB 1111 1111 1 111 () 1 1 () 1 () 111 1111 1 111 () + V ANALOG OUTPUT 495 + V REF 1. 6384 496 249 + V REF 1. 6384 496 REF 248 1. 6384 = V 496 247 + V REF 1. 6384 496 REF R R R 2R 2R 2R 2R 2R D D9 D1 D11 REF_ GND SHOWN FOR ALL ONES ON DAC 121kΩ 77.25kΩ 1kΩ 1 () 1 + V REF 1. 6384 496 5V () V Note: () are for the sub-bit. MOSI SS DAC CONTENTS ANALOG OUTPUT MSB LSB SCK SPI/QSPI PORT 1111 1111 1 111 () 247 + V REF 248 I/O 1 1 () 1 + V REF 248 1 () V 111 1111 111 () 1 -V REF 248 1 () 247 -V REF 248 SK SO I/O MICROWIRE PORT () Note: () are for the sub-bit. 248 -VREF = -V 248 REF 14

ANALOG OUTPUT VALUE (LSB) 7 6 5 4 3 2 1 AT STEP 1 (1/4LSB ) AT STEP 11 (1/2LSB ) 1 1 11 1 11 11 DIGITAL INPUT CODE 111 ANALOG OUTPUT VALUE (LSB) 6 5 4 3 2 1 1LSB DIFFERENTIAL LINEARITY ERROR (-1/4LSB) DIFFERENTIAL LINEARITY ERROR (+1/4LSB) 1 1 11 1 11 DIGITAL INPUT CODE 1LSB ANALOG OUTPUT VALUE (LSB) 3 2 1 ACTUAL DIAGRAM ACTUAL OFFSET POINT OFFSET ERROR (+1 1/4LSB) IDEAL OFFSET POINT IDEAL DIAGRAM 1 1 11 DIGITAL INPUT CODE ANALOG OUTPUT VALUE (LSB) 7 6 5 4 IDEAL DIAGRAM IDEAL FULL-SCALE OUTPUT GAIN ERROR (-1 1/4LSB) 1 11 11 111 DIGITAL INPUT CODE ACTUAL FULL-SCALE OUTPUT 15

REF_ DAC_ GAIN = 1.6384V/V GND 5V/3V 121kΩ 77.25kΩ 1kΩ REF_ DAC_ GND 5V/3V 77.25kΩ 121kΩ 1kΩ 1kΩ.6384R R 1kΩ V+ V- V OUT 5V/3V 26kΩ AC REFERENCE INPUT 5V/3V REF_ 5V/3V V+ PHOTODIODE 5mV P-P 1kΩ MAX495 REF_ 121kΩ 121kΩ V+ DAC_ 77.25kΩ µp DAC_ 77.25kΩ V- V OUT 1kΩ 1kΩ R PULLDOWN GND GND µ µ 16

V IN V REF REFA REFB SHIFT REGISTER INPUT REG A INPUT REG B DAC REG A DAC REG B DAC A DAC B GND 121kΩ 121kΩ 77.25kΩ OUTA OUTB 77.25kΩ R1 R3 R2 R4 VOUT = (GAIN) (OFFSET) = V 2NA R2 IN 496 R1 + R2 1 + R4 R3 V OUT V REF 2NB 496 R4 R3 NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DAC A. NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DAC B. 1 2 3 TO OTHER SERIAL DEVICES TRANSISTOR COUNT: 4184 PROCESS: BiCMOS 17

LDAC DECODE CONTROL 16-BIT SHIFT REGISTER SR CONTROL GND INPUT REG A DAC REG A REFA DAC A 121kΩ 77.25kΩ 1kΩ 121kΩ OUTA 77.25kΩ INPUT REG B DAC REG B DAC B 1kΩ OUTB REFB 18

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