16-Bit Bus LVDS Serializer/Deserializer - 25-80 MHz Literature Number: JAJS960
16 Bus LVDS / 25-80MHz 20001108 Changed pin description for pin 3 and 18. Add PCB Layout consideration on Apps Info section. Add receiver noise margin figure and reference. (PH) Updated frequency in PID from 30-80 to 35-80 MHz (PH) format MIN/MAX values for Djit (MB) Chg ESD to 2.5 kv, chg trnm typs, add trjit and tdjit typs,chg icct to 209 ma 2nd release ready post FAE 2nd edit Post FAE changes Implemented changes from MKting (ph) Removed all Trademark references to TRI STATE format/typo edits (JFG) Change package reference to LQFP Preliminary edit with correct figures updated pid source to reflect base segment removed cross reference for xref ns6176 hot insertion 1st rev. with text and table (ph) Initial PPRS to SGML PH fixed table width for Deseraializer declared graphic entity 200143-27 Fixed Deserializer switching characteristic table border changed Pin name for pin # 3 and 8. Added Caption and reference for Figure 16 (PH) Changed min oper freq to 25MHz (PH) Take out receiver noise margin curve (PH) replace 20014332 with 20024828 Change trnm to trnmi (PH) trnmmin 230ps (PH) Min oper. freq. change to 30MHz / changed tdjit and noise margin (PH) add ref to figure 15 and 16 (PH) 3RD EDIT ON GRAPHIC FORMAT (PH) 2ND EDIT FOR GRAPHIC FORMAT (PH) Change figure format (PH) Add new Jitter and Noise Margin graph (PH) PCB & Power stuff typo edit (PH) Update PCB guideline on APPS info. (PH) Pre-release check (PH) inserted a new column to get the figure to compose side by side converted to nat2000 and composed Converted to nat2000 DTD Edited by JG (PH) artwork changes on figures 1, 2, 17, 18 and finalized spec. (PH) clean up format (JFG) spell checked, release ready (PH) 16 Bus LVDS / 25-80MHz 1 (SERDES) 16 BLVDS 1 I/O BLVDS BLVDS EMI 2002 2 25 80MHz 16:1/1:16 / ( 2.56Gbps) 5 BLVDS EMI PLL PLL 3.3V : 80MHz 104mA ( ) 119mA ( ) 100mV ( ) ESD 80 PQFP 40 85 2.5kV 16 Bus LVDS / 25-80MHz 20020218 National Semiconductor Corporation DS200143-08-JP 1
(Note 1) (V CC ) 0.3V 4V LVCMOS/LVTTL 0.3V (V CC 0.3V) LVCMOS/LVTTL 0.3V (V CC 0.3V) Bus LVDS 0.3V 3.9V Bus LVDS 0.3V 3.9V Bus LVDS 10ms 150 65 150 ( 4 ) 260 80L PQFP 25 23.2mW/ JA 43 /W JC 11.1 /W ESD ( ) >2.5kV (V CC ) 3.15 3.3 3.45 V (T A ) 40 25 85 25 80 MHz Symbol Parameter Conditions Pin/Freq. Min Typ Max Units LVCMOS/LVTTL DC Specifications V IH High Level Input Voltage 2.0 V CC V V IL Low Level Input Voltage TCLK_R/F,DEN, TCLK, TPWDN, DIN, GND 0.8 V SYNC, RCLK_R/F, V CL Input Clamp Voltage I CL 18 ma REN, REFCLK, 0.7 1.5 V PWRDN I IN Input Current V IN 0V or 3.6V 10 2 10 A V OH High Level Output Voltage I OH 9 ma 2.3 3.0 V CC V V OL Low Level Output Voltage I OL 9 ma R OUT, RCLK, LOCK GND 0.33 0.5 V I OS Output Short Circuit Current VOUT 0V 15 48 85 ma I OZ TRI-STATE Output Current PWRDN or REN 0.8V, V OUT 0V or VCC R OUT, RCLK, 10 0.4 10 A Bus LVDS DC specifications VTH VTL I IN Differential Threshold High Voltage Differential Threshold Low Voltage Input Current VCM 1.1V 100 mv V IN 2.4V, V CC 3.6V or 0V V IN 0V, V CC 3.6V or 0V RI, RI 100 mv 10 5 10 A 10 5 10 A 2
( ) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units Bus LVDS DC specifications Output Differential Voltage V OD RL 100, Figure 17 350 500 550 mv (DO ) (DO ) V OD Output Differential Voltage Unbalance 2 15 mv V OS Offset Voltage 1.05 1.2 1.25 V V OS Offset Voltage Unbalance 2.7 15 mv I OS Output Short Circuit Current DO 0V, Din H, TXPWDN and DEN 2.4V DO, DO 35 50 70 ma I OZ Tri-State Output Current TXPWDN or DEN 0.8V, DO 0V OR VDD 10 1 10 A VDD 0V, DO 0V I OX Power-Off Output Current or 3.6V SER/DES SUPPLY CURRENT (DVDD, PVDD and AVDD pins) I CCT I CCX Total Supply Current (includes load current) Supply Current Powerdown C L 15 pf, R L 100 C L 15 pf, R L 100 PWRDN 0.8V, REN 0.8V f 80 MHz, PRBS15 pattern f 80 MHz, Worse case pattern (Checker-board pattern) 10 1 10 A 209 ma 225 320 ma 0.35 1.0 ma TCLK Symbol Parameter Conditions Min Typ Max Units t TCP Transmit Clock Period 12.5 T 40 ns t TCIH Transmit Clock High Time 0.4T 0.5T 0.6T ns t TCIL Transmit Clock Low Time 0.4T 0.5T 0.6T ns t CLKT TCLK Input Transition Time 3 6 ns t JIT TCLK Input Jitter 80 ps (RMS) Symbol Parameter Conditions Min Typ Max Units t LLHT t LHLT Bus LVDS Low-to-High Transition Time Bus LVDS High-to-Low Transition Time R L 100 Figure 3 C L 10pF to GND t DIS DIN (0-15) Setup to TCLK Figure 6 t DIH DIN (0-15) Hold from TCLK R L 100, C L 10pF to GND 0.2 0.4 ns 0.2 0.4 ns 2.4 ns 0 ns 3
( ) Symbol Parameter Conditions Min Typ Max Units t HZD DO HIGH to TRI-STATE Delay 2.3 10 ns t LZD t ZHD t ZLD DO LOW to TRI-STATE Delay DO TRI-STATE to HIGH Delay DO TRI-STATE to LOW Delay Figure 7 (Note 4) R L 100, C L 10pF to GND 1.9 10 ns 1.0 10 ns 1.0 10 ns t SPW SYNC Pulse Width Figure 8 5*t TCP 6*t TCP ns t PLD Serializer PLL Lock Time R L 100 510*t TCP 513*t TCP ns t SD Serializer Delay Figure 9 R L 100 t TCP 1.0 t TCP 2.0 t TCP 4.0 ns t RJIT Random Jitter 10 ps(rms) t DJIT Deterministic Jitter 35 MHz 240 140 ps Figure 15 80 MHz 75 100 ps REFCLK Symbol Parameter Conditions Min Typ Max Units t RFCP REFCLK Period 12.5 T 40 ns t RFDC REFCLK Duty Cycle 40 50 60 % t RFCP / t TCP Ratio of REFCLK to TCLK 0.95 1.05 t RFTT REFCLK Transition Time 6 ns Symbol Parameter Conditions Pin/Freq. Min Typ Max Units t RCP Receiver out Clock Figure 9 Period t RCP t TCP RCLK 12.5 40 ns t RDC RCLK Duty Cycle RCLK 45 50 55 % t CLH t CHL t ROS t ROH t HZR t LZR t ZHR CMOS/TTL Low-to-High Transition Time CMOS/TTL High-to-Low Transition Time ROUT (0-9) Setup Data to RCLK ROUT (0-9) Hold Data to RCLK HIGH to TRI-STATE Delay LOW to TRI-STATE Delay TRI-STATE to HIGH Delay TRI-STATE to LOW Delay CL 15 pf Figure 4 Figure 11 Figure 12 Rout(0-9), LOCK, RCLK Rout(0-9), LOCK 2 4 ns 2 4 ns 0.35*t RCP 0.5*t RCP ns 0.35*t RCP 0.5*t RCP ns 2.2 10 ns 2.2 10 ns 2.3 10 ns t ZLR 2.9 10 ns t DD Deserializer Delay RCLK 1.75*t RCP 2 1.75*t RCP 5 1.75*t RCP 7 ns 4
( ) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units t DSR1 t DSR2 Deserializer PLL Lock Time from PWRDWN (with SYNCPAT) Deserializer PLL Lock time from SYNCPAT (Note 7) 35MHz 3.7 10 s 80 MHz 1.9 4 s 35MHz 1.5 5 s 80 MHz 0.9 2 s t RNMI-R Ideal Deserializer Noise Margin Right Figure 16 (Note 6) 35 MHz 630 ps 80 MHz 230 ps t RNMI-L Ideal Deserializer Noise Margin Left Figure 16 (Note 6) 35 MHz 630 ps 80 MHz 230 ps Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Typ V CC 3.3V T A 25 VOD VOD VTH VTL TRI-STATE PLL REFCLK (SYNCPAT) PLL tdsr1 tdsr2 tdsr1 tdsr2 tdsr1 tdsr2 (R R ) (SYNCPAT) trnmi ( ) AN-1217 Sync 8 "H" 8 "L" 5
AC FIGURE 1. Worst Case Serializer ICC Test Pattern FIGURE 2. Worst Case Deserializer ICC Test Pattern FIGURE 3. Serializer Bus LVDS Output Load and Transition Times FIGURE 4. Deserializer CMOS/TTL Output Load and Transition Times 6
AC ( ) FIGURE 5. Serializer Input Clock Transition Time FIGURE 6. Serializer Setup/Hold Times FIGURE 7. Serializer TRI-STATE Test Circuit and Timing 7
AC ( ) FIGURE 8. Serializer PLL Lock Time, SYNC Timing and PWRDN TRI-STATE Delays FIGURE 9. Serializer Delay FIGURE 10. Deserializer Delay FIGURE 11. Deserializer Setup and Hold Times 8
AC ( ) FIGURE 12. Deserializer TRI-STATE Test Circuit and Timing FIGURE 13. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays 9
AC ( ) FIGURE 14. Deserializer PLL Lock Time from SyncPAT FIGURE 15. Deterministic Jitter and Ideal Bit Position 10
AC ( ) t RNMI-L t RNMI-R FIGURE 16. Deserializer Noise Margin (t RNMI ) and Sampling window V OD (DO ) (DO ) (DO ) (DO ) FIGURE 17. V OD Diagram FIGURE 18. Icc vs Freq 11
AC ( ) FIGURE 19. Icc vs Freq (Rx only) FIGURE 20. Icc vs Freq (Tx only) 12
1 16 LVCMOS LVTTL BLVDS 16 ( ) ( ) SER/DES 3 TRI-STATE 2 PLL PLL 1: / V CC TRI-STATE V CC V CC OK (2.2V) PLL TCLK REFCLK TCLK REFCLK PLL TCLK TRI- STATE TCLK SYNC "H" (SYNC ) PLL REFCLK TRI-STATE LOCK RIN / SYNC PLL "H" 2: PLL 2 ( ) SYNC SYNC LVDS SYNC SYNC 150 PLL LOCK "L" LOCK "L" SYNC SYNC LOCK SYNC 16 "H" "L" DIN [0:15] TCLK SYNC 6 TCLK "H" DIN [0:15] TCLK 18 (16 2 ) TCLK 60MHz 60 18 1080Mbps 16 TCLK 16 TCLK 60MHz 60 16 960Mbps TCLK 25MHz 80MHz LOCK "L" ROUT [0:15] RCLK ROUT [0:15] RCLK ROUT [0:15] LOCK "L" "H" 80MHz ROUT [0:15] LOCK RCLK 3 CMOS (typ 15pF ) ASIC REN TRI-STATE (V CC 0V) (RPWDN* "L") 2 PLL LOCK "H" 13
( ) LOCK ROUT LOCK "L" ROUT LOCK PLL LOCK "H" LOCK "H" SYNC SYNC REFCLK SYNC PLL LOCK SYNC SYNC "L" "H" PLL RMT (repetitive multi-transition) RMT "L" "H" (DIN 15 ) "L" H "L" "H" 1 2 RMT LOCK RMT PLL LOCK "L" ROUT TPWDN* RPWDN* RPWDN* "L" PLL TRI-STATE A RPWDN* "H" TPWDN* "L" A PLL TRI-STATE TPWDN* "H" PLL TCLK TRI-STATE REN "L" TRI- STATE ROUT [0:15] RCLK TRI-STATE (RPWDN*) REN "H" TRI-STATE DEN "L" TRI- STATE LVDS TRI- STATE DEN "H" TRI-STATE 2 LINE_LE "H" (RIN / ) (ROUT [0:15]) (DO / ) (RIN / ) LINE_LE "H" (DIN [0:15]) (ROUT [0:15]) (DO / ) 1 16 TTL 1.28Gbps Bus LVDS PLL 2 PLL REFCLK PLL LOCK CMOS LVDS CMOS I CC REFCLK TRI-STATE 14
( ) : TCLK V CC ( ) : ISI V CM : V CC Figure 16 5 2 LOCK LOW 5 SYNC TRI-STATE LVDS LVDS VCC I/O I/O VCC BLVDS 2 4 50MHz 0.01 F 0.1 F 2.2 F 10 F 5 2 2 1/2 50 1 50 F 100 F X7R 0603 20 30MHz 2 / PLL LVDS 4 CMOS (TTL) LVDS LVDS LVDS 100 LVDS 100 LVDS LVDS PDF (appinfo/lvds/) BLVDS / 15
( ) DVDD DVDD DVDD DVDD DVDD 4 22nF (4 70 280mA) 4 (4ns) VDD (50mV ) 22.4nF 0.1 F DVDD PVDD PLL PVDD PLL 2 PLL PLL 300kHz 1MHz VDD ( ) (CRC CLC ) PLL PVDD 2 PVDD AVDD LVDS AVDD LVDS 4 AVDD 0.1 F 0.1 F 0.01 F AGND LVDS LVDS LVDS DVDD PVDD AVDD 16
TVHG Top VIew 17
I/O 1 RPWDN* CMOS I RPWDN* "L" PLL (Note 8) 2 REN CMOS I REN "L" TRI-STATE PLL ( LOCK ) (Note 8) 3 CONFIG1 "H" (NC) "L" 4 REFCLK CMOS I 5 10 11 15 AVDD 6 9 12 16 AGND 7 RIN LVDS I LVDS 8 RIN LVDS I LVDS 13 DO LVDS O LVDS 14 DO LVDS O LVDS 17 TCLK CMOS I DIN PLL TCLK 18 CONFIG2 "H" (NC) "L" 19 DEN CMOS I DEN "L" TRI-STATE PLL (Note 8) 20 SYNC CMOS I SYNC "H" ( ) SYNC (Note 8) 21 22 23 24 25 26 27 28 33 34 35 36 37 38 39 40 DIN (0:15) CMOS I (Note 8) 29 32 PGND PLL 30 31 PVDD PLL 41 44 51 52 59 60 DGND 61 68 80 42 TPWDN* CMOS I TPWDN* "L" PLL (Note 8) 43 50 53 58 62 69 DVDD 45 46 47 48 54 55 56 57 64 65 66 67 70 71 72 73 ROUT (0:15) CMOS O 49 RCLK CMOS O ROUT [0:15] LVCMOS 63 LOCK* CMOS O LOCK* PLL LOCK "H" PLL "L" 74 76 PGND PLL 75 77 PVDD PLL 78 LINE_LE CMOS I LINE_LE "H" RIN / DO / (Note 8) 79 LOCAL_LE CMOS I LOCAL_LE "H" DIN [0:15] ROUT [0:15] (Note 8) Note 8: "L" 18
millimeters Dimensions shown in millimeters only Order Number TVHG NS Package Number VHG80A 16 Bus LVDS / 25-80MHz 1. (a) (b) 2. 135-0042 2-17-16 TEL.(03)5639-7300 / 0120-666-116
IMPORTANT NOTICE