353 ISO/IEC JTC1 SC LSI 1 1 ASIC RISC SPARC 4 Fig. 1 1 Fig. 1 Diagram of Responsive Processor [2] [6] [7] [8] [9] 4 PCI USB RS 232C A/D D/A PWM

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1 352 Vol. 19 No. 3, pp , Responsive Processor for Parallel/Distributed Real Time Control Nobuyuki Yamasaki 1 and Toshihiro Matsui 2 In this paper, we propose and design Responsive Processor for parallel/distributed real time processing, which can control various electronic control systems including robots, mechatronic systems, home automation, office automation, factory automation, etc. Responsive Processor integrates many functions into an ASIC chip, such as a RISC MPU core (SPARC), Responsive Links for real time communication, many peripheral functions including SDRAM I/Fs, DMAC, PCI, USB, PWM generators, A/D converters, D/A converters, etc. In order to realize real time communication needed for parallel/distributed control, a set of Responsive Link consists of a pair of two way data links and event links. Prioritized routing which enables packets with higher priority to overtake other packets is implemented by hardware at each node. Many kinds of systems can flexibly be composed by connecting these chips using Responsive Links. Key Words: Parallel/Distributed Control, Real Time, System on a chip, Responsive Link Keio University/Electrotechnical Laboratory 2 Electrotechnical Laboratory [1] Yamabico bus ASPIRE [2] [3] VME [4] I 2 C LAN [5] MPU ADC DAC PWM DMAC SIO 1 System on a chip VLSI JRSJ Vol. 19 No Apr., 2001

353 ISO/IEC JTC1 SC25 1 2. LSI 1 1 ASIC RISC SPARC 4 Fig. 1 1 Fig.

2 353 ISO/IEC JTC1 SC LSI 1 1 ASIC RISC SPARC 4 Fig. 1 1 Fig. 1 Diagram of Responsive Processor [2] [6] [7] [8] [9] 4 PCI USB RS 232C A/D D/A PWM I/O I/O PCI 3. [10]

3 354 CPU I/O I/O I/O Fig. 2 LAN Fig. 2 Fig. 2 Fig. 2 Humanoid Fig Base TX Switching Hub 3. 3 [11] [12] JRSJ Vol. 19 No Apr., 2001

4 Responsive Link I/O 4. 1 Responsive Link Gbit Ethernet ATM Fibre Channel IEEE 1394 USB Table 1 Trade off of packet size Point \ Packet Size Larger Smaller Throughput Higher Lower Latency Longer Shorter DSP 8[bit] 10 [cm] Table 1 point to point 1 1 Fig

5 356 Table 2 Speed vs. power on Responsive Link Speed of Modulation (Mbaud) Speed of Data (Mbps) Latency of Event (µsec) Power (W) Fig. 3 Responsive Link I/F Fig. 4 Packet format of Responsive Link point to point Fig. 4 1 FEC 1 frame 8 [bit] +4 [bit] 1 [bit] Fig. 4 AC 100 [Mbaud] Table [Mbaud] 1 8 [byte] Latency of Event =2[µsec] + 1 [µsec] n [hops] 2[µsec] 1 [hop] 1[µsec] [13] Gbit Ethernet Myrinet [14] 4 [byte] 10 [µsec] JRSJ Vol. 19 No Apr., 2001

6 Fig [Gbps] P CML Pseudo Current Mode LogicP CML LVTTL Low Voltage TTL ECL Emitter Coupled Logic LVTTL ECL DMA SDRAM DMA DMA & 4 DMA 5 6 DMAC DMA SPARC Fig. 1 SPARC SDRAM DMA DMA 4 DMA DMA 5 DMA bit SPARC 4. 2 RISC SPARC [3] SPARClite [15] [16] 100 [MHz] 8 [kb] 8 [kb] Table

358 Table 3 Clock vs. power on processing core Clock (MHz) 100 80 60 40 20 Sleep Speed (MIPS) 121 97 73 48 24 0 Power (W) 1.0 0.8 0.6 0.4 0.2 0.01 Table 4 Peripherals Peripherals for control Num.

7 358 Table 3 Clock vs. power on processing core Clock (MHz) Sleep Speed (MIPS) Power (W) Table 4 Peripherals Peripherals for control Num. of Channels 10bit A/D Converter 8 8bit D/A Converter 2 50 MHz PWM Generator 9 24bit Pulse Counter 9 Digital I/O Port 16 Table 5 Peripherals Peripherals for computer Num. of Channels SDRAM I/F 2 Interrupt Controller 43 DMA Controller 4 PCI I/F 1 USB I/F (Function, Hub) 1 Asyncronous SIO (RS 232C) 2 Synchronous SIO 1 16bit Timer/Counter 4 Real Time Clock a b c d 2 3 I/O I/O Table 4 A/D D/A 2 A/D D/A PWM DC 2 1 AC 3 1 DC 4 AC 3 PWM 9 PWM 50 [MHz] 24 [bit] I/O 4. 4 Table 5 PCI USB 4. 5 Fig. 5 SPARC 300 [k gate] ADC DAC Fig. 5 Layout of Responsive Processor [k gate] 0.35 [µm] CMOS 4 2,378 [k gate] 14.5 [mm] 14.5 [mm] = 210 [mm 2 ] 416 BGA (40 [mm] 40 [mm]) 3.3 [V] 2 [W] Fig JRSJ Vol. 19 No Apr., 2001

RS 232C PCI USB 5. 2 SPARC GCC GNU C SPARC GNU ROM Windows Windows GNU GNU GDB Windows WinGDB PC Fig.

8 359 Fig. 6 Responsive Processor UNIX Windows PC UNIX Linux FreeBSD Solaris Windows 5. 1 PC 1 Responsive Link 2 PCI 3 USB 4 Serial (RS 232C) PCI Card PC CardBus Card (PCMCIA type) Embedded Card (Credit card size) RS 232C RS 232C PCI USB 5. 2 SPARC GCC GNU C SPARC GNU ROM Windows Windows GNU GNU GDB Windows WinGDB PC Fig. 7 Screen of WinGDB RS 232C stdin/stdout PC GDB PC WinGDB ROM ROM PC 1 PC C SPARC g 2 PC WinGDB 3 RS 232C 4 GCC WinGDB 5 PC WinGDB & WinGDB GDB UNIX GDB C WinGDB GDB Fig. 7 WinGDB ROM WinGDB WinGDB

9 360 WinGDB µ PULSER [17] [13] 6. 1 ISO/IEC JTC1 SC25 Windows GDB WinGDB WinGDB ROM 7. 1/2 1 BGA CSP Chip Size Package SPARC IP 1 COE 21 COE Jijo2 [ 1 ] Sho ji Suzuki, Jun ichi Iijima and Shin ichi Yuta: Design and implementation of an architecture of autonomous mobile robots for experimental researches, 6th International Conference on Advanced Robotics, pp , [2] ASPIRE vol.37, no.1, pp.81 91, [3] ASPIRE RISC vol.14, no.4, pp , [4] vol.15. no.3, pp , [5] 14 pp , [ 6 ] John A. Stankovic: Misconceptions about real time computing, IEEE Computer, pp.2 10, [ 7 ] A. Benveniste, P.L. Guernic, Y. Sorel and M. Sorine: A denotational theory of synchronous reactive systems, Information and Computation, vol.99, pp , [8] CPSY , vol.96, no.597, pp.53 58, [ 9 ] Nobuyuki Yamasaki and Toshihiro Matsui: A Functionally Distributed Responsive Micro Controller for Distributed Real time Processing, Proceedings of IEEE/RSJ International Conference on Intelligent Robots and Systems, vol.2, pp , [10] Selim G. Akl: Parallel Sorting Algorithms. Academic Press Inc., JRSJ Vol. 19 No Apr., 2001

361 [11] D vol.120-d, no.1, pp.80 87, 2000. [12] vol.16, no.3, pp.337 344, 1998. [13] OS µ PULSER vol.

com [15] SPARClite MB86830 [16] SPARClite MB86930 [17] µ PULSER vol.j77-d-i, no.2, pp.207 214, Feb. 1994.

10 361 [11] D vol.120-d, no.1, pp.80 87, [12] vol.16, no.3, pp , [13] OS µ PULSER vol.98, no.687, pp.47 54, [14] [15] SPARClite MB86830 [16] SPARClite MB86930 [17] µ PULSER vol.j77-d-i, no.2, pp , Feb Nobuyuki Yamasaki COE IEEE Toshihiro Matsui ISRR ACM IEEE

A Responsive Processor for Parallel/Distributed Real-time Processing

A Responsive Processor for Parallel/Distributed Real-time Processing E-mail: yamasaki@{ics.keio.ac.jp, etl.go.jp} http://www.ny.ics.keio.ac.jp etc. CPU) I/O I/O or Home Automation, Factory Automation, (SPARC) (SDRAM I/F, DMAC, PCI, USB, Timers/Counters, SIO, PIO, )