A Responsive Processor for Parallel/Distributed Real-time Processing

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1 etl.go.jp}

2

3 etc.

4 CPU) I/O

5

6 I/O or

7

8

9 Home Automation, Factory Automation, (SPARC) (SDRAM I/F, DMAC, PCI, USB, Timers/Counters, SIO, PIO, ) (ADC, DAC, PWM Generators, Pulse Counters,...) 1 System-on-a-chip

10

11

12 Responsive Processor Responsive Link (Real-Time Communication) Control I/O (ADC, DAC, PWM Generators, Counters,...) Motor Sensor... Processing Core (SPARC) DMAC MMU Computer I/O SDRAM PCI USB

13 IEEE-1394 USB IEEE-1394:63, USB: 127)

14

15 64B, 16B ( ) ( ) (12.5 to 100M bps) Point-to-point Responsive Processor

16 image sync signal sound sync Shared traffic indefinite latency and throughput sync interrupt status open signal connect Event link Low Latency image sound voice table text Data link High Throughput

17

18

19 Data Packet Format (64B) Source Addr. Destination Addr. EventPacketFormat(16B) Source Addr. Destination Addr. Payload Control & Status Payload Control & Status 1byte Control & Status Format (32bits) 1bit Full Data Length Dirty0 Dirty1 Dirty2 Dirty3 Dirty4 Dirty5 Dirty6 Dirty7 Dirty8 Dirty9 Dirty10 Dirty11 Dirty12 Dirty13 Dirty14 Dirty15 3 Start End Int. Fatal Correct Serial Number (Cnt.) Frame Format (12bits) Data bits Redundancy bits

20 Responsive Link Connector Responsive Link Cable Tx Data+ Tx Data- Rx Data+ Data Link Rx Data- Tx Event+ Tx Event- Rx Event+ Event Link Rx Event-

21

22

23 Priority1 Priority0 EE P1 PEL3 L1 Src Addr(16b) Dtn Addr(16b) DE P0 L4 L2 L0 0)

24 Data (Priority0) Source Data (Priority1) Event (Priority2) Event (Priority0) Destination

25

26

27 byte 1byte(8bit) 1frame(12bit) 8bit 4bit x 4 +x+1

28 Bit Stuffing 5 1 0

29 NRZI (Non Return to Zero Inverted) 0 1

30 OS

31 Processing Core (SPARClite MB MHz) Power Management Unit (100, 80, 60, 40, 20 [MHz], Sleep) MMU (64way) Responsive Links (4 links, 200, 100, 50, 25 [MHz]) DMAC (4channels, Bus swapping, Bus sizing) SDRAM I/F (2channels, 100MHz) PCI I/F (Master/Target) USB I/F (Function, Hub) PWM Generators (50MHz, 9channels) Pulse Counters (24bit, 9channels) Timers/Counters (16bit, 4channels) Real-Time Clock A/D Converters (10bit, 8channels) D/A Converters (8bit, 2channels) Interrupt Controllers (43channels) SIO (RS-232C, 2channels) PIO (16bit),...

32

33 Process 0.35 m, CMOS, 4 layered metal Usable gates : 2,378 k gates Die size :14.5 mm x 14.5mm = 210mm2 Package : 416pin BGA (40mm x 40mm) Voltage : 3.3V Max. power : 2W

34 Responsive Link Overtaking Buffer for Data Routing Table Overtaking Buffer for Event MMU DMAC Communication Buffer (DPM) SDRAM I/F I/O Controller (IRC,SIO,PIO,Timer, Counter,PWM,etc.) PCI USB SPARClite ADC,DAC

35

36 Performance of MPU Clock(MHz) Sleep Speed(MIPS) Power(W) Performance of Responsive Link Clock (MHz) Max. Speed (Mbaud) Speed of Data (Mbps) Latency of Event( sec) Power (W) Latency of Event (Worst) = 1 ( sec) + 2 ( sec/hop) x n (hop)

37 PCI card (PCI half size) CardBus card (PCMCIA size) Embedded board (Credit card size)

38 PCI Card

39 PCI Card with Analog Devices 16bit DAC 6channels 12bit ADC 6channels

40 PC(Windows or UNIX) PCI,USB,RS- 232C GNU (gcc, as, ld, make, etc.) WinGDB

41 WinGDB

42 VxWorks psosystem itron OS-9 RT-Mach PULSER RT-Linux

43 Responsive Link ( ) ISO/IEC JTC1 SC25 99 ISO/IEC JTC1 SC25 Responsive Link NWIP ANSI

44 Responsive Link JTC1 SC25 WG4 Responsive Link SG Responsive Link SG JTC1 SC25 WG4 RWCP NTT

45 Responsive Processor Responsive Link Processing Core (SPARC)

46

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