Vol. 45 No. SIG 3(ACS 5) Responsive Link 51 Responsive Link Responsive Link WG6 2) IPSJ-TS 0006:2003 ISO/IEC JTC1 SC25 WG4 3) [µs
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1 Vol. 45 No. SIG 3(ACS 5) Mar Responsive Link, FA OA Responsive Link Responsive Link Hot-Plug&Play Responsive Link Responsive Processor Responsive Multithreaded Processor IPSJ-TS 0006:2003 ISO/IEC SC25 WG4 Design and Implementation of Real-time Communication Responsive Link for Distributed Control Nobuyuki Yamasaki, In this paper, we design and implement Responsive Link for distributed real-time control, which can be applied to various electronic control systems including robot systems, mechatronic systems, home automation, office automation, factory automation, etc. In order to realize flexible real-time communications, Responsive Link has many unique features including separation of data transmission for soft real-time (data link) and event transmission for hard real-time (event link), independent routing of the data link and the event link, priority based packet overtaking (the packet with higher priority overtakes other packets at each node.), packet acceleration/deceleration using priority replacement (packet priority can be replaced with a new priority level at each node to accelerate/decelerate packets under distributed control.), prioritized routing (when multiple packets with different priority levels are sent to the same destination, the different route can be set to realize exclusive communication lines or detours.), dynamically variable link speed (800, 400, 200, 100, 50, 25, 12.5 [Mbaud]), hot-plug&play, topology free, etc. Responsive Link is implemented on Responsive Processor and RMT Processor for distributed control. Responsive Link has been standardized as IPSJ- TS 0006:2003 in Japan. Responsive Link is also under standardisation at ISO/IEC JTC1 SC25 WG4. 1. Keio University Presently with an associate researcher of National Institute of Advanced Industrial Science and Technology Responsive Link Responsive Link 1) 50
2 Vol. 45 No. SIG 3(ACS 5) Responsive Link 51 Responsive Link Responsive Link WG6 2) IPSJ-TS 0006:2003 ISO/IEC JTC1 SC25 WG4 3) [µsec] 10 [msec] EDF Fig. 1 EDF scheduling. MPEG 10 [msec] 1 [sec] Responsive Link 2.2 EDF Earliest Deadline First RM Rate Monotonic 1 EDF
3 52 Mar ),5) Responsive Link 2.3 Ethernet ATM Fibre Channel IEEE-1394 USB2.0 Ethernet CSMA/CD ATM IEEE1394 AV I/O 63 Plug&Play USB2.0 I/O PC I/O 127 PC IEEE Responsive Link
4 Vol. 45 No. SIG 3(ACS 5) Responsive Link 53 2 Responsive Link Fig. 2 Responsive Link interface. point-to-point Responsive Link Rate Monotonic Scheduling 3 Responsive Link Fig. 3 Packet format of Responsive Link. 4 Responsive Link Fig. 4 Header format of Responsive Link ) Responsive Link 256 8bit 0 Responsive Link Responsive Link 12 bit 12 bit 8 bit 2 12 = bit 8 bit 2 24 =16M 3.3
5 54 Mar Responsive Link Fig. 5 Network switch of Responsive Link. 7) In0 4 Out bit byte In In-Pointer L0 L4 L2 2
6 Vol. 45 No. SIG 3(ACS 5) Responsive Link 55 6 Fig. 6 Responsive Link Overtaking buffer of Responsive Link. 7 Responsive Link Fig. 7 Routing table of Responsive Link. 6 L0 L4 Out0 Out4 5 Priority ArbitorN 6 PriorityN 5 Priority ArbitorN 1 In-pointer 1 In 1 L1 L3 Out-pointer1 Out-pointer3 1 Out1 Out3 Priority1 Priority3 Out3 Priority Arbitor3
7 56 Mar Out3 Out3 1 L3 Out1 Priorty1 Out1 Out1 2 Out-pointer1 2 Priority1 Out1 Out-pointer SDRAM sdram-in-flagn 2 sdram-out-flagn / 6 sdramout-pointer SDRAM sdramin-pointer Responsive Link SDRAM 3.4 Responsive Link 7 Responsive Link 7 Reference Referent EE DE L[4-0] Responsive Link TLB MMU
8 Vol. 45 No. SIG 3(ACS 5) Responsive Link 57 Responsive Link RT-OS Responsive Link LRU RT-OS 3.5 7) PE PE Priority[7-0] P7 P ) 0 (1) 1 (2) Re-
9 58 Mar Responsive Link CRC 8 Responsive Link Fig. 8 Prioritized routing of Responsive Link. 9 Responsive Link Fig. 9 Prioritized tree routing of Responsive Link. sponsive Link bit 4 bit 1 bit CODEC Responsive Link CODEC 8 bit 4 bit 12 bit 1 CODEC (1) ( 2 ) Bit Stuffing 1 0 ( 3 ) NRZI 9) x 4 + x +1 8 bit LSB 4 bit 12 bit 1 bit 1 12 bit MSB 1 bit Bit Stuffing
10 Vol. 45 No. SIG 3(ACS 5) Responsive Link Table 1 Syndrome and error position. Table 2 Communication speed vs. cable. Syndrome Error Position (4 Meaning redundancy bits) No error Redundancy-bit error Redundancy-bit error Redundancy-bit error Redundancy-bit error bit error bit error bit error bit error bit error bit error bit error bit error NRZI NRZI Non Return to Zero InvertedNRZI bit stuffing DPLL DPLL Digital Phase Lock Loop 1 bit DPLL Responsive Link 1 [bit/frame] Speed (Mbaud) Maximum Length (m) Recommendable Cable Cat5e Cat5e Cat6 Cat6 3 Dirty 4 byte Dirty Dirty 1 Correct Fatal Responsive Link [Mbaud] [Mbaud] Category6 40 [m] DPLL 3.2 [GHz] [GHz] 2 4 DPLL DPLL DPLL 2 4. Responsive Link Responsive Processor 1) Responsive MultiThreaded (RMT ) Processor 10),11) 2
11 60 Mar Responsive Processor Responsive Processor Responsive Link Responsive Link Responsive Processor Responsive Link 100 [Mbaud] 4 2 bit Responsive Processor 30 Responsive Processor Responsive Link SDRAM 16 [MB] 256 CAM DPM CAM CAM IP CAM 32 DPM DPM bit 3.3 CODEC byte 8 bit Responsive Processor Fig. 10 Layout of Responsive Processor Responsive Processor SPARC 300 [k gates] 8 Responsive Link 2 5 Responsive Link 400 [k gates] 0.35µm CMOS 4 2,378 [k gates] 14.5 [mm] 14.5 [mm]=210 [mm 2 ] 416 BGA 40 [mm] 40 [mm] 3.3 [V] 2 [W] 3
12 Vol. 45 No. SIG 3(ACS 5) Responsive Link 61 3 Responsive Link Table 3 Speed vs. power on Responsive Link. Modulation (Mbaud) Data Speed (Mbps) Event Latency(µsec) Power (W) Responsive Link Fig. 11 Hop counts vs. latency of Responsive Link. 100 [Mbaud] 1 8 byte Latency of Event =2.1[µsec] + 1.0[µsec] n [hops] 2.1 [µsec] 1 [hop] 1.0 [µsec] 12) Gigabit Ethernet Myrinet 13) 4 [byte] 10 [µsec] 11 Responsive Processor 25 [Mbaud] Responsive Link ideal OT Responsive Processor RT-OS RT- Frontier 14) OS ideal OT 12 RMT Processor Fig. 12 Layout of RMT Processor. 4.2 RMT Processor RMT Processor Responsive Link Responsive Link RMT Processor Responsive Link 800 [Mbaud] 8 DDR SDRAM 256 [MB] 256 RMT Processor 1 Systemon-a-chip RMT Processing Unit 8way SMT Responsive Link PCI64 USB2.0 IEEE1394 DDR SDRAM I/F DMAC PWM 12 RMT Processor
13 62 Mar RMT 6 [M gates] Responsive Link [k gates] 0.13µm CMOS 8 Cu 14 [M gates] 10.0 [mm] 10.0 [mm]=100 [mm 2 ] BGA 40 [mm] 40 [mm] Core 1.0 [V] I/O 2.5 [V] 8 [W] 5. Responsive Link WG IPSJ-TS 0006:2003 2) ISO/IEC JTC1 SC25 WG4 3) 6. Responsive Link Responsive Link Hot-Plug&Play Responsive Link PRESTO SORST Responsive Processor COE RMT Processor Responsive Link WG6 ISO/IEC JTC1 SC25 WG4 Responsive Link SG DHRC 1) Vol.19, No.3, pp (2001). 2) index.html 3) sc25.html 4) Vol.36, No.7, pp (1995). 5) CODA Vol.J78 D I, No.8, pp (1995). 6) Liu, J.W.S.: Real-Time Systems, pp , Prentice Hall (2000). 7) (2003). 8) (2002). 9) Halsall, F.: Data Communications, Computer Networks, and Open Systems, Forth Edition, Addison-Wesley Publishing Company (1995). 10) Vol.44, No.1, pp.6 13 (2003). 11) Responsive Multithreaded Processor ARC-145 pp (2003). 12) OS µ PULSER Vol.98, No.687, pp (1999). 13) 14) Kobayashi, H. and Yamasaki, N.: Scheduling Imprecise Computations with Wind-up Parts, 19th International Conference on Computers
14 Vol. 45 No. SIG 3(ACS 5) Responsive Link 63 and Their Applications, pp (2003). ( ) ( ) LSI IEEE
A Responsive Processor for Parallel/Distributed Real-time Processing
E-mail: yamasaki@{ics.keio.ac.jp, etl.go.jp} http://www.ny.ics.keio.ac.jp etc. CPU) I/O I/O or Home Automation, Factory Automation, (SPARC) (SDRAM I/F, DMAC, PCI, USB, Timers/Counters, SIO, PIO, )
353 ISO/IEC JTC1 SC LSI 1 1 ASIC RISC SPARC 4 Fig. 1 1 Fig. 1 Diagram of Responsive Processor [2] [6] [7] [8] [9] 4 PCI USB RS 232C A/D D/A PWM
![353 ISO/IEC JTC1 SC LSI 1 1 ASIC RISC SPARC 4 Fig. 1 1 Fig. 1 Diagram of Responsive Processor [2] [6] [7] [8] [9] 4 PCI USB RS 232C A/D D/A PWM](/thumbs/91/106429053.jpg "353 ISO/IEC JTC1 SC LSI 1 1 ASIC RISC SPARC 4 Fig. 1 1 Fig. 1 Diagram of Responsive Processor [2] [6] [7] [8] [9] 4 PCI USB RS 232C A/D D/A PWM")
352 Vol. 19 No. 3, pp.352 361, 2001 1 2 Responsive Processor for Parallel/Distributed Real Time Control Nobuyuki Yamasaki 1 and Toshihiro Matsui 2 In this paper, we propose and design Responsive Processor
Microsoft PowerPoint - resp_link.ppt
分 散 制 御 のアプリケーション 分 散 制 御 用 リアルタイム 通 信 規 格 : Responsive Link 慶 應 義 塾 大 学 理 工 学 部 情 報 工 学 科 山 﨑 信 行 E-mail: yamasaki@ics.keio.ac.jp URL: http://www.ny.ics.keio.ac.jp/ 各 種 ロボット 自 動 車 VOD (Video On Demand)
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The copyright of this material is retained by the Information Processing Society of Japan (IPSJ). The material has been made available on the website
The copyright of this material is retained by the Information Processing Society of Japan (IPSJ). The material has been made available on the website by the author(s) under the agreement with the IPSJ.
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