2004 OS : : : 1G01P033-1 :

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1 2004 OS : : : 1G01P033-1 :

2 MINIX ARM Current Program Status Register Memory Management Unit CerfCube CerfCube I-Boot TTY

3 pipe write/read (1) (2)

4 2.1 MINIX USR Program Status Register ARM L1 Page Table Entries TTB L2 Page Table Entries L1 Page Table Walk L2 Page Table Walk IRQ x ARM x ARM write/read write/read (1) write/read (2)

5 MMU CerfCube CerfCube write (µsec)

6 PC Linux FreeBSD OS OS OS OS OS MINIX ARM MINIX

7 Abstract In recent years, due to the requirement of more sophisticated applications on embedded systems, general-purpose operating systems which have been used on desktop PC s, such as Linux and FreeBSD, are ported to embedded systems. These operating systems support separated memory region, which improves a security of a system, though it decreases the speed of context switch and increases the overhead of interprocess communications. In our research, first we ported MINIX, one of a general-purpose operating system which is fairly small OS, to ARM architecture to measure the processing time of interprocess communication pipe. From the result, we found out the unnecessary initialization of block chache and removed it.

8 1 1.1 PDA LAN Bluetooth PC Linux FreeBSD OS OS OS GUI PC OS OS 100 OS 1.2 OS OS MINIX ARM MINIX[1] MINIX, ARM CerfCube 3 MINIX ARM 4 ARM-MINIX pipe 5?? 1

9 2 MINIX ARM CerfCube 2.1 MINIX MINIX Andrew S. Tanenbaum UNIX V7 1 OS 4 OS OS Atari, Amiga, Macintosh, SPARC MINIX : MINIX 1 C kernel 1 1 MINIX 2.0 POSIX 2 MINIX 2.0 x86 SPARC 2

10 3 POSIX API fork exec chdir stat 4 init, sh, ls init MINIX POSIX API POSIX API sendrec MINIX send, receive, sendrec 3 POSIX API MINIX 2.2 ARM ARM ARM(Advanced RISC Machine) CPU ARM ARM Acorn Computers RISC(Reduced Instruction Set Computer) PC ARM User 2.2 User

11 2.2: USR r0 r15 r0 r12 r13, r14, r15 3 r13: sp(stack pointer) r14: lr(link register) r15: pc(program counter) cpsr(current program status register), spsr(saved program status register) Current Program Status Register cpsr cpsr?? cpsr flags, status, extension, control 4 ARM 7 2 cpsr 4

12 2.3: Program Status Register Abort(ABT), Fast Interrupt Request(FIQ), Interrupt Request(IRQ), Supervisor(SVC), System(SYS), Undefined(UND) 6 cpsr User(USR) cpsr Control Field Condition Flag 2.1 cpsr Abort ABT yes Fast Interrupt Request FIQ yes Interrupt Request IRQ yes Supervisor SVC yes System SYS yes Undefined UND yes User USR no : cpsr 2.4 ARM

13 2.4: ARM USR cpsr SYS USR USR SVC r13, r14 r13, r14 r13 svc, r14 svc r13 svc, r14 svc user r13 usr, r14 usr r0 r12 cpsr I F 2 ( 2.3 ) I 1 IRQ F 1 FIQ cpsr ALU(Arithmetic Logic Unit) ARM 6

14 2.2 Q Saturation / V overflow C Carry Z Zero 0 N Negative : : : : 2.5 (pc) 2.5: 3 3 pc 8 pc 2 pc 7

15 (KB) (KB) PTE Master/Section L Fine L2 4 1, Coarse L : MMU 2.6: L1 Page Table Entries Memory Management Unit ARM MMU 2 1 L1 2 L2 L1 Master Section L1 L2 1MB PTE(Page Table Entry) L1 4GB 1MB 4096 PTE L1 4 1MB Fine L Coarse L2 256 Fault MMU PTE 2 ( 2.6 ) PTE 1MB 12 PTE 12 Coarse PTE Fine PTE L2 L2 1KB 4KB Fault PTE Prefetch Abort Data Abort L1 CP15 2 CP15 2 TTB(Translation Table Base Address) L1 8

16 : TTB L2 4 Large Page 64KB Small Page 4KB Tiny Page 1KB Fault Page 2.8: L2 Page Table Entries MMU PTE 2 ( 2.8 ) Large PTE 64KB 4 64KB 4 16KB Small PTE 16KB Large PTE 4 4KB 4 1KB Tiny PTE 1KB 1 Fault PTE Prefetch Abort Data Abort Translation Lookaside Buffer TLB(Translation Lookaside Buffer) PTE ARM TLB 2 TLB TLB 9

17 MMU TLB TLB TLB PTE TLB TLB 2.9: L1 Page Table Walk 2.10: L2 Page Table Walk MMU 1MB ( 2.9) master L1 1 MMU 12 L1 Master PTE 1MB PTE TLB PTE

18 I F RESET SVC 1 1 DABT ABT 1 0 FIQ FIQ 1 1 IRQ IRQ 1 0 PABT ABT 1 0 SWI SVC 1 0 UNDEF UND : KB ( 2.10) L1 Master PTE PTE 2 01 PTE Coarse Page L Fine Page L L2 PTE PTE ARM Reset(RESET), Data Abort(DABT), Fast Interrupt Request(FIQ), Interrupt Request(IRQ), Prefetch Abort(PABT), Software Interrupt(SWI), Undefined Instruction(UNDEF) 7 ARM 1. cpsr spsr 2. pc lr 3. cpsr I F 4. pc RESET RESET RESET cpsr I F 1 SVC 11

19 RESET 1 DABT 2 FIQ 3 IRQ 4 PABT 5 SWI 6 UNDEF 6 2.5: DABT MMU USR I 1 ABT FIQ FIQ FIQ DABT IRQ cpsr F 1 FIQ I F 1 FIQ IRQ IRQ 2 IRQ FIQ DABT (cause) cpsr I 1 IRQ I 1 IRQ PABT I 1 ABT SWI swi I 1 SVC UNDEF ARM Thumb 3 ARM UNDEF I 1 UND 3 16bit 12

20 USR IRQ 2.11 USR IRQ pc IRQ lr irq cpsr spsr irq cpsr I (IRQ) 2.11: IRQ ARM 0x x c MMU 0xffff0000-0xffff001c 2.6 ( ) RESET 0x xffff0000 UNDEF 0x xffff0004 SWI 0x xffff0008 PABT 0x c 0xffff000c DABT 0x xffff0010 0x xffff0014 IRQ 0x xffff0018 FIQ 0x c 0xffff001c 2.6: 13

21 b <address> b <address> b 32MB ldr pc, [pc, #offset ] ldr pc offset ±0-4KB ldr 4KB mov pc, #immediate mov immediate pc immediate 8bit FIQ FIQ FIQ 0x c 0x : ldr pc, [pc, #reset_handler] 0x : ldr pc, [pc, #undef_handler] 0x : ldr pc, [pc, #swi_handler] 0x c: ldr pc, [pc, #pabt_handler] 0x : ldr pc, [pc, #dabt_handler] 0x : ldr pc, [pc, #none_handler] 0x : ldr pc, [pc, #irq_handler] 0x c: sub lr, lr, #4 stmdb bl ldmdb movs sp!, {r0-r3} fiq_isr sp!, {r0-r3} pc, lr 2.3 CerfCube CerfCube CerfCube Intrinsyc Software CerfBoard CurfCube 7cm CPU Intel Strong ARM SA MHz 16MB 32MB SDRAM Ethernet USB (CurfCube ) CerfCube i-linux 2.4 Windows CE OS 3.0 i-linux 2.4 i-linux CerfCube 14

22 CPU SDRAM Ethernet Intel StrongARM SA MHz Intel Strata (16-bit ) 32MB SDRAM (32-bit ) 3-RS232C (2 ) 1 LED 10 Base-T Type I Type II CF USB Type B 5.0 VDC 400mA ( ) 57mm 69mm 2.7: CerfCube Flash Unused (1 128KB) 0 Bootloader (I-Boot) 0x KB 0x0001FFFF 1-2 Bootloader Reservec 0x KB 0x0005FFFF 3-10 Linux Kernel 0x MB 0x0015FFFF JFFS2 FileSystem 0x MB 0x00FFFFFF 0x xBFFFFFFF RAM 0xC MB 0xC1FFFFFF 2.8: CerfCube 15

23 CerfCube WWW Web Ethernet minicom CerfCube Intrinsync Software I-Boot i-linux I-Boot Linux Windows CE i-linux ENTER I-Boot I-Boot I-Boot I-Boot I-Boot Flash RAM Flash RAM Flash TFTP RAM RAM RAM 0x24 0x016f2818 0x28 i-linux 4.1 bzimage 0xc xc

24 3 3.1 ARM x86 MINIX x86-minix, ARM MINIX ARM-MINIX x86-minix (a) (b) (c) TTY x86-minix boot boot MINIX MINIX kernel mm(memory Manager) fs(file System) init MINIX kernel mm fs init 17

25 a.out BSS MINIX 1 CerfCube I-Boot TFTP 3.2 boot 0xc kernel 0xc mm 0xc fs 0xc init 0xc boot CerfCube 0xc boot boot kernel mm fs init 4K ARM MINIX ELF x86 MINIX a.out BSS kernel 3.1: x x86-minix

26 3.2: ARM ARM 0 L1 PTE PTE MINIX 3.3: x86 19

27 3.4: ARM 3.4 x86-minix 0, 1, 3 ARM-MINIX SVC SYS USR SYS USR 3.1 x86-minix ARM-MINIX 1( ) 0 SVC 2( ) 1 SYS 3( ) 2 USR 4( ) 3 USR 3.1: 3.5 send, receive, sendrec 20

28 x86 (IDT 1 ) x86-minix IDT ARM-MINIX ARM 0x xffff0000 CerfCube RAM MMU RAM 0xffff : ARM- MINIX RAM I-Boot TFTP RAM CerfCube RAM ARM-MINIX RAM 1 Interrupt Descriptor Table 21

29 3.7.2 CerfCube OS Timer Counter Register(OSCR) OS Timer Match Register( OSMR) OSMR TTY TTY(Tele-TYpewriter) x86 MINIX TTY ARM MINIX MINIX I/O MINIX 2 I/O ( 3.6) 3.6: 3.9 pipe, write/read 22

30 3.9.1 pipe pipe pipe / write/read / write/read write/read 3.7 write/read 0 2 ( ) (sys copy) 1KB 1KB 2.345KB 1KB, 1KB, 0.345KB 3 sys copy 3.7: write/read 23

31 TICK TIME initticks, dumpticks TICK TIME #define TICK_TIME asm("mcr p0, 0, r0, c0, c0": : : "r0") mcr ARM - ARM UNDEF ARM-MINIX UNDEF OSCR tick time TICK TIME 1.4µsec initticks tick time dumpticks tick time printk 24

32 4 4.1 (1) write/read / : write/read (1) 1024 write 256, 512, 768, / : write (µsec) sys copy

33 lseek 0 / FIFO(First In First Out) lseek (2) : write/read (2) 4.3 write 1KB ARM-MINIX 7KB 1 write lseek ESPIPE 26

34 4.3: 1 27

35 5 ARM MINIX ARM-MINIX write 1220µsec ARM-MINIX 28

36 29

37 [1] A.S. +A.S. : MINIX,, [2] : 486,, [3] Andrew N. SLOSS: ARM System Developer s Guide, Elsevier, [4] Adam Wiggins, Harvey Tuch, Volkmar Uhlig, and Gernot Heiser Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor 30

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プロセッサ・アーキテクチャ 2. NII51002-8.0.0 Nios II Nios II Nios II 2-3 2-4 2-4 2-6 2-7 2-9 I/O 2-18 JTAG Nios II ISA ISA Nios II Nios II Nios II 2 1 Nios II Altera Corporation 2 1 2 1. Nios II Nios II Processor Core JTAG interface