Microsoft PowerPoint - ●日立伊部様CREST_Ibe4
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1 CREST ディペンダブル VLSI システムの基盤技術 領域会議 2011 年 7 月 1,2 日科学技術振興機構 CMOS テ ハ イスの中性子起因ソフトエラーの定量化と対策技術開発戦略ー過去から未来へー IRPS2011での招待講演 IRPS 2011レポート 中性子線がボードのCPUやメモリなどを誤動作させる仕組み で紹介 [ ] ( 株 ) 日立製作所横浜研究所伊部英史, IEEE Fellow
2 International Reliability Physics Symposium IRPS2011, April 12-14, 2011, Monterey, CA P3C-2 Quantification and Mitigation Strategies of Neutron Induced Soft-Errors in CMOS Devices and Components -The Past and Future- Hitachi, Ltd. E. Ibe, Fellow, IEEE, Ken-ichi Shimbo, Hitoshi Taniguchi, Tadanobu Toba, Koji Nishi and Yoshio Taniguchi
3 目的 1 地上の中性子に起因する電子システムへの最近の脅威のレヒ ュー 2 核反応から電子装置の障害に到る物理フ ロセスのレヒ ュー 3 最近のシステムレヘ ルの障害の定量化と対策上の問題 4 DOUB(Design On Upper Bound: 上限障害レヘ ルに基づく設計 ) : システムレヘ ル対策の新しい障害対策戦略の提言 5 LABIR(inter-LAyer Built-In Reliability): 低オーハ ーヘット 障害対策技術新コンセフ トの提案 1
4 エラーアト レス領域の爆発的拡大 (SRAM) およそ 100x100 ヒ ット nm nm BL nm WL 65nm Ibe, WDSN (2009) nm 22nm * 原点で核反応を 回発生させた時の全エラーの分布 22nm では 100 万ヒ ット領域に影響. MCU( 一回の核反応で同時に複数のヒ ットがエラーになる現象 ) の多重度は 100 ヒ ットを超える場合あり 冗長系の無力化 およそ 1000x1000 ヒ ット 2
5 航空機高度での自動操縦装置 TMR のエラー * σ SEU =3x10-13 cm 2 /bit:unreasonably high, suggesting neutron impact clearly ~x300 Altitude (m) :altitude and latitude of TMR error Latitude ( ) * Boeing 777 Autopilot data ;Edited from the data in Normalized Neutron Flux (-)[JESD89A] 3
6 高耐性 FF とクロック系起因のエラー Soft Error Rate (A.U.) 1.00E E E E E E-05 Seifert, SELSE3 (2007) SEUT_SER Local Clock Error Even hardened FFs and clock lines are getting more and more vulnerable to soft-error with scaling 1.00E Design Rule (nm) 4
7 セット / リセット系からの SET ノイズ Cabanas-Holman, TNS (2009) Reset D Q CLK Q Rough range for terrestrial neutron events 5
8 装置 (Server, Router, MCU) レベルの SER All active parts(cpu,chip 1,Chip2,..) have their own Soft Error Rates (SERs) depending on functionality and application. Chip1 CPU (FFs, logic gates, SRAMs) Chip3 All portions are uniformly irradiated by terrestrial neutrons. Printed Circuit Board (PCB) Chip2 Capacitor (Passive part:seu immune) 6
9 装置 (Server, Router, MCU) レベルの SER High energy neutron Nuclear reaction Chip1 CPU (FFs, logic gates, SRAMs) Chip3 Spallation Reaction Printed Circuit Board (PCB) Chip2 Capacitor (Passive part:seu immune) 7
10 装置 (Server, Router, MCU) レベルの SER Chip1 CPU (FFs, logic gates, SRAMs) Nuclear reaction Chip3 Ion hit Ion hit Secondary ion Printed Circuit Board (PCB) Chip2 Capacitor (Passive part:seu immune) 8
11 装置 (Server, Router, MCU) レベルの SER Chip1 CPU (FFs, logic gates, SRAMs) Nuclear reaction Ion hit Single Event Transient (SET) propagation Single Event Effect (Fault/Transient) Chip3 Transient pulse Printed Circuit Board (PCB) Chip2 Capacitor (Passive part:seu immune) 9
12 装置 (Server, Router, MCU) レベルの SER Chip1 CPU (FFs, logic gates, SRAMs) Nuclear reaction Chip3 Ion hit Transient pulse Upset Single Event Upset Printed Circuit Board (PCB) Chip2 Capacitor (Passive part:seu immune) 10
13 装置 (Server, Router, MCU) レベルの SER Chip1 CPU (FFs, logic gates, SRAMs) Nuclear reaction Chip3 Ion hit Transient pulse Upset System Failure Failure Printed Circuit Board (PCB) Chip2 Capacitor (Passive part:seu immune) 11
14 フリップフロップへの直接効果 Difficulty 1: Complexity in F/Fs error modes SET in Set/Reset line=mnt Direct SEU by secondary ion hit=seu CLK D Q Q Erroneous clock by SET in clock line=mnt 12
15 様々なロジックゲートのマスキング効果 Secondary ion Logic masking L B AND Difficulty 2: Intrinsic difficulty in combinational logics D Q A H Decay L CLK Q SET Electric masking Latch window Window masking (Timing derating) 13
16 問題は マルチノート トランシ ェント (MNT) やク ローハ ル制御系での新しいエラーモート の全てを定量化しきれるのか? ロシ ックケ ートの MNT に有効な対策はあるのか? ( 冗長系は消費電力の点でも回避方向が鮮明になりつつある リトライ ロールバックが主流へ ) 14
17 問題は マルチノート トランシ ェント (MNT) やク ローハ ル制御系での新しいエラーモート の全てを定量化しきれるのか? ロシ ックケ ートの MNT に有効な対策はあるのか? ( 冗長系は消費電力の点でも回避方向が鮮明になりつつある リトライ ロールバックが主流へ ) 新発想が必要! 14
18 システムレベル SER 定量化の従来法 Estimating: Raw SET SET g raw SET g raw = in total logic gates in a chip N g j= 1 n g j set j, g raw With modified SER m raw and SET g raw by multiplying masking factors ω g k (<1) or ω m s (<1), mean chip-level SER SER c L is estimated: c L k g k SER = ω SET g raw 15
19 ロジックゲートの SER 測定法例 Makino, TNS (2009) Buffer Irradiation (Mostly heavy ion) SET Pulse width = (number of 1 s) x delay in one buffer 16
20 Frequency (A.U.) Chip/ Board Level SER (A.U.) 従来法の問題点 Average Target Level (TL) (a) NG (b) OK Reliability cannot be guaranteed without knowledge of variation Variation depends on circuitry application, susceptibility in gates, global control lines (clock, set/reset) to SETs. Estimation of the variation is much more difficult and time/cost consuming than that of the average. 17
21 DOUB* の提案 SET g raw is the ultimate upper bound of SER c L because all the masking factor ω g k<=1. Thus, c L SER = SET g raw where, A = denotes the upper bound of A. A<=A = for all possible conditions of A. In order to obtain more realistic upper bound, one may pursue, c L k g k SER = ω SET g raw ω g k Upper bound of masking factor *Design On Upper Bound 18
22 上限の設定例 simpler upper bound of logic SER in a chip UB p : Bound due to hitting probability Chip level SER φ N j= 1 g N g n g j σ j, g hit φ j= 1 n g j s j, g node σ j, g hit where, :effective cross section of hitting on storage s j, g node UB a : due to area nodes in the j-th gate. Easily calculated by using Monte- Carlo soft-error simulator like CORIMS : surface area of storage nodes in the j-th gate. Immediately calculated by using design data. 19
23 上限に基づくチップ / ボードレベル耐性設計例 Start Estimation of current level UB of Chip/Board UB OK? No Yes End: Don t Care Chip/ board Implementation of higher level mitigation 1 st order: replacement of device. Highest: LABIR Final choice for Eco : Space redundancy like duplication,. TMR 20
24 チップ / ホ ート 部分照射 / 対策技術 Most vulnerable part in network router causing reboot failure was identified as 1SRAM compared to 2CPU and 3 FPGA by partial board irradiation test. First order mitigation: Simple replacement of SRAM to DRAM is applied to where speed is not critical. Neutron beam size (10cm ) CPU Access memory architecture CPU Memory Map Critical data 14.5MB 3FPGA FPGA Set A (SRAM only) Set B (DRAM +SRAM) SRAM (14.5MB) DRAM with ECC (11.8MB) SRAM (2.7MB) ECC: Error Correction Code 285mm 1SRAM (+DRAM) (excluded) SRAM CPU 2CPU 400mm 21
25 一次オーダ低減策の例 Vulnerable chip that cause rebooting failure in the network switch was identified as SRAM chip among SRAM, DRAM, FPGA, and CPU chips by using partial neutron irradiation tests. SRAMs that do not require speed are replaced by DRAMs with ECC. Reduction (about one tenth) in failure rates are consistent between measured susceptibility in accelerated and field tests. Rebooting Failure Cross Section (A.U.) Neutron Irrad. Test (18hrs) Rebooting Failure Rate(A.U.) ~1/8 ~1/9 Field Test in Tokyo (~1year) SRAM only SRAM +DRAM SRAM SRAM only +DRAM Shimbo, SELSE7 (2011) 22
26 Integrated collaboration among stack layers. Frequerncy (A.U.) Additional current peaks Ep= I dd (A) LABIR のコンセフ トと例 Senseamp Error symptom Current peaks observed in SRAM V dd line under neutron irradiation (Ibe, CICC, 2006) Checkpoint p-well Step Step n-1 n-1 Ion hit n-well Step Step n Rollback Symptom detection Interruption to pipeline process Rollback to checkpoint Error symptom Step Step n+1 n+1 23
27 Cross Layer Reliability( 米国最新動向 ) 微細化に伴いコンホ ーネントの信頼性は予測困難になっているが 従来の対策はコストがかかり消費電力も問題 ( 今後の対策は冗長系は使えない : リトライが基本 ) 単一階層 ( デバイス 回路 CPU, ファームウェア OS ミト ルウェア アフ リケーション) での対策は最早不可能だが 社会システムのすべての面で問題が顕在化 階層間が協調して消費電力の少ない対策を進める構想 Cross Layer Reliabilityを提唱 米国の国プロ提案 ( 科研費レヘ ルで構想研究完 ) 社会システム : 航空宇宙 車載機器 医療 テ ータセンタ スハ コン インフラ セキュリテイ 主な参加組織 ( 全 82 組織 ) 国立研究所 LANL, Sandia, JPL, NRL. 空軍研究所 企業 Intel, マイクロソフト, TI, Cisco, Oracle, IBM, Freescale, Nokia, ロッキート, ホ ーインク, Xilinx, ARM, GE, Medtronic, 他 大学 UC ハ ークレー, イリノイ大, トロント大, スタンフォート 大, ミシカ ン大, 南カリフォルニア大, テキサス大, カリフォルニア大, Caltech, フ リンストン大, 他 図 Cross Layer Reliability のイメーシ 24
28 結言 SRAM のスケーリングが 22nm までに到ると 一回の中性子核反応でエラーになるビットの領域が 100 万ビットの広さに及ぶ MNT や様々な新しいモードに起因する装置障害は今後一層加速する見通し 簡便な段階的装置 SER 耐性の定量化と対策の戦略 DOUB (Design On Upper Bound) を提案 部分ボード照射法を一次オーダの定量化 対策手段として紹介 LABIR (inter-layer Built-In Reliability) を冗長系でない低オーバーヘッドの DOUB の最高レベル耐性向上策として提案. 25
29
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