ADV7390/ADV7391/ADV7392/ADV7393: SD ／ HD低消費電力、チップ・スケール、10 ビットビデオ・エンコーダ

Transcription

1 SD/HD ADV739/ADV739/ADV7392/ADV DAC SD 6 26MHz DAC ED 8 26MHz DAC HD 4 297MHz DAC 37mA DAC 4:2:2 YCrCb SD ED HD 4:4:4 RGB SD CVBS S Y/C YPrPb SD ED HD RGB SD ED HD LFCSP 325mm 5mm LFCSP 46mm 6mm LFCSP DAC DAC DAC 74.25MHz 8//6HD SMPTE 274M 8i 296M 72p 24M 35i NTSC M PAL B/D/G/H/I/M/N PAL 6 NTSCPAL24.54MHz/ 29.5MHz Macrovision Rev 7..L SD Rev.2 ED VBI F SC CGMS WSS I 2 C SPI MPU 2.7V3.3V.8V 3.3.8V I/O 4 85 DVD STB ADV7393 DGND (2) V DD (2) SCL/ SDA/ ALSB/ MOSI SCLK SPI_SS SFL/ MISO AGND V AA GND_IO VDD_IO P5 TO P/ P7 TO P VBI DATA SERVICE INSERTION 4:2:2 TO 4:4:4 INPUT DEINTERLEAVE RGB/YCrCb TO YUV MATRIX ASYNC BYPASS ADD SYNC ADD BURST MPU PORT PROGRAMMABLE LUMINANCE FILTER PROGRAMMABLE CHROMINANCE FILTER SUBCARRIER FREQUENCY LOCK (SFL) YUV TO YCrCb/ RGB SIN/COS DDS BLOCK 6 FILTER 6 FILTER ADV739x MULTIPLEXER -BIT DAC -BIT DAC 2 -BIT DAC 3 DAC DAC 2 DAC 3 YCrCb HDTV TEST PATTERN GENERATOR PROGRAMMABLE ED/HD FILTERS SHARPNESS AND ADAPTIVE FILTER CONTROL YCbCr TO RGB MATRIX 4 FILTER POWER MANAGEMENT CONTROL VIDEO TIMING GENERATOR 6x/4x OVERSAMPLING PLL REFERENCE AND CABLE DETECT R SET RESET HSYNC VSYNC 5,343,96 5,442,355 4,63,63 4,577,26 4,89,98 CLKIN PV DD PGND EXT_LF COMP REV. REVISION 26 Analog Devices, Inc. All rights reserved MT

2 ADV739/ADV739/ADV7392/ADV7393

3 ADV739/ADV739/ADV7392/ADV7393 /6 Revision : Initial Version

4 ADV739/ADV739/ADV7392/ADV7393 HD 72p/8i/35i 4297MHz YCrC RGB CGMS 72p/8i CGMSB 72p/8i DDR ED 525p/625p 826MHz Y PrPb YCrCb-RGB Macrovision Rev.2 525p/625p CGMS 525p/625p CGMSB 525p DDR EIA/CEA-86B SD 626MHz Y PrPb DNR Luma-SSAF TM PrPb SSAF TM /S VCR FF/RW Macrovision Rev 7..L CGMS WSS EIA/CEA-86B ADV739/ADV739/ADV7392/ADV7393 D/A 3 2.7V/3.3V DAC SD HD CVBS S YC YPrPb/RGB TV DAC ADV739/ADV739 SDRSD DDRHD 8 ADV7392/ADV SD RGB EAV/SAV I 2 CSPI ADV739x. ADV739x Clock Frame Input Resolution I/P 2 Rate (Hz) (MHz) Standard 72 x 24 P x 288 P x 48 I ITU-R BT.6/ x 576 I ITU-R BT.6/ x 48 I NTSC Square Pixel 72 x 576 I PAL Square Pixel 72 x 483 P SMPTE 293M 72 x 483 P BTA T-4 72 x 483 P ITU-R BT x 576 P 5 27 ITU-R BT x 483 P ITU-R BT x 576 P 5 27 ITU-R BT x 35 I SMPTE 24M 92 x 35 I SMPTE 24M 28 x 72 P 6, 5, 3, SMPTE 296M 25, x 72 P 23.97, SMPTE 296M 59.94, x 8 I 3, SMPTE 274M 92 x 8 I SMPTE 274M 92 x 8 P 3, 25, SMPTE 274M 92 x 8 P 23.98, SMPTE 274M 92 x 8 P ITU-R BT.79-5 ED/HD 2 IP

5 ADV739/ADV739/ADV7392/ADV7393 T MIN T MAX Parameter Conditions Min Typ Max Unit SUPPLY VOLTAGES V DD V V DD_IO V PV DD V V AA V POWER SUPPLY REJECTION RATIO.2 %/% V DD.7.89V PV DD.7.89V V AA V V DD_IO V T MIN T MAX Parameter Conditions Min Typ Max Unit f CLKIN SD/ED 27 MHz ED (at 54 MHz) 54 MHz HD MHz CLKIN High Time, t 9 4 % of one clock cycle CLKIN Low Time, t 4 % of one clock cycle CLKIN Peak-to-Peak Jitter Tolerance 2 ±ns SD ED 525p/625p HD V DD.7.89V PV DD.7.89V V AA V V DD_IO V T MIN T MAX Parameter Conditions Min Typ Max Unit Full-Drive Output Current R SET = 5 Ω, R L = 37.5 Ω ma Low Drive Output Current R SET = 4.2 kω, R L = 3 Ω 4.3 ma DAC-to-DAC Matching DAC, DAC 2, DAC 3 2. % Output Compliance, V OC.4 V Output Capacitance, C OUT pf Analog Output Delay 6 ns DAC Analog Output Skew DAC, DAC 2, DAC 3 ns 5%DAC 5%

6 ADV739/ADV739/ADV7392/ADV7393 V DD.7.89V PV DD.7.89V V AA V V DD_IO V T MIN T MAX Parameter Conditions Min Typ Max Unit Input High Voltage, V IH 2. V Input Low Voltage, V IL.8 V Input Leakage Current, I IN V IN = V DD_IO ± µa Input Capacitance, C IN 4 pf Output High Voltage, V OH I SOURCE = 4 µa 2.4 V Output Low Voltage, V OL I SINK = 3.2 ma.4 V Three-State Leakage Current V IN =.4 V, 2.4 V ± µa Three-State Output Capacitance 4 pf MPU V DD.7.89V PV DD.7.89V V AA V V DD_IO V T MIN T MAX Parameter Conditions Min Typ Max Unit MPU PORT, I 2 C MODE See Figure 5 SCL Frequency 4 khz SCL High Pulse Width, t.6 µs SCL Low Pulse Width, t 2.3 µs Hold Time (Start Condition), t 3.6 µs Setup Time (Start Condition), t 4.6 µs Data Setup Time, t 5 ns SDA, SCL Rise Time, t 6 3 ns SDA, SCL Fall Time, t 7 3 ns Setup Time (Stop Condition), t 8.6 µs MPU PORT, SPI MODE See Figure 6 SCLK Frequency MHz SPI_SS to SCLK Setup Time, t 2 ns SCLK High Pulse Width, t 2 5 ns SCLK Low Pulse Width, t 3 5 ns Data Access Time after SCLK Falling Edge, t 4 35 ns Data Setup Time prior to SCLK Rising Edge, t 5 2 ns Data Hold Time after SCLK Rising Edge, t 6 ns SPI_SS to SCLK Hold Time, t7 ns SPI_SS to MISO High Impedance, t8 4 ns

7 ADV739/ADV739/ADV7392/ADV7393 V DD.7.89V PV DD.7.89V V AA V V DD_IO V T MIN T MAX Parameter Conditions Min Typ Max Unit VIDEO DATA AND VIDEO CONTROL PORT 2, 3 4 Data Input Setup Time, t SD 2. ns ED/HD-SDR 2.3 ns ED/HD-DDR 2.3 ns ED (at 54 MHz).7 ns 4 Data Input Hold Time, t 2 SD. ns ED/HD-SDR. ns ED/HD-DDR. ns ED (at 54 MHz). ns 4 Control Input Setup Time, t SD 2. ns ED/HD-SDR or ED/HD-DDR 2.3 ns ED (at 54 MHz).7 ns 4 Control Input Hold Time, t 2 SD. ns ED/HD-SDR or ED/HD-DDR. ns ED (at 54 MHz). ns 4 Control Output Access Time, t 3 SD 2 ns ED/HD-SDR, ED/HD-DDR, or ns ED (at 54 MHz) 4 Control Output Hold Time, t 4 SD 4. ns ED/HD-SDR, ED/HD-DDR, or 3.5 ns ED (at 54 MHz) PIPELINE DELAY 5 SD CVBS/YC Outputs (2x) SD oversampling disabled 68 clock cycles CVBS/YC Outputs (8x) SD oversampling disabled 79 clock cycles CVBS/YC Outputs (6x) SD oversampling enabled 67 clock cycles Component Outputs (2x) SD oversampling disabled 78 clock cycles Component Outputs (8x) SD oversampling disabled 69 clock cycles Component Outputs (6x) SD oversampling enabled 84 clock cycles ED Component Outputs (x) ED oversampling disabled 4 clock cycles Component Outputs (4x) ED oversampling disabled 49 clock cycles Component Outputs (8x) ED oversampling enabled 46 clock cycles HD Component Outputs (x) HD oversampling disabled 4 clock cycles Component Outputs (2x) HD oversampling disabled 42 clock cycles Component Outputs (4x) HD oversampling enabled 44 clock cycles RESET CONTROL RESET Low Time ns SD ED 525p/625p HD SDR DDR 2 ADV7392/ADV7393 P[5:] ADV739/ADV739 P[7:] 3 HSYNC VSYNC 4 5

8 ADV739/ADV739/ADV7392/ADV Parameter Conditions Min Typ Max Unit STATIC PERFORMANCE Resolution Bits Integral Nonlinearity (INL) R SET = 5 Ω, R L = 37.5 Ω.5 LSBs Differential Nonlinearity (DNL), 2 R SET = 5 Ω, R L = 37.5 Ω.5 LSBs STANDARD DEFINTION (SD) MODE Luminance Nonlinearity.5 ±% Differential Gain NTSC.5 % Differential Phase NTSC.6 Degrees Signal-to-Noise Ratio (SNR) 3 Luma ramp 58 db Flat field full bandwidth 75 db ENHANCED DEFINITION (ED) MODE Luma Bandwidth 2.5 MHz Chroma Bandwidth 5.8 MHz HIGH DEFINITION (HD) MODE Luma Bandwidth 3. MHz Chroma Bandwidth 3.75 MHz DAC DAC2 DAC3 2 DNL DAC ve DNL ve DNL 3 ADV7392/ADV Parameter Conditions Min Typ Max Unit NORMAL POWER MODE, 2 3 I DD SD (6x oversampling enabled), CVBS 33 ma SD (6x oversampling enabled), YPrPb 68 ma ED (8x oversampling enabled) 4 59 ma HD (4x oversampling enabled) 4 8 ma I DD_IO ma 5 I AA DAC enabled 5 ma All DACs enabled 22 ma I PLL 4 ma SLEEP MODE I DD 5 µa I AA.3 µa I DD_IO.2 µa I PLL. µa R SET 5Ω DAC 2 75% 3 I DD 4 SDRDDR 5 I AA DAC

9 ADV739/ADV739/ADV7392/ADV t 9 ADV739/ADV739 3 ADV7392/ ADV t t t 2 t 3 t 4 CLKIN t 9 t t 2 CONTROL INPUTS HSYNC VSYNC IN SLAVE MODE PIXEL PORT Cb Y Cr Y Cb2 Y2 Cr2 t t 3 CONTROL OUTPUTS IN MASTER/SLAVE MODE 2. t 4 SD8/ 4:2:2 YCrCb CLKIN t 9 t t 2 CONTROL INPUTS HSYNC VSYNC IN SLAVE MODE PIXEL PORT Y Y Y2 Y3 PIXEL PORT Cb Cr Cb2 Cr2 t t3 CONTROL OUTPUTS IN MASTER/SLAVE MODE 3. SD6 4:2:2 YCrCb t

10 ADV739/ADV739/ADV7392/ADV7393 CLKIN t 9 t t 2 CONTROL INPUTS HSYNC VSYNC IN SLAVE MODE PIXEL PORT Y Y Y2 Y3 PIXEL PORT Cb Cr Cb2 Cr2 t t3 CONTROL OUTPUTS IN MASTER/SLAVE MODE 4. SD6 4:4:4 RGB t CLKIN t 9 t t 2 CONTROL INPUTS HSYNC VSYNC PIXEL PORT G G G2 PIXEL PORT B B B2 t PIXEL PORT R R R2 CONTROL OUTPUTS 5. ED/HD-SDR6 4:2:2 YCrCb t 4 t CLKIN* t 9 t CONTROL INPUTS HSYNC VSYNC PIXEL PORT Cb Y Cr Y Cb2 Y2 Cr2 t 2 t t 2 t t 3 6. CONTROL OUTPUTS t 4 *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS x, BITS AND 2. ED/HD-DDR8/ 4:2:2 YCrCb HSYNC /VSYNC

11 ADV739/ADV739/ADV7392/ADV7393 CLKIN* t 9 t PIXEL PORT 3FF XY Cb Y Cr Y t 2 t t 2 t t 3 7. CONTROL OUTPUTS t 4 *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS x, BITS AND 2. ED/HD-DDR8/ 4:2:2 YCrCb EAV/SAV CLKIN t 9 t CONTROL INPUTS HSYNC VSYNC PIXEL PORT Cb Y Cr Y Cb2 Y2 Cr2 t 2 t t 3 8. CONTROL OUTPUTS ED 54MHz 8/ 4:2:2 YCrCb HSYNC /VSYNC t CLKIN t 9 t PIXEL PORT 3FF XY Cb Y Cr Y CONTROL OUTPUTS t t 2 t 3 t ED 54MHz 8/ 4:2:2 YCrCb EAV/SAV

12 ADV739/ADV739/ADV7392/ADV7393 Y OUTPUT b HSYNC VSYNC PIXEL PORT Y Y Y2 Y3 PIXEL PORT* Cb Cr Cb2 Cr2 a a = AS PER RELEVANT STANDARD. b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY.. ED-SDR 6 4:2:2 YCrCb HSYNC /VSYNC Y OUTPUT b HSYNC VSYNC PIXEL PORT Cb Y Cr Y a a(min) = 244 CLOCK CYCLES FOR 525p. a(min) = 264 CLOCK CYCLES FOR 625p. b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY.. ED-DDR 8/ 4:2:2 YCrCb HSYNC /VSYNC 6234-

13 ADV739/ADV739/ADV7392/ADV7393 Y OUTPUT b HSYNC VSYNC PIXEL PORT Y Y Y2 Y3 PIXEL PORT Cb Cr Cb2 Cr2 a a = AS PER RELEVANT STANDARD. b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. 2. HD-SDR 6 4:2:2 YCrCb HSYNC /VSYNC Y OUTPUT b HSYNC VSYNC PIXEL PORT Cb Y Cr Y a a = AS PER RELEVANT STANDARD. b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. 3. HD-DDR 8/ 4:2:2 YCrCb HSYNC /VSYNC

14 ADV739/ADV739/ADV7392/ADV7393 HSYNC VSYNC PIXEL PORT Cb Y Cr Y 4. SD PAL = 264 CLOCK CYCLES NTSC = 244 CLOCK CYCLES SDA t 3 t 3 t 5 t 6 t SCL t 2 t 7 t 4 t MPU I 2 C SPI_SS t t 2 t 3 t 7 SCLK MOSI X t 5 t 6 D7 D6 D5 D4 D3 D2 D D X X X X X X X X MISO t 4 t 8 X X X X X X X X X D7 D6 D5 D4 D3 D2 D D 6. MPU SPI

15 ADV739/ADV739/ADV7392/ADV7393 Parameter V AA to AGND V DD to DGND PV DD to PGND V DD _IO to GND_IO V AA to V DD V DD to PV DD V DD_IO to V DD AGND to DGND AGND to PGND AGND to GND_IO DGND to PGND DGND to GND_IO PGND to GND_IO Digital Input Voltage to GND_IO Analog Outputs to AGND Storage Temperature Range (t S ) Junction Temperature (t J ) Lead Temperature (Soldering, sec) Rating.3 V to +3.9 V.3 V to +2.3 V.3 V to +2.3 V.3 V to +3.9 V.3 V to +2.2 V.3 V to +.3 V.3 V to +2.2 V.3 V to +.3 V.3 V to +.3 V.3 V to +.3 V.3 V to +.3 V.3 V to +.3 V.3 V to +.3 V.3 V to V DD_IO +.3 V.3 V to V AA 6 to θ JA. Package Type 2 θ JA θ JC Unit 32-Lead LFCP /W 4-Lead LFCSP /W JEDEC4 2 LFCSPPCB ADV739x Sn RoHS 2555IR JEDEC STD-2 ADV739x SnPb Sn SnPb ESD ESD ESD ESD

16 ADV739/ADV739/ADV7392/ADV GND_IO 3 P 3 P 29 DGND 28 V DD 27 HSYNC 26 VSYNC 25 SFL/MISO 4 GND_IO 39 P3 38 P2 37 P 36 DGND 35 V DD 34 P 33 HSYNC 32 VSYNC 3 SFL/MISO V DD_IO P2 2 P3 3 P4 V 4 5 DD DGND 6 P5 7 P6 8 PIN INDICATOR ADV739/ ADV739 TOP VIEW (Not to Scale) 24 R SET 23 COMP 22 DAC 2 DAC 2 2 DAC 3 9 V AA 8 AGND 7 PV DD V DD_IO P4 2 P5 3 P6 4 P7 5 VDD 6 DGND 7 P8 8 P9 9 P PIN INDICATOR ADV7392/ ADV7393 TOP VIEW (Not to Scale) 3 R SET 29 COMP 28 DAC 27 DAC 2 26 DAC 3 25 V AA 24 AGND 23 PV DD 22 EXT_LF 2 PGND P7 ALSB/SPI_SS SDA/SCLK SCL/MOSI CLKIN RESET PGND EXT_LF ADV739/ADV ADV7392/ADV7393 P ALSB/SPI_SS 2 SDA/SCLK 3 SCL/MOSI 4 P2 5 P4 P P5 9 CLKIN 2 RESET ADV739/9 ADV7392/93 9 to 7, 4 to 2, P7 to P I 8 P7 P P LSB 3, 3 ADV739/ADV to 5, to 8, 5 P5 to P I 6 P5 P P LSB to 2, 39 to 37, 34 ADV7392/ADV CLKIN I HD 74.25MHz ED 27MHz54MHz HSYNC VSYNC I/O I/O SD 27MHz SD ED HD SD ED HD 25 3 SFL/MISO I/O SFL SPIMISO SFL DDS 24 3 R SET I DAC DAC2 DAC3 37.5Ω R SET AGND5Ω 3Ω R SET AGND4.2kΩ COMP O COMP V AA 2.2nF 22, 2, 2 28, 27, 26 DAC, DAC 2, O DACDAC DAC SCL/MOSI I I 2 C SPI 3 SDA/SCLK I/O I 2 C SPI 2 ALSB/SPI_SS I ALSB MPU I 2 C LSB 2 SPI SPI_SS

17 ADV739/ADV739/ADV7392/ADV7393 ADV739/9 ADV7392/ RESET I ADV739x 9 25 V AA P 3.3V 5, 28 6, 35 V DD P.8V V DD.8V V DD_IO P 3.3V 7 23 PV DD P PLL.8V PV DD.8V 6 22 EXT_LF I PLL 5 2 PGND G PLL 8 24 AGND G 6, 29 7, 36 DGND G 32 4 GND_IO G ED 525p/625p 2 LSB ADV739 LSBI 2 C xd4lsb I 2 C xd6 ADV739 LSB I 2 C x54 I 2 C x56

18 ADV739/ADV739/ADV7392/ADV7393 EDPr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4. Y RESPONSE IN ED 8 OVERSAMPLING MODE.5 2 GAIN (db) GAIN (db) FREQUENCY (MHz) FREQUENCY (MHz) ED 8 PrPb 22. ED 8 Y EDPr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4 HD Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4 2 2 GAIN (db) 3 4 GAIN (db) FREQUENCY (MHz) FREQUENCY (MHz) ED 8 PrPb SSAF 23. HD 4 PrPb SSAF 4:2:2 Y RESPONSE IN ED 8 OVERSAMPLING MODE HD Pr/Pb RESPONSE. 4:4:4 INPUT MODE GAIN (db) GAIN (db) FREQUENCY (MHz) FREQUENCY (MHz) ED 8 Y 24. HD 4 PrPb SSAF 4:4:4

19 ADV739/ADV739/ADV7392/ADV7393 Y RESPONSE IN HD 4 OVERSAMPLING MODE GAIN (db) (db) MAGNITUDE FREQUENCY (MHz) FREQUENCY (MHz) HD 4 Y 28. SD PAL 3..5 Y PASS BAND IN HD 4x OVERSAMPLING MODE GAIN (db) MAGNITUDE (db) FREQUENCY (MHz) 26. HD 4 Y FREQUENCY (MHz) SD NTSC MAGNITUDE (db) MAGNITUDE (db) FREQUENCY (MHz) FREQUENCY (MHz) SD NTSC 3. SD PAL

20 ADV739/ADV739/ADV7392/ADV7393 Y RESPONSE IN SD OVERSAMPLING MODE 5 4 GAIN (db) (db) MAGNITUDE FREQUENCY (MHz) FREQUENCY (MHz) SD 6 Y 34. SD SSAF MAGNITUDE (db) (db) MAGNITUDE FREQUENCY (MHz) FREQUENCY (MHz) SD SSAF 2MHz 35. SD SSAF 4 2 (db) MAGNITUDE (db) MAGNITUDE FREQUENCY (MHz) FREQUENCY (MHz) SD SSAF 36. SD CIF

21 ADV739/ADV739/ADV7392/ADV7393 (db) 2 (db) 2 MAGNITUDE 3 4 MAGNITUDE FREQUENCY (MHz) FREQUENCY (MHz) SD QCIF 4. SD.3MHz (db) 2 (db) 2 MAGNITUDE 3 4 MAGNITUDE FREQUENCY (MHz) FREQUENCY (MHz) SD3.MHz 4. SD.MHz (db) 2 (db) 2 MAGNITUDE 3 4 MAGNITUDE FREQUENCY (MHz) FREQUENCY (MHz) SD2.MHz 42. SD.65MHz

22 ADV739/ADV739/ADV7392/ADV7393 (db) 2 (db) 2 MAGNITUDE 3 4 MAGNITUDE FREQUENCY (MHz) FREQUENCY (MHz) SDCIF 44. SDQCIF

23 ADV739/ADV739/ADV7392/ADV7393 MPU ADV739x 2 I 2 C 4 SPI MPU I 2 C SPI SPI I 2 C ADV739x 2 I 2 C SDASCL 2 ADV739x ADV739x LSB A ADV739x ALSB/ SPI_SS A X ADDRESS CONTROL SET UP BY ALSB/SPI_SS ADV739/ADV7392 xd4 xd6 A X ADDRESS CONTROL SET UP BY ALSB/SPI_SS READ/WRITE CONTROL WRITE READ READ/WRITE CONTROL WRITE READ ADV739/ADV7393 x54 x56 SCL SDA 8 7R/W MSB LSB 9 SDA SCL R/W LSB LSB ADV739x SDA 87 R/W ADV739x 2 SCL ADV739x 9 SDA ADV739x 47 48

24 ADV739/ADV739/ADV7392/ADV7393 SDA SCL S P START ADDR R/W ACK SUBADDRESS ACK DATA ACK STOP 47. I 2 C WRITE SEQUENCE S SLAVE ADDR A(S) SUBADDR A(S) DATA A(S) DATA A(S) P LSB = LSB = READ SEQUENCE S SLAVE ADDR A(S) SUBADDR A(S) S SLAVE ADDR A(S) DATA A(M) DATA A(M) P S = START BIT P = STOP BIT A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER 48. A(S) = NO-ACKNOWLEDGE BY SLAVE A (M) = NO-ACKNOWLEDGE BY MASTER I 2 C SPI ADV739x 4 SPI MOSISCLK 2 MISO SPI ADV739x SPI SPI SPI ADV739x ALSB/SPI_SS3 ALSB/SPI_SS3 SPI SPI ADV739x ADV739x ALSB/SPI_SS ALSB/SPI_SS SCLKxD4 MOSI ADV739x MOSI 2 MOSI MSBSCLK 8 MOSI MSB ADV739x SCLK ADV739x ADV739x ALSB/SPI_SS MOSI ALSB/SPI_SS ALSB/SPI_SS ALSB/SPI_SS SCLK xd5 MOSI MSBADV739x 8MISO MSBADV739x SCLK ADV739x ALSB/SPI_SS

25 ADV739/ADV739/ADV7392/ADV7393 ADV739x MPU MPU 3. x 3 27 SR7 SR 8 MPU SR7 to Bit Number Register Reset SR Register Bit Description Setting Value x Power Sleep Mode. With this control enabled, the current Sleep x2 Mode consumption is reduced to µa level. All DACs and mode off. Register the internal PLL circuit are disabled. Registers can be Sleep read from and written to in sleep mode. mode on. PLL and Oversampling Control. This control allows PLL on. the internal PLL circuit to be powered down and the PLL off. oversampling to be switched off. DAC 3: Power on/off. DAC 3 off. DAC 3 on. DAC 2: Power on/off. DAC 2 off. DAC 2 on. DAC : Power on/off. DAC off. DAC on. Reserved.

26 ADV739/ADV739/ADV7392/ADV x x9 SR7 to Bit Number Reset SR Register Bit Description Register Setting Value x Mode Reserved. x Select DDR Clock Edge Alignment. Chroma clocked in on rising clock Register Note: Only used for ED and edge and luma clocked in on falling HD DDR modes. clock edge. Reserved. Reserved. Luma clocked in on rising clock edge and chroma clocked in on falling clock edge. Reserved. Input Mode. SD input. Note: See Reg. x3, Bits[7:3] ED/HD-SDR input 2 for ED/HD format selection. ED/HD-DDR input. Reserved. Reserved. Reserved. Reserved. ED (at 54 MHz) input. Reserved. x2 Mode Reserved. Zero must be written to these bits. x2 Register Test Pattern Black Bar. 3 Disabled. Enabled. Manual RGB Matrix Adjust. Disable manual RGB matrix adjust. Enable manual RGB matrix adjust. Sync on RGB. No sync. Sync on all RGB outputs. RGB/YPrPb Output Select. RGB component outputs. YPrPb component outputs. SD Sync Output Enable. No sync output. Output SD syncs on HSYNC and VSYNC pins. ED/HD Sync Output Enable. No sync output. Output ED/HD syncs on HSYNC and VSYNC pins. x3 ED/HD CSC x x LSBs for GY. x3 Matrix x4 ED/HD CSC x x LSBs for RV. xf Matrix x x LSBs for BU. x x LSBs for GV. x x LSBs for GU. x5 ED/HD CSC x x x x x x x x Bits[9:2] for GY. x4e Matrix 2 x6 ED/HD CSC x x x x x x x x Bits[9:2] for GU. xe Matrix 3 x7 ED/HD CSC x x x x x x x x Bits[9:2] for GV. x24 Matrix 4 x8 ED/HD CSC x x x x x x x x Bits[9:2] for BU. x92 Matrix 5 x9 ED/HD CSC x x x x x x x x Bits[9:2] for RV. x7c Matrix 6 ED(525p/625p) 2 ADV7392/ADV7393(4 ) 3 x3 2 (ED/HD) x84 6(SD)

27 ADV739/ADV739/ADV7392/ADV xb x7 SR7 to Bit Number Reset SR Register Bit Description Register Setting Value xb DAC, DAC 2, Positive Gain to DAC Output % x DAC 3 Output Voltage. +.8% Level +.36% % +7.5% Negative Gain to DAC Output 7.5% Voltage % 7.364%.8% xd DAC Power Mode DAC Low Power Mode. DAC low power disabled x DAC low power enabled DAC 2 Low Power Mode. DAC 2 low power disabled DAC 2 low power enabled DAC 3 Low Power Mode. DAC 3 low power disabled DAC 3 low power enabled SD/ED Oversample Rate Select. SD = 6x, ED = 8x SD = 8x, ED = 4x Reserved. x Cable Detection DAC Cable Detect. Cable detected on DAC x Read Only. DAC unconnected DAC 2 Cable Detect. Cable detected on DAC 2 Read Only. DAC 2 unconnected Reserved. Unconnected DAC auto DAC auto power-down power-down. disable DAC auto power-down enable Reserved. x3 Pixel Port P[7:] Readback x x x x x x x x Read only xxx Readback A (ADV739/ADV739). P[5:8] Readback (ADV7392/ADV7393). x4 Pixel Port P[7:] Readback x x x x x x x x Read only xxx Readback B (ADV7392/ADV7393). x6 Control Port Reserved. x x x Read only xxx Readback VSYNC Readback. x HSYNC Readback. x SFL/MISO Readback. Reserved. x x x7 Software Reset Reserved. x x Software Reset. Writing a resets the device; this is a self-clearing bit Reserved. X [6:4] ()

28 ADV739/ADV739/ADV7392/ADV x3 SR7 to Bit Number Reset SR Register Bit Description Register Setting Value x3 ED/HD ED/HD Output EIA-77.2 output ED x Mode Standard. EIA-77.3 output HD Register EIA-77. output Output levels for full input range Reserved ED/HD Input External HSYNC, Synchronization VSYNC and field Format. inputs Embedded EAV/SAV codes ED/HD Input Mode. SMPTE 293M, ITU-BT Hz Nonstandard timing mode BTA-4, ITU-BT Hz ITU-BT Hz ITU-BT Hz SMPTE 296M-, SMPTE 274M-2 6 Hz/59.94 Hz SMPTE 296M-3 5 Hz SMPTE 296M-4, SMPTE 274M-5 3 Hz/29.97 Hz SMPTE 296M-6 25 Hz SMPTE 296M-7, SMPTE 296M-8 24 Hz/23.98 Hz SMPTE 24M 6 Hz/59.94 Hz Reserved Reserved SMPTE 274M-4, SMPTE 274M-5 3 Hz/29.97 Hz SMPTE 274M-6 25 Hz SMPTE 274M-7, SMPTE 274M-8 3 Hz/29.97 Hz SMPTE 274M-9 25 Hz SMPTE 274M-, SMPTE 274M- 24 Hz/23.98 Hz ITU-R BT Hz to Reserved x34 6 HSYNCVSYNC HSYNC

29 ADV739/ADV739/ADV7392/ADV x3 x33 SR7 to Bit Number Reset SR Register Bit Description Register Setting Value x3 ED/HD Mode ED/HD Pixel Data Valid. Pixel data valid off x Register 2 Pixel data valid on HD Oversample Rate Select. 4x 2x ED/HD Test Pattern Enable. HD test pattern off HD test pattern on ED/HD Test Pattern Hatch Hatch/Field. Field/frame ED/HD Vertical Blanking Disabled Interval (VBI) Open. Enabled ED/HD Undershoot Limiter. Disabled IRE 6 IRE.5 IRE ED/HD Sharpness Filter. Disabled Enabled x32 ED/HD Mode ED/HD Y Delay with Respect clock cycles x Register 3 to Falling Edge of HSYNC. clock cycle 2 clock cycles 3 clock cycles 4 clock cycles ED/HD Color Delay with clock cycles Respect to Falling Edge of clock cycle HSYNC. 2 clock cycles 3 clock cycles 4 clock cycles ED/HD CGMS Enable. Disabled Enabled ED/HD CGMS CRC Enable. Disabled x33 Enabled ED/HD Mode ED/HD Cr/Cb Sequence. Cb after falling edge of HSYNC x68 Register 4 Cr after falling edge of HSYNC ADV7392/ADV7393(4 ) Reserved. must be written to this bit ED/HD Input Format. 8-bit input -bit input Sinc Compensation Filter on Disabled DAC, DAC 2, DAC 3. Enabled Reserved. must be written to this bit ED/HD Chroma SSAF Filter. Disabled Enabled Reserved. must be written to this bit ED/HD Double Buffering. Disable Enabled

30 ADV739/ADV739/ADV7392/ADV x34 x38 SR7 to Bit Number Reset SR Register Bit Description Register Setting Value x34 ED/HD Mode ED/HD Timing Reset. Internal ED/HD timing x48 Register 5 counters enabled Resets the internal ED/HD timing counters ED/HD HSYNC Control. HSYNC output control (refer to Table 5) ED/HD VSYNC Control. VSYNC output control (refer to Table 5) Reserved. ED Macrovision Enable. 2 ED Macrovision disabled ED Macrovision enabled Reserved. must be written to this bit ED/HD VSYNC Input/Field = Field input Input. = VSYNC input ED/HD Horizontal/Vertical Update field/line counter Counter Mode. 3 Field/line counter free running x35 ED/HD Mode Reserved. x Register 6 Reserved. ED/HD Sync on PrPb. Disabled Enabled ED/HD Color DAC Swap. DAC 2 = Pb, DAC 3 = Pr DAC 2 = Pr, DAC 3 = Pb ED/HD Gamma Correction Gamma Correction Curve A Curve Select. Gamma Correction Curve B ED/HD Gamma Disabled Correction Enable. Enabled ED/HD Adaptive Filter Mode. Mode A Mode B ED/HD Adaptive Filter Enable. Disabled Enabled x36 ED/HD Y Level 4 ED/HD Test Pattern Y Level. x x x x x x x x Y level value xa x37 ED/HD Cr Level 4 ED/HD Test Pattern Cr Level. x x x x x x x x Cr level value x8 x38 ED/HD Cb Level 4 ED/HD Test Pattern Cb Level. x x x x x x x x Cb level value x8 x2 7 ED/HD 2 ADV739 ADV ED/HD(x3 2 )

31 ADV739/ADV739/ADV7392/ADV x39 x43 SR7 to Bit Number Reset SR Register Bit Description Register Setting Value x39 ED/HD Mode Reserved. x Register 7 ED/HD EIA/CEA-86B Disabled Synchronization Compliance. Enabled Reserved. x4 ED/HD Sharpness ED/HD Sharpness Filter Gain Gain A = x Filter Gain Value A. Gain A = + Gain A = +7 Gain A = 8 Gain A = ED/HD Sharpness Filter Gain Gain B = Value B. Gain B = + Gain B = +7 Gain B = 8 Gain B = x4 ED/HD CGMS ED/HD CGMS Data Bits. C9 C8 C7 C6 CGMS C9 to C6 x Data x42 ED/HD CGMS ED/HD CGMS Data Bits. C5 C4 C3 C2 C C C9 C8 CGMS C5 to C8 x Data x43 ED/HD CGMS ED/HD CGMS Data Bits. C7 C6 C5 C4 C3 C2 C C CGMS C7 to C x Data 2 2. x44 x57 SR7 to Bit Number Register Reset SR Register Bit Description Setting Value x44 ED/HD Gamma A ED/HD Gamma Curve A (Point 24). x x x x x x x x A x x45 ED/HD Gamma A ED/HD Gamma Curve A (Point 32). x x x x x x x x A x x46 ED/HD Gamma A2 ED/HD Gamma Curve A (Point 48). x x x x x x x x A2 x x47 ED/HD Gamma A3 ED/HD Gamma Curve A (Point 64). x x x x x x x x A3 x x48 ED/HD Gamma A4 ED/HD Gamma Curve A (Point 8). x x x x x x x x A4 x x49 ED/HD Gamma A5 ED/HD Gamma Curve A (Point 96). x x x x x x x x A5 x x4a ED/HD Gamma A6 ED/HD Gamma Curve A (Point 28). x x x x x x x x A6 x x4b ED/HD Gamma A7 ED/HD Gamma Curve A (Point 6). x x x x x x x x A7 x x4c ED/HD Gamma A8 ED/HD Gamma Curve A (Point 92). x x x x x x x x A8 x x4d ED/HD Gamma A9 ED/HD Gamma Curve A (Point 224). x x x x x x x x A9 x x4e ED/HD Gamma B ED/HD Gamma Curve B (Point 24). x x x x x x x x B x x4f ED/HD Gamma B ED/HD Gamma Curve B (Point 32). x x x x x x x x B x x5 ED/HD Gamma B2 ED/HD Gamma Curve B (Point 48). x x x x x x x x B2 x x5 ED/HD Gamma B3 ED/HD Gamma Curve B (Point 64). x x x x x x x x B3 x x52 ED/HD Gamma B4 ED/HD Gamma Curve B (Point 8). x x x x x x x x B4 x x53 ED/HD Gamma B5 ED/HD Gamma Curve B (Point 96). x x x x x x x x B5 x x54 ED/HD Gamma B6 ED/HD Gamma Curve B (Point 28). x x x x x x x x B6 x x55 ED/HD Gamma B7 ED/HD Gamma Curve B (Point 6). x x x x x x x x B7 x x56 ED/HD Gamma B8 ED/HD Gamma Curve B (Point 92). x x x x x x x x B8 x x57 ED/HD Gamma B9 ED/HD Gamma Curve B (Point 224). x x x x x x x x B9 x

32 ADV739/ADV739/ADV7392/ADV x58 x5d SR7 to Bit Number Register Reset SR Register Bit Description Setting Value x58 ED/HD Adaptive Filter Gain ED/HD Adaptive Filter Gain, Gain A = x Value A. Gain A = + Gain A = +7 Gain A = 8 Gain A = ED/HD Adaptive Filter Gain, Gain B = Value B. Gain B = + Gain B = +7 Gain B = 8 Gain B = x59 ED/HD Adaptive Filter Gain 2 ED/HD Adaptive Filter Gain 2, Gain A = x Value A. Gain A = + Gain A = +7 Gain A = 8 Gain A = ED/HD Adaptive Filter Gain 2, Gain B = Value B. Gain B = + Gain B = +7 Gain B = 8 Gain B = x5a ED/HD Adaptive Filter Gain 3 ED/HD Adaptive Filter Gain 3, Gain A = x Value A. Gain A = + Gain A = +7 Gain A = 8 Gain A = ED/HD Adaptive Filter Gain 3, Gain B = Value B. Gain B = + Gain B = +7 Gain B = 8 Gain B = x5b ED/HD Adaptive Filter ED/HD Adaptive Filter x x x x x x x x Threshold A x Threshold A Threshold A. x5c ED/HD Adaptive Filter ED/HD Adaptive Filter x x x x x x x x Threshold B x Threshold B Threshold B. x5d ED/HD Adaptive Filter ED/HD Adaptive Filter x x x x x x x x Threshold C x Threshold C Threshold C.

33 ADV739/ADV739/ADV7392/ADV x5e x6e SR7 to Bit Number Register Reset SR Register Bit Description Setting Value x5e ED/HD CGMS Type B ED/HD CGMS Disabled x Register Type B Enable. Enabled ED/HD CGMS Disabled Type B CRC Enable. Enabled ED/HD CGMS H5 H4 H3 H2 H H H5 to H Type B Header Bits. x5f ED/HD CGMS Type B ED/HD CGMS P7 P6 P5 P4 P3 P2 P P P7 to P x Register Type B Data Bits. x6 ED/HD CGMS Type B ED/HD CGMS P5 P4 P3 P2 P P P9 P8 P5 to P8 x Register 2 Type B Data Bits. x6 ED/HD CGMS Type B ED/HD CGMS P23 P22 P2 P2 P9 P8 P7 P6 P23 to P6 x Register 3 Type B Data Bits. x62 ED/HD CGMS Type B ED/HD CGMS P3 P3 P29 P28 P27 P26 P25 P24 P3 to P24 x Register 4 Type B Data Bits. x63 ED/HD CGMS Type B ED/HD CGMS P39 P38 P37 P36 P35 P34 P33 P32 P39 to P32 x Register 5 Type B Data Bits. x64 ED/HD CGMS Type B ED/HD CGMS P47 P46 P45 P44 P43 P42 P4 P4 P47 to P4 x Register 6 Type B Data Bits. x65 ED/HD CGMS Type B ED/HD CGMS P55 P54 P53 P52 P5 P5 P49 P48 P55 to P48 x Register 7 Type B Data Bits. x66 ED/HD CGMS Type B ED/HD CGMS P63 P62 P6 P6 P59 P58 P57 P56 P63 to P56 x Register 8 Type B Data Bits. x67 ED/HD CGMS Type B ED/HD CGMS P7 P7 P69 P68 P67 P66 P65 P64 P7 to P64 x Register 9 Type B Data Bits. x68 ED/HD CGMS Type B ED/HD CGMS P79 P78 P77 P76 P75 P74 P73 P72 P79 to P72 x Register Type B Data Bits. x69 ED/HD CGMS Type B ED/HD CGMS P87 P86 P85 P84 P83 P82 P8 P8 P87 to P8 x Register Type B Data Bits. x6a ED/HD CGMS Type B ED/HD CGMS P95 P94 P93 P92 P9 P9 P89 P88 P95 to P88 x Register 2 Type B Data Bits. x6b ED/HD CGMS Type B ED/HD CGMS P3 P2 P P P99 P98 P97 P96 P3 to P96 x Register 3 Type B Data Bits. x6c ED/HD CGMS Type B ED/HD CGMS P P P9 P8 P7 P6 P5 P4 P to P4 x Register 4 Type B Data Bits. x6d ED/HD CGMS Type B ED/HD CGMS P9 P8 P7 P6 P5 P4 P3 P2 P9 to P2 x Register 5 Type B Data Bits. x6e ED/HD CGMS Type B ED/HD CGMS P27 P26 P25 P24 P23 P22 P2 P2 P27 to P2 x Register 6 Type B Data Bits.

34 ADV739/ADV739/ADV7392/ADV x8 x83 SR7 to Bit Number Reset SR Register Bit Description Register Setting Value x8 SD Mode SD Standard. NTSC x Register PAL B, PAL D, PAL G, PAL H, PAL I PAL M PAL N SD Luma Filter. LPF NTSC LPF PAL Notch NTSC Notch PAL Luma SSAF Luma CIF Luma QCIF Reserved SD Chroma Filter..3 MHz.65 MHz. MHz 2. MHz Reserved Chroma CIF Chroma QCIF 3. MHz x82 SD Mode SD PrPb SSAF Filter. Disabled xb Register 2 Enabled SD DAC Output. Refer to Table 32 in the Output Configuration section Reserved. SD Pedestal. Disabled Enabled SD Square Pixel Mode. Disabled Enabled SD VCR FF/RW Sync. Disabled Enabled SD Pixel Data Valid. Disabled Enabled SD Active Video Edge Disabled Control. Enabled x83 SD Mode SD Pedestal YPrPb No pedestal on YPrPb x4 Register 3 Output. 7.5 IRE pedestal on YPrPb SD Output Levels Y. Y = 7 mv/3 mv Y = 74 mv/286 mv SD Output Levels PrPb. 7 mv p-p (PAL), mv p-p (NTSC) 7 mv p-p mv p-p 648 mv p-p SD Vertical Blanking Disabled Interval (VBI) Open. Enabled SD Closed Captioning Closed captioning disabled Field Control. Closed captioning on odd field only Closed captioning on even field only Closed captioning on both fields Reserved. Reserved

35 ADV739/ADV739/ADV7392/ADV x84 x87 SR7 to Bit Number Reset SR Register Bit Description Register Setting Value x84 SD Mode SD VSYNC -3H. Disabled x Register 4 VSYNC = 2.5 lines (PAL), VSYNC = 3 lines (NTSC) SD SFL/SCR/TR Mode Select. Disabled Subcarrier reset mode enabled Timing reset mode enabled SFL mode enabled SD Active Video Length. 72 pixels 7 (NTSC), 72 (PAL) SD Chroma. Chroma enabled Chroma disabled SD Burst. Enabled Disabled SD Color Bars. Disabled Enabled SD Luma/Chroma Swap. DAC 2 = luma, DAC 3 = chroma DAC 2 = chroma, DAC 3 = luma x86 SD Mode NTSC Color Subcarrier Adjust 5.7 µs x2 Register 5 (Delay from the falling edge of 5.3 µs output HSYNC pulse to start of color burst) µs (must be set for Macrovision compliance) Reserved Reserved. SD EIA/CEA-86B Disabled Synchronization Compliance. Enabled Reserved. SD Horizontal/Vertical Update field/line counter Counter Mode. Field/line counter free running SD RGB Color Swap. 2 Normal Color reversal enabled x87 SD Mode SD PrPb Scale. Disabled x Register 6 Enabled SD Y Scale. Disabled Enabled SD Hue Adjust. Disabled Enabled SD Brightness. Disabled Enabled SD Luma SSAF Gain. Disabled Enabled SD Input Standard Auto Disabled Detection. Enabled Reserved. must be written to this bit SD RGB Input Enable. 2 SD YCrCb input SD RGB input 2 ADV7392/ADV7393(4 )

36 ADV739/ADV739/ADV7392/ADV x88 x89 SR7 to Bit Number Reset SR Register Bit Description Register Setting Value x88 SD Mode Reserved. x Register 7 SD Noninterlaced Mode. Disabled Enabled SD Double Buffering. Disabled Enabled SD Input Format. 8-bit input 6-bit input -bit input Reserved SD Digital Noise Reduction. Disabled Enabled SD Gamma Correction Enable. Disabled Enabled SD Gamma Correction Curve Gamma Correction Curve A Select. Gamma Correction Curve B x89 SD Mode SD Undershoot Limiter. Disabled x Register 8 IRE 6 IRE.5 IRE Reserved. must be written to this bit SD Black Burst Output on Disabled DAC Luma. Enabled ADV7392/ADV7393(4 ) SD Chroma Delay. Disabled 4 clock cycles 8 clock cycles Reserved Reserved. must be written to these bits

37 ADV739/ADV739/ADV7392/ADV x8a x98 SR7 to Bit Number Reset SR Register Bit Description Register Setting Value x8a SD Timing SD Slave/Master Mode. Slave mode x8 Register Master mode SD Timing Mode. Mode Mode Mode 2 Mode 3 Reserved. SD Luma Delay. No delay 2 clock cycles 4 clock cycles 6 clock cycles SD Minimum Luma Value. 4 IRE 7.5 IRE SD Timing Reset. x A low-high-low transition resets the internal SD timing counters x8b SD Timing Register SD HSYNC Width. ta = clock cycle x Note: Applicable in t a = 4 clock cycles master modes only, t a = 6 clock cycles that is, Subaddress t a = 28 clock cycles x8a, Bit =. SD HSYNC to VSYNC Delay. tb = clock cycles t b = 4 clock cycles t b = 8 clock cycles t b = 8 clock cycles SD HSYNC to VSYNC Rising x tc = t b Edge Delay (Mode Only). x t c = t b + 32 µs VSYNC Width (Mode 2 Only). clock cycle 4 clock cycles 6 clock cycles 28 clock cycles HSYNC to Pixel Data Adjust. clock cycles clock cycle 2 clock cycles 3 clock cycles x8c SD F SC Register Subcarrier Frequency Bits[7:] x x x x x x x x Subcarrier Frequency Bits[7:] xf x8d SD F SC Register Subcarrier Frequency Bits[5:8] x x x x x x x x Subcarrier Frequency Bits[5:8] x7c x8e SD F SC Register 2 Subcarrier Frequency Bits[23:6] x x x x x x x x Subcarrier Frequency Bits[23:6] xf x8f SD F SC Register 3 Subcarrier Frequency Bits[3:24] x x x x x x x x Subcarrier Frequency Bits[3:24] x2 x9 SD F SC Phase Subcarrier Phase Bits[9:2] x x x x x x x x Subcarrier Phase Bits[9:2] x x9 SD Closed Captioning Extended Data on Even Fields. x x x x x x x x Extended Data Bits[7:] x x92 SD Closed Captioning Extended Data on Even Fields. x x x x x x x x Extended Data Bits[5:8]. x x93 SD Closed Captioning Data on Odd Fields. x x x x x x x x Data Bits[7:] x x94 SD Closed Captioning Data on Odd Fields. x x x x x x x x Data Bits[5:8] x x95 SD Pedestal Register Pedestal on Odd Fields Setting any of these bits to x x96 SD Pedestal Register Pedestal on Odd Fields disables pedestal on the line number indicated by the bit settings x x97 SD Pedestal Register 2 Pedestal on Even Fields x x98 SD Pedestal Register 3 Pedestal on Even Fields x NTSC

38 ADV739/ADV739/ADV7392/ADV x99 xa5 SR7 to Bit Number Reset SR Register Bit Description Register Setting Value x99 SD CGMS/WSS SD CGMS Data. x x x x CGMS Data Bits[C9:C6] x SD CGMS CRC. Disabled Enabled SD CGMS on Odd Fields. Disabled Enabled SD CGMS on Even Fields. Disabled Enabled SD WSS. Disabled Enabled x9a SD CGMS/WSS SD CGMS/WSS Data. x x x x x x CGMS Data Bits[C3:C8] or x WSS Data Bits[W3:W8] SD CGMS Data. x x CGMS Data Bits[C5:C4] x9b SD CGMS/WSS 2 SD CGMS/WSS Data. x x x x x x x x CGMS Data Bits[C7:C] or x WSS Data Bits[W7:W] x9c SD Scale LSB LSBs for SD Y Scale Value. x x SD Y Scale Bits[:] x Register LSBs for SD Cb Scale Value. x x SD Cb Scale Bits[:] LSBs for SD Cr Scale Value. x x SD Cr Scale Bits[:] LSBs for SD F SC Phase. x x Subcarrier Phase Bits[:] x9d SD Y Scale Register SD Y Scale Value. x x x x x x x x SD Y Scale Bits[7:2] x x9e SD Cb Scale Register SD Cb Scale Value. x x x x x x x x SD Cb Scale Bits[7:2] x x9f SD Cr Scale Register SD Cr Scale Value. x x x x x x x x SD Cr Scale Bits[7:2] x xa SD Hue Register SD Hue Adjust Value. x x x x x x x x SD Hue Adjust Bits[7:] x xa SD Brightness/WSS SD Brightness Value. x x x x x x x SD Brightness Bits[6:] x SD Blank WSS Data. Disabled Enabled xa2 SD Luma SSAF SD Luma SSAF Gain/ 4 db x Attenuation. Note: Only applicable if Subaddress db x87, Bit 4 =. +4 db Reserved. xa3 SD DNR Coring Gain Border. No gain x Note: In DNR mode, the +/6 [ /8] values in brackets apply. +2/6 [ 2/8] +3/6 [ 3/8] +4/6 [ 4/8] +5/6 [ 5/8] +6/6 [ 6/8] +7/6 [ 7/8] +8/6 [ ] Coring Gain Data. No gain Note: In DNR mode, the +/6 [ /8] values in brackets apply. +2/6 [ 2/8] +3/6 [ 3/8] +4/6 [ 4/8] +5/6 [ 5/8] +6/6 [ 6/8] +7/6 [ 7/8] +8/6 [ ]

39 ADV739/ADV739/ADV7392/ADV7393 SR7 to Bit Number Reset SR Register Bit Description Register Setting Value xa4 SD DNR DNR Threshold. x Border Area. 2 pixels 4 pixels Block Size. 8 pixels 6 pixels xa5 SD DNR 2 DNR Input Select. Filter A x Filter B Filter C Filter D DNR Mode. DNR mode DNR sharpness mode DNR Block Offset. pixel offset pixel offset 4 pixel offset 5 pixel offset 28. xa6 xbb SR7 to Bit Number Register Reset SR Register Bit Description Setting Value xa6 SD Gamma A SD Gamma Curve A (Point 24). x x x x x x x x A x xa7 SD Gamma A SD Gamma Curve A (Point 32). x x x x x x x x A x xa8 SD Gamma A2 SD Gamma Curve A (Point 48). x x x x x x x x A2 x xa9 SD Gamma A3 SD Gamma Curve A (Point 64). x x x x x x x x A3 x xaa SD Gamma A4 SD Gamma Curve A (Point 8). x x x x x x x x A4 x xab SD Gamma A5 SD Gamma Curve A (Point 96). x x x x x x x x A5 x xac SD Gamma A6 SD Gamma Curve A (Point 28). x x x x x x x x A6 x xad SD Gamma A7 SD Gamma Curve A (Point 6). x x x x x x x x A7 x xae SD Gamma A8 SD Gamma Curve A (Point 92). x x x x x x x x A8 x xaf SD Gamma A9 SD Gamma Curve A (Point 224). x x x x x x x x A9 x xb SD Gamma B SD Gamma Curve B (Point 24). x x x x x x x x B x xb SD Gamma B SD Gamma Curve B (Point 32). x x x x x x x x B x xb2 SD Gamma B2 SD Gamma Curve B (Point 48). x X x x x x x x B2 x xb3 SD Gamma B3 SD Gamma Curve B (Point 64). x x x x x x x x B3 x xb4 SD Gamma B4 SD Gamma Curve B (Point 8). x x x x x x x x B4 x xb5 SD Gamma B5 SD Gamma Curve B (Point 96). x x x x x x x x B5 x xb6 SD Gamma B6 SD Gamma Curve B (Point 28). x x x x x x x x B6 x xb7 SD Gamma B7 SD Gamma Curve B (Point 6). x x x x x x x x B7 x xb8 SD Gamma B8 SD Gamma Curve B (Point 92). x x x x x x x x B8 x xb9 SD Gamma B9 SD Gamma Curve B (Point 224). x x x x x x x x B9 x xba SD Brightness Detect SD Brightness Value. x x x x x x x x Read only xxx xbb Field Count Register Field Count. x x x Read only xx Reserved. Reserved Revision Code. Read only

40 ADV739/ADV739/ADV7392/ADV xf xf SR7 to Bit Number Reset SR Register Bit Description Register Setting Value xe Macrovision MV Control Bits. x x x x x x x x x xe Macrovision MV Control Bits. x x x x x x x x x xe2 Macrovision MV Control Bits. x x x x x x x x x xe3 Macrovision MV Control Bits. x x x x x x x x x xe4 Macrovision MV Control Bits. x x x x x x x x x xe5 Macrovision MV Control Bits. x x x x x x x x x xe6 Macrovision MV Control Bits. x x x x x x x x x xe7 Macrovision MV Control Bits. x x x x x x x x x xe8 Macrovision MV Control Bits. x x x x x x x x x xe9 Macrovision MV Control Bits. x x x x x x x x x xea Macrovision MV Control Bits. x x x x x x x x x xeb Macrovision MV Control Bits. x x x x x x x x x xec Macrovision MV Control Bits. x x x x x x x x x xed Macrovision MV Control Bits. x x x x x x x x x xee Macrovision MV Control Bits. x x x x x x x x x xef Macrovision MV Control Bits. x x x x x x x x x xf Macrovision MV Control Bits. x x x x x x x x x xf Macrovision MV Control Bit. x Bits[7:] must be x Macrovision ADV739 ADV7392

41 ADV739/ADV739/ADV7392/ADV7393 ADV739/ADV739 ADV739/ADV739 x [6:4] ADV739/ADV739 SD 3 CrCb CLKINP7 P P LSB YCLKIN x [2:] ADV739/ADV739 CLKIN Input Mode P7 P6 P5 P4 P2 P2 P P SD YCrCb ED/HD-DDR YCrCb ED (at 54 MHz) YCrCb x [6:4] SD YCrCb 827MHz 4:2:2 27MHz CLKIN HSYNC VSYNC EAV/SAV ITU-R BT.6/656 P7 P P LSB MPEG2 DECODER 2 27MHz ADV739/ ADV739 VSYNC, HSYNC CLKIN P[7:] CLKIN P[7:] 3FF XY Cb Y Cr Y NOTES. SUBADDRESS x [2:] SHOULD BE SET TO IN THIS CASE ED/HD-DDR EAV/SAV A 3FF XY Y Cb Y Cr NOTES. SUBADDRESS x [2:] SHOULD BE SET TO IN THIS CASE. ED/HD-DDR EAV/SAV B MPEG2 DECODER YCrCb INTERLACED TO PROGRESSIVE YCrCb 8 ADV739/ ADV739 CLKIN P[7:] YCrCb 8 P[7:] 49. SD VSYNC, HSYNC ED/HD-DDR x [6:4] EDHD YCrCb 8DDR 4:2:2 CLKIN HSYNC VSYNC EAV/SAV 84:2:2 ED/HD YCrCb DDR 8DDR 4:2:2 YCrCb Y CLKINP7 P P LSB 54 MHz x [6:4] ED YCrCb 854MHz 4:2:2 54MHz CLKIN EAV/SAV P7 P P LSB CLKIN P[7:] 53. 3FF XY Cb Y Cr Y ED 54MHz EAV/SAV

42 ADV739/ADV739/ADV7392/ADV7393 ADV7392/ADV7393 ADV7392/ADV7393 x [6:4] ADV7392/ADV7393 SD 3 x [6:4] SD YCrCb 8//6 4:2:2 SD RGB 6 4:4:4 27MHz CLKIN HSYNC VSYNC 8 EAV/SAV 84:2:2 YCrCb x87 7 x88 [4:3] 84:2:2 YCrCb P5 P8 P8 LSB ITU-R BT.6/656 4:2:2 YCrCb x87 7 x88 [4:3] 4:2:2 YCrCb P5 P6 P6 LSB ITU-R BT.6/656 64:2:2 YCrCb x87 7 x88 [4:3] 64:2:2 YCrCb Y P5 P8 P8 LSB CrCb P7 P P LSB /2 3.5 MHz 3 64:4:4 RGB x :4:4 RGB P4 PP P5 P5 P P P5 P LSB /2 3.5 MHz 4 MPEG2 DECODER YCrCb MHz 8/ ADV7392/ ADV7393 VSYNC, HSYNC CLKIN P[5:8]/P[5:6] SD ADV7392/ADV7393 Input Mode P5 P4 P3 P2 P P P9 P8 P7 P6 P5 P4 P3 P2 P P SD 2 SD RGB Input Enable (x87[7]) = 8-Bit YCrCb -Bit YCrCb 6-Bit 3 Y CrCb SD RGB Input Enable (x87[7]) = 6-Bit 3 B G R ED/HD-SDR (6-Bit) Y CrCb ED/HD-DDR 4 ED/HD Input Format (x33[2]) = 8-Bit YCrCb ED/HD Input Format (x33[2]) = -Bit YCrCb ED (At 54 MHz) ED/HD Input Format (x33[2]) = 8-Bit YCrCb ED/HD Input Format (x33[2]) = -Bit YCrCb x [6:4] 2 SD x88 [4:3] 3 EAV/SAV 4 ED 525p625p

43 ADV739/ADV739/ADV7392/ADV7393 x [6:4] EDHD YCrCb 8/DDR 6 SDR4:2:2 MPEG2 DECODER YCrCb ADV7392/ ADV7393 CLKIN CLKIN HSYNC VSYNC EAV/SAV INTERLACED TO PROGRESSIVE CrCb Y 8 8 P[7:] P[5:8] 6 4:2:2 YCrCb SDR 64:2:2 YCrCb Y P5 P8 P8 LSB CrCbP7 P P LSB 8/4:2:2 YCrCb DDR 8/DDR 4:2:2 YCrCb Y CLKIN P5 P8/P6 P8/P6 LSB CrCb CLKINP5 P8/P6 P8/P6 LSB x33 2 Y CLKIN x [2:] CLKIN P[5:8]/ P]5:6] 3FF XY Cb Y Cr Y 57. MPEG2 DECODER YCrCb INTERLACED TO PROGRESSIVE 58. ED/HD-SDR YCrCb ED/HD-DDR 54MHz x [6:4] ED YCrCb 8/54MHz 4:2:2 2 8/ 2 VSYNC HSYNC ADV7392/ ADV7393 CLKIN P[5:8]/P[5:6] VSYNC HSYNC NOTES. SUBADDRESS x [2:] SHOULD BE SET TO IN THIS CASE. 2. -BIT MODE IS ENABLED USING SUBADDRESS x33, BIT ED/HD-DDR EAV/SAV A MHz CLKIN EAV/SAV P5 P8/P6 P8/P6 LSB CLKIN P[5:8]/ P[5:P6] 3FF XY Y Cb Y Cr x33 2 CLKIN NOTES. SUBADDRESS x [2:] SHOULD BE SET TO IN THIS CASE. 2. -BIT MODE IS ENABLED USING SUBADDRESS x33, BIT ED/HD-DDR EAV/SAV B P[5:8]/P[5:6] 59. 3FF XY Cb Y Cr Y NOTES. -BIT MODE IS ENABLED USING SUBADDRESS x33, BIT 2. ED 54MHz EAV/SAV MPEG2 DECODER YCrCb 54MHz ADV7392/ ADV7393 CLKIN INTERLACED TO PROGRESSIVE 6. YCrCb 8/ 2 P[5:8]/P[5:6] VSYNC, HSYNC ED 54MHz

44 ADV739/ADV739/ADV7392/ADV7393 ADV739x SD RGB/YPrPb Output Select SD DAC Output SD Luma/Chroma Swap (x2, Bit 5) (x82, Bit ) (x84, Bit 7) DAC DAC 2 DAC 3 G B R Y Pb Pr CVBS Luma Chroma CVBS Chroma Luma SD RGB x ED/HD RGB/YPrPb Output Select (x2, Bit 5) ED/HD Color DAC Swap (x35, Bit 3) DAC DAC 2 DAC 3 G B R G R B Y Pb Pr Y Pr Pb 34. ED 54MHz RGB/YPrPb Output Select (x2, Bit 5) ED/HD Color DAC Swap (x35, Bit 3) DAC DAC 2 DAC 3 G B R G R B Y Pb Pr Y Pr Pb

45 ADV739/ADV739/ADV7392/ADV7393 ADV739x SD ED HD PLL PLL PLL x 35 ADV739x ED/HD x3 [7:3] ED/HDED/HD x3 [7:3]ED/HD ADV739x ED/HD x3 [7:3] CLKIN HSYNC VSYNC6 36 ED/HDEAV/SAV ED/HDMacrovision ADV739/ADV7392 PLL x ANALOG OUTPUT b 6. c a = TRI-LEVEL SYNCHRONIZATION PULSE LEVEL. b = BLANKING LEVEL/ACTIVE VIDEO LEVEL. c = SYNCHRONIZATION PULSE LEVEL. a b BLANKING LEVEL ACTIVE VIDEO ED/HD b Input Mode PLL and Oversampling SD/ED Oversample Rate HD Oversample Rate Oversampling Mode (x, Bits[6:4]) Control (x, Bit ) Select (xd, Bit 3) Select (x3, Bit ) and Rate SD x x SD (2x) SD x SD (8x) SD x SD (6x) / ED x x ED (x) / ED x ED (4x) / ED x ED (8x) / HD x x HD (x) / HD x HD (2x) / HD x HD (4x) ED (at 54 MHz) x x ED (@ 54 MHz) (x) ED (at 54 MHz) x ED (@ 54 MHz) (4x) ED (at 54 MHz) x ED (@ 54 MHz) (8x) 36. ED/HD Output Level Transition HSYNC VSYNC b c or 2 c a a b c b a 3 b c6 2 VSYNC VSYNC3 VSYNC

46 ADV739/ADV739/ADV7392/ADV7393 ED/HD x34 ED/HD ED/HD x34 ED/HD SD x84 [2:] ADV739x SFL/MISOSD 4 x84 [2:] SFL TR x84 [2:] SFL/MISO SD SCR x84 [2:] SFL/MISO 7 PAL3 NTSC xbb SFL x84 [2:] ADV739x SFL ADV739x ADV739x SFL ADV DISPLAY START OF FIELD 4 OR 8 F SC PHASE = FIELD 4 OR NO TIMING RESET APPLIED DISPLAY START OF FIELD F SC PHASE = FIELD TIMING RESET PULSE TIMING RESET APPLIED 62. SDx84 [2:] DISPLAY START OF FIELD 4 OR 8 F SC PHASE = FIELD 4 OR NO F SC RESET APPLIED DISPLAY START OF FIELD 4 OR 8 F SC PHASE = FIELD F SC RESET PULSE F SC RESET APPLIED 63. SD x84 [2:]

47 ADV739/ADV739/ADV7392/ADV7393 ADV739x CLKIN COMPOSITE VIDEO LCC ADV743 VIDEO DECODER SFL P9 TO P SFL/MISO PIXEL PORT 5 DAC DAC 2 DAC 3 H/L TRANSITION COUNT START 28 4 BITS RESERVED 4 BITS SUBCARRIER LOW PHASE 3 2 F SC PLL INCREMENT 2 SEQUENCE BIT 3 RESET BIT 4 RESERVED RTC 64. TIME SLOT 4 9 VALID SAMPLE FOR EXAMPLE, VCR OR CABLE. 2F SC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV73xx F INVALID SAMPLE 8/LINE LOCKED CLOCK SD x84 [2:] BITS RESERVED SC DDS REGISTER IS F SC PLL INCREMENTS BITS 2: PLUS BITS :9 OF SUBCARRIER FREQUENCY REGISTERS. 3SEQUENCE BIT PAL: = LINE NORMAL, = LINE INVERTED NTSC: = NO CHANGE 4RESET ADV739x DDS. 5REFER TO THE ADV739/ADV739 AND ADV7392/ADV7393 INPUT CONFIGURATION TABLES FOR PIXEL DATA PIN ASSIGNMENTS SD VCR FF/RW x82 5 DVD VCR FF/RW VCR FF/RW x82 5 VSYNC VSYNC x3 4 x83 4 ADV739x SD ED HD VBI CGMS WSS VITS VBI ED/HD x3 4 SD x83 4 VBI VBI SDVBI EAV/SAV VBI CGMS VBI CGMS SD x8c x8f NTSC d _2F7CF SD F SC : xf SD F SC : x7c SD F SC 2: xf SD F SC 3: x2 VBI SMPTE 293M 525p 3 42ITU-R BT p 6 43 VBI NTSC 2 PAL 7 22

48 ADV739/ADV739/ADV7392/ADV7393 F SC 4 FSC4 3 ADV739x F SC 37 NTSC PAL B/D/G/H/I 37. F SC Subaddress Description NTSC PAL B/D/G/H/I x8c F SC xf xcb x8d F SC x7c x8a x8e F SC 2 xf x9 x8f F SC 3 x2 x2a SD x88 ADV739x SD NTSCPAL 2 24p/59.94Hz 288p/5Hz ADV739x SD x88 27MHz CLKIN EAV/SAV HSYNCVSYNC NTSC PAL SD 24p/59.94Hz ADV739x NTSC x88 288p/5Hz ADV739x PAL x88 SD x82 4 ADV739x x82 4 NTSC MHz PAL 29.5MHz ANALOG VIDEO INPUT PIXELS NTSC/PAL M SYSTEM (525 LINES/6Hz) PAL SYSTEM (625 LINES/5Hz) Y C r Y 65. EAV CODE F F END OF ACTIVE VIDEO LINE X Y 8 8 F F A A A F F B B B EAV/SAV 8 SAV CODE 8 F X C F Y b Y C r Y C b 4 CLOCK ANCILLARY DATA (HANC) 4 CLOCK 272 CLOCK 28 CLOCK 4 CLOCK 4 CLOCK 344 CLOCK 536 CLOCK START OF ACTIVE VIDEO LINE Y C r Y C b HSYNC FIELD PIXEL DATA Cb Y Cr Y 66. PAL = 38 CLOCK CYCLES NTSC = 236 CLOCK CYCLES

49 ADV739/ADV739/ADV7392/ADV ADV739x EXTENDED (SSAF) PrPb FILTER MODE 38. Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma SSAF SD Luma CIF SD Luma QCIF SD Chroma.65 MHz SD Chroma. MHz SD Chroma.3 MHz SD Chroma 2. MHz SD Chroma 3. MHz SD Chroma CIF SD Chroma QCIF SD PrPb SSAF ED/HD Sinc Compensation Filter ED/HD Chroma SSAF Subaddress x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x82 x33 x33 SD x8 [7:2] x82 Y22 SSAF CIF QCIF PrPb 6CIFQCIF SD SSAF x dB 3 xa ADV739x 38 PrPb SSAF 2.7MHz 3.8MHz 4dB 67 x82 GAIN (db) PrPb SSAF 39 CVBS FREQUENCY (MHz) Filter Pass-Band Ripple (db) 3 db Bandwidth (MHz) 2 Luma LPF NTSC Luma LPF PAL. 4.8 Luma Notch NTSC.9 2.3/4.9/6.6 Luma Notch PAL. 3./5.6/6.4 Luma SSAF Luma CIF Luma QCIF Monotonic.5 Chroma.65 MHz Monotonic.65 Chroma. MHz Monotonic Chroma.3 MHz Chroma 2. MHz Chroma 3. MHz Monotonic 3.2 Chroma CIF Monotonic.65 Chroma QCIF Monotonic.5 db db Hz fc Hz Hz f Hz f2 Hz fc ff2 3dB 2 3dB 3dB

50 ADV739/ADV739/ADV7392/ADV7393 ED/HD Sinc x33 3 ADV739x ED/HD DAC DAC2 DAC3 sinc x GAIN (db) EIA77.2/EIA77.3 x3 [:] 4. EIA77.2/EIA77.3 ED/HD Sample Color Y Value Cr Value Cb Value White 235 (xeb) 28 (x8) 28 (x8) Black 6 (x) 28 (x8) 28 (x8) Red 8 (x5) 24 (xf) 9 (x5a) Green 45 (x9) 34 (x22) 54 (x36) Blue 4 (x29) (x6e) 24 (xf) Yellow 2 (xd2) 46 (x92) 6 (x) Cyan 7 (xaa) 6 (x) 66 (xa6) Magenta 6 (x6a) 222 (xde) 22 (xca) FREQUENCY (MHz) ED/HD Sinc x3 x9 CSC x [6:4] ADV7392/ADV7393 RGB YPrPb SD RGB YPrPb ED/HD GAIN (db) FREQUENCY (MHz) ED/HD Sinc SD YPrPb/RGB Out RGB In/YCrCb In Input Output (Reg. x2, Bit 5) (Reg. x87, Bit 7) YCrCb YPrPb YCrCb RGB RGB 2 YPrPb RGB 2 RGB CVBS/YC CSC 2 ADV7392/ADV ED/HD x36 x38 x36 x ED/HD x3 2 Y Cr Cb ITU-R BT ED/HD Input Output YPrPb/RGB Out (Reg. x2, Bit 5) YCrCb YPrPb YCrCb RGB ED/HD CSC ED/HD CSC ED HD x2 3 CSC EDHD 42

51 ADV739/ADV739/ADV7392/ADV7393 RGBED/HD CSC R GY Y RV Pr G GY Y GU PbGV Pr B GY Y BU Pb YPrPb Y GY Y Pr RV Pr Pb BU Pb GY x5 [7:]x3 [:] GU x6 [7:]x4 [7:6] GV x7 [7:]x4 [5:4] BU x8 [7:]x4 [3:2] RV x9 [7:]x4 [:] CSC Subaddress x3 x4 x5 x6 x7 x8 x9 ED/HD CSC Default x3 xf x4e xe x24 x92 x7c ED/HD CSC x3 x9 HD 8i72p SMPTE 274M SMPTE 296M R Y.575Pr G Y.468Pr.87Pb B Y.855Pb SMPTE 293M R Y.42Pr G Y.74Pr.344Pb B Y.773Pb CSC ED/HD CSC YCrCb RGB ED/HD CSC. ED/HD CSC x RGB x Sync on PrPb x Sync on RGB x2 4 GY BU RV SD x9c x9f SD Y SD Cb SD Cr 3 SD Y Cb Cr CbCr. 2.Y..5 Y Cb Cr 52.3 Y Cb Cr Y Cb Cr666 Y Cb Cr b x9c SD LSB x2a x9d SD Y xa6 x9e SD Cb xa6 x9f SD Cr xa6 CVBS YC YPrPb RGB 35 ED/HD CSC GY x3b GU x3b GV x93 BU x248 RV xf ED/HD CSC EDGY GU GV BU RV

52 ADV739/ADV739/ADV7392/ADV7393 SD xa SD xa SD x87 2 xa ADV739x x8 xff x NTSC xff x PAL HCR d 28 HCR d 4 x x d x d x69 SD xba ADV739x SD xba SD xa [6:] SD WSS xa Y x87 3 NTSC IRE 22.5IRENTSC 7 PAL 7.5IRE 5IRE SD NTSC 2IRE xa x28 SD IRE x28 PAL 7IRE xa x72 SD IRE x b b 2 b x Setup Level Setup Level Setup Brightness (NTSC) with (NTSC) Without Level Control Pedestal Pedestal (PAL) Value 22.5 IRE 5 IRE 5 IRE xe 5 IRE 7.5 IRE 7.5 IRE xf 7.5 IRE IRE IRE x IRE 7.5 IRE 7.5 IRE x7 x3f x44 SD x87 5 ADV739x SD x87 5 ADV739x NTSC PAL B/D/G/H/I ADV739x SDx8 [:] IRE NTSC WITHOUT PEDESTAL +7.5 IRE IRE 7.5 IRE NO SETUP VALUE ADDED POSITIVE SETUP VALUE ADDED NEGATIVE SETUP VALUE ADDED

53 ADV739/ADV739/ADV7392/ADV7393 x33 7 ED/HD x88 2 SD x33 7 ED/HDA BED/HD CGMS ED/HD x88 2 SDSDA B SD Y SD Cr SD Cb SD SD SD Macrovision [5:] xe [5:] DAC xb DAC 7 DAC DAC3xB GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS xb 7mV 3mV CASE B 7mV NEGATIVE GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS xb 7 B DAC 7.5% DAC4.33mA DAC 4.8 ma 7.5%4.658 ma 7.5% x DAC 45 DAC 4.33 ma 45. DAC DAC Current Subaddress xb (ma) % Gain Note (x4) % (x3f) % (x3e) % (x2) % (x) % (x) 4.33.% Reset value, nominal (xff) % (xfe) % (xc2) % (xc) % (xc) % 3mV 7. DAC 7 A x44 x57 ED/HD xa6 xb9 SD CRT Signal OUT = (Signal IN ) γ γ SDED/HD 2 8 A B ED/HD x35 5 ED/HD A x44 x4d ED/HD B x4e x57

54 ADV739/ADV739/ADV7392/ADV7393 SD x88 6 SD A xa6 xaf SD B xb xb9 2 A B ED/HD x35 4 SD x x DESIRED = (x INPUT ) γ x DESIRED x INPUT γ γ n 6 γ n γ n n n γ γ.5 γ n γ 24 8/ γ 32 6/ γ 48 32/ γ 64 48/ γ 8 64/ γ 96 8/ γ 28 2/ γ 6 44/ γ 92 76/ γ / GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT 3 GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR VARIOUS GAMMA VALUES G AMM A CORRECTED AMPLITUD E SIGNAL INPUT SIGNAL OUTPUT G AMM A CORRECTED AMPLITUD E SIGNAL INPUT LOCATION LOCATION

55 ADV739/ADV739/ADV7392/ADV7393 ED/HD x4 x58 x5d ADV739x 3 2 ED/HD 74Y ED/HD x3 7 ED/HD x x4 ED/HD ED/HD ED/HD ED/HD A ED/HD B ED/HD C ED/HD ED/HD2 ED/HD3 3 ED/HD AB C x5b x5c x5d ED/HD 2 3 x58 x59 x5a ED/HD x4 2 ED/HD x35 6 ED/HD A B LPF ED/HD 2 3 ED/HD B A ED/HD B A B ED/HD 2 3 ED/HD A B ED/HD ED/HDED/HD x3 7 x35 7 INPUT SIGNAL: STEP MAGNITUDE SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK.5 FREQUENCY (MHz) FILTER A RESPONSE (Gain Ka) 74. MAGNITUDE FREQUENCY (MHz) FILTER B RESPONSE (Gain Kb) ED/HD Scale) (Linear RESPONSE MAGNITUDE FREQUENCY (MHz) FREQUENCY RESPONSE IN SHARPNESS FILTER MODE WITH Ka = 3 AND Kb =

56 ADV739/ADV739/ADV7392/ADV7393 a d R2 b e R4 R c f R2 CH 5mV M 4.µs CH CH 5mV M 4.µs CH REF A 5mV 4.µs ms ALL FIELDS REF A 5mV 4.µs ms ALL FIELDS 75. ED/HDED/HD ED/HD ED/HD Y ED/HD Subaddress Register Setting Reference x xfc x x x2 x2 x3 x x3 x8 x4 x a x4 x8 b x4 x4 c x4 x4 d x4 x8 e x4 x22 f Y 47. Subaddress x x x2 x3 x3 x35 x4 x58 x59 x5a x5b x5c x5d 77 Register Setting xfc x38 x2 x x8 x8 x xac x9a x88 x28 x3f x64

57 ADV739/ADV739/ADV7392/ADV7393 DNR DNR 76. ED/HD 77. ED/HD A B x MPEG 8 8 MPEG2 6 6 MPEG DNR 2 4 DNR YCrCb DNR 3 8DNR DNR MODE NOISE SIGNAL PATH INPUT FILTER BLOCK DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN CORING GAIN DATA CORING GAIN BORDER Y DATA INPUT FILTER OUTPUT < THRESHOLD? MAIN SIGNAL PATH FILTER OUTPUT > THRESHOLD + SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL DNR OUT DNR SHARPNESS MODE DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN 78. ED/HD B SD xa3 xa5 DNR Y DNR DNR DNR DNR Y DATA INPUT NOISE SIGNAL PATH INPUT FILTER BLOCK 79. CORING GAIN DATA CORING GAIN BORDER FILTER OUTPUT > THRESHOLD? FILTER OUTPUT < THRESHOLD MAIN SIGNAL PATH + + SD DNR ADD SIGNAL ABOVE THRESHOLD RANGE FROM ORIGINAL SIGNAL DNR OUT

58 ADV739/ADV739/ADV7392/ADV7393 xa3 [3:] 4 DNR /8 DNR DNR.5 /6 DNR xa3 [7:4] 4 MPEG DNR /8 DNR DNR.5 /6 DNR DNR27 TO DNR24 = x 8. SD DNR DNRxA4 [5:] 663 xa MHz PIXELS (NTSC) APPLY DATA CORING GAIN 8. APPLY BORDER CORING GAIN OXXXXXXOOXXXXXXO OXXXXXXOOXXXXXXO OXXXXXXOOXXXXXXO 8 8 PIXEL BLOCK 2-PIXEL BORDER SD DNR OFFSET CAUSED BY VARIATIONS IN INPUT TIMING DATA 8 8 PIXEL BLOCK xa MHz 2 DNR xa5 [2:] 3 Y DNR 82 MAGNITUDE FILTER D FILTER C 82. FILTER B FILTER A FREQUENCY (MHz) SD DNR DNR xa5 4 DNR DNR DNR DNR DNR DNR DNR SSAF xa5 [7:4]

59 ADV739/ADV739/ADV7392/ADV7393 SD x82 7 ADV739x x IRE LUMA CHANNEL WITH ACTIVE VIDEO EDGE DISABLED IRE 87.5 IRE 3 /8 /2 7/8 3 7/8 /2 /8 LUMA CHANNEL WITH ACTIVE VIDEO EDGE ENABLED IRE IRE 2.5 IRE IRE VOLTS IRE:FLT F2 L x VOLTS IRE:FLT F2 L35 x

60 ADV739/ADV739/ADV7392/ADV7393 ADV739x EAV/SAV HSYNC VSYNC 48 HSYNCVSYNC Signal Pin Condition SD HSYNC In HSYNC SD Slave Timing Mode, Mode 2, or Mode 3 Selected (Subaddress x8a[2:]). SD VSYNC /FIELD In VSYNC SD Slave Timing Mode, Mode 2, or Mode 3 Selected (Subaddress x8a[2:]). ED/HD HSYNC In HSYNC ED/HD Timing Synchronization Inputs Enabled (Subaddress x3, Bit 2 = ). ED/HD VSYNC /FIELD In VSYNC ED/HD Timing Synchronization Inputs Enabled (Subaddress x3, Bit 2 = ). SDED/HDx2[7:6] 49. Signal Pin Condition SD HSYNC Out HSYNC SD Timing Synchronization Outputs enabled (Subaddress x2, Bit 6 = ). SD VSYNC /FIELD Out VSYNC SD Timing Synchronization Outputs enabled (Subaddress x2, Bit 6 = ). ED/HD HSYNC Out HSYNC ED/HD Timing Synchronization Outputs enabled (Subaddress x2, Bit 7 = ). 2 ED/HD VSYNC /FIELD Out VSYNC ED/HD Timing Synchronization Outputs enabled (Subaddress x2, Bit 7 = ). 2 ED/HDx2 7 2 ED/HDEAV/SAV x HSYNC ED/HD HSYNC ED/HD Sync SD Sync ED/HD Input Sync Control Output Enable Output Enable Format (x3, Bit 2) (x34, Bit ) (x2, Bit 7) (x2, Bit 6) Signal on HSYNC Pin Duration x x Tristate. x x Pipelined SD HSYNC. x Pipelined ED/HD HSYNC. x Pipelined ED/HD HSYNC based on AV Code H bit. x x Pipelined ED/HD HSYNC based on horizontal counter. HSYNC ED/HD HSYNC HSYNC As per HSYNC timing. Same as line blanking interval. Same as embedded HSYNC. 5. VSYNC ED/HD Input ED/HD VSYNC ED/HD Sync SD Sync Sync Format Control Output Enable Output Enable (x3, Bit 2) (x34, Bit 2) (x2, Bit 7) (x2, Bit 6) Video Standard Signal on VSYNC Pin Duration x x x Tristate. x x Interlaced Pipelined SD VSYNC /Field. x x Pipelined ED/HD VSYNC or field signal. As per VSYNC or Field signal timing. x All HD interlaced Pipelined Field signal Field. standards based on AV Code F bit. x All ED/HD progressive Pipelined VSYNC based Vertical blanking standards on AV Code V bit. interval. x x All ED/HD standards Pipelined ED/HD VSYNC Aligned with except 525p based on vertical counter. serration lines. x x 525p Pipelined ED/HD VSYNC Vertical blanking based on vertical counter. interval. VSYNC ED/HD VSYNC EAV/SAVVSYNC

61 ADV739/ADV739/ADV7392/ADV7393 xd [2:] ADV739x DAC R SET 5Ω R L 37.5Ω R SET 4.2kΩ R L 3Ω xd [2:] DAC DAC DAC 4% x [:] ADV739x DAC DAC2 R SET 5Ω R L 37.5Ω R SET 4.2kΩ R L 3Ω DAC x ON SD ED HD CVBS YC YPrPb RGB CVBS/YCDAC DAC2 CVBS YC YPrPbRGBDAC ADV739x DACDAC2 x DAC DAC x 4 x 4 DAC DAC DAC2 DAC DAC CVBS/YC DACDAC DAC2DAC2 DAC3 DACDAC2 DAC DAC x3 x4 x6 ADV739x I 2 C/SPI MPU P[5:]P[7:] HSYNC VSYNC SFL/MISO MPU x3 x4 x6 CLKIN SD x [6:4] x7 RESET MPU I 2 C ADV739x I 2 C/SPI MPU x7 SPI I 2 C I 2 C RESET RESET RC RC RESET YPrPbRGB DAC 3 DAC DAC2

62 ADV739/ADV739/ADV7392/ADV7393 PC DAC ADV739x 3 DAC 37.5Ω R L 34.7mA DAC 3 DAC 3Ω R L 4.33mA ADV739x R SET R SET AGND DAC DAC2 DAC3 R SET 5Ω R L 37.5Ω R SET 4.2kΩ R L 3Ω R SET ADV739xCOMPCOMP V AA 2.2nF R SET 4.2kΩ R L 3Ω DAC AD86 ADV739x DAC LPF 6 SD 8 ED 4 HD ADA443-ADA ADV739x Input Mode (x, Bits[6:4]) Oversampling Output Rate (MHz) SD Off 27 (2x) On 8 (8x) On 26 (6x) ED Off 27 (x) On 8 (4x) On 26 (8x) HD Off (x) On 48.5 (2x) On 297 (4x) 53. Cutoff Attenuation Frequency 5 Application Oversampling (MHz) (MHz) SD 2x > x > x > ED x > x > x > HD x > x > x > DAC OUTPUT 86. 6Ω µh 22pF 6Ω Ω 56Ω SD 6 75Ω BNC OUTPUT DAC OUTPUT 6Ω 4.7µH 6.8pF 6.8pF 6Ω Ω BNC OUTPUT Ω 56Ω ED DAC OUTPUT 3Ω nH 75Ω 3 33pF 33pF 75Ω 4 BNC OUTPUT 5Ω 5Ω

63 ADV739/ADV739/ADV7392/ADV7393 GAIN (db) GAIN (db) GAIN (db) HD 4 CIRCUIT FREQUENCY RESPONSE 24n 3 2n MAGNITUDE (db) 6 2 8n 9 3 PHASE (Degrees) 5n 2 4 2n 5 5 9n GROUP DELAY (Seconds) 8 6 6n 2 7 3n 24 8 M M M G FREQUENCY (Hz) SD 6 CIRCUIT FREQUENCY RESPONSE 48 8n 4 MAGNITUDE (db) 6n n 3 24 PHASE GROUP DELAY (Seconds) 2n (Degrees) 4 6 n 5 8 8n 6 6n 7 8 4n 8 6 2n 9 24 M M M G FREQUENCY (Hz) ED 8 CIRCUIT FREQUENCY RESPONSE MAGNITUDE (db) GROUP DELAY (Seconds) PHASE (Degrees) (Degrees) PHASE PC PCB ADV739x ADV739x 4 PC COMPR SET PC ADV739x ADV739x PCB ADV739x ADC DAC PC ADV739x PCB DAC ADV739x DAC R SET 4.2kΩ R L 3Ω V AA V DD V DD_IO PV DD V AA PV DD FREQUENCY (MHz) 2 HD

64 ADV739/ADV739/ADV7392/ADV7393 nf.µf V AA PV DD V DD_IO V DD ADV739x nf.µf V AA µf ADV739x V AA PV DD ADV739x V DD_IO DAC DAC DAC PC ADV739x DACDAC DAC

65 ADV739/ADV739/ADV7392/ADV7393 V DD_IO PV DD V AA V DD FERRITE BEAD 33µF µf GND_IO GND_IO FERRITE BEAD 33µF µf PGND PGND FERRITE BEAD 33µF µf AGND AGND FERRITE BEAD 33µF µf DGND DGND.µF GND_IO.µF PGND.µF AGND.µF DGND.µF GND_IO.µF PGND.µF AGND.µF DGND µf AGND V DD_IO POWER SUPPLY DECOUPLING PV DD POWER SUPPLY DECOUPLING V AA POWER SUPPLY DECOUPLING V DD POWER SUPPLY DECOUPLING FOR EACHPOWER PIN NOTES. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED TO THE COMP, R SET AND DAC OUTPUT PINS SHOULD BE LOCATED CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS THE ADV739x. 2. WHEN OPERATING IN I2C MODE, THE I2C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB/SPI_SS PIN: ALSB/SPI_SS =, I 2 C DEVICE ADDRESS = xd4 OR x54 ALSB/SPI_SS =, I 2 C DEVICE ADDRESS = xd6 OR x56 3. THE RESISTOR CONNECTED TO THE R SET PIN SHOULD HAVE A % TOLERANCE. 4. THE RECOMMENDED MODE OF OPERATION FOR THE DACs IS FULL- DRIVE (R SET = 5Ω, R L = 37.5Ω). V AA PIXEL PORT INPUTS CONTROL INPUTS/OUTPUTS P P P2 P3 P4 P5 P6 P7 P8 P9 P P P2 P3 P4 P5 V D D HSYNC VSYNC V D D V A A ADV7392/ ADV7393 ONLY P V D D V DD_I O ADV739x COMP R SET DAC DAC 2 DAC 3 75Ω 5Ω AGND 2.2nF AGND DACs TO 3 FULL DRIVE OPTION (RECOMMENDED) OPTIONAL LPF OPTIONAL LPF 75Ω AGND OPTIONAL LPF 75Ω AGND DAC DAC 2 DAC 3 R SET DAC DACs TO 3 LOW DRIVE OPTION 4.2kΩ AGND ADA44-3 LPF 75Ω DAC CLOCK INPUT CLKIN 3Ω AGND MPU PORT INPUTS/OUTPUTS SDA/SCLK SCL/MOSI SFL/MISO ALSB/SPI_SS DAC 2 ADA44-3 LPF 75Ω DAC 2 EXTERNAL LOOP FILTER PV DD 5nF 2nF 7Ω RESET EXT_LF DAC 3 3Ω AGND ADA44-3 LPF 75Ω DAC 3 LOOP FILTER COMPONENTS SHOULD BE LOCATED CLOSE TO THE EXT_LF PIN AND ON THE SAME SIDE OF THE PCB AS THE ADV739x. AGND PGND DGND DGND GND_IO 3Ω AGND AGND PGND DGND DGND GND_IO 92. ADV739x

66 ADV739/ADV739/ADV7392/ADV7393 SD CGMS x99 x9b ADV739x EIAJ CPR-24ARIB TR-B5 CGMS CGMS 2283 CGMS x99 [6:5] SD CGMSADV739x NTSC CGMS 2 CGMS 93 ED CGMS x4 x43 x5e x6e 525p ADV739x EIAJ CPR p CGMS ED CGMS x p CGMS 4 525p CGMS x4 x42 x43 ADV739x CEA-85-A 525p CGMS B ED CGMSB x5e 525p CGMSB 4 525p CGMSB x5e x6e 625p ADV739x IEC p CGMS ED CGMS x p CGMS p CGMS x42x43 HD CGMS x4 x43 x5e x6e ADV739x EIAJ CPR-24-2 HD 72p 8i CGMS HD CGMS x32 6 8i CGMS HD CGMS x4 x42 x43 ADV739x CEA-85-A HD 72p 8i CGMSB HD CGMSB x5e 72p CGMS 23 HD CGMSB x5e 8i CGMS 8 58 HD CGMSB x5e x6e CGMS CRC SD CGMS CRC x99 4 ED/HD CGMS CRC x32 7 6CRC CGMS6 C9 C4 ADV739x CGMS 4 C3 C 42 CGMS CRC x 6 x SD CGMS CRCED/HD CGMS CRC 2 C9 C CGMS CRC ED/HD CGMSB CRC x5e 6 CRC CGMSB6 P22 P27 ADV739x CGMS B 28 H H5P P CGMS B CRC x 6 x ED/HD CGMSB CRC 34 H H5P P27 CGMSB CRC HD CGMS x p CGMS 24

67 ADV739/ADV739/ADV7392/ADV IRE +7 IRE REF CRC SEQUENCE C C C2 C3 C4 C5 C6 C7 C8 C9 C C C2 C3 C4 C5 C6 C7 C8 C9 IRE 4 IRE.2µs 2.235µs ±2ns 93. CGMS 49.µs ±.5µs mV 7% ± % REF CRC SEQUENCE BIT BIT BIT 2 C C C2 C3 C4 C5 C6 C7 C8 C9 C C C2 C3 C4 C5 C6 C7 C8 C9 mv 3mV 5.8µs ±.5µs 6T 2.2µs ±.22µs 22T T = /(f H 33) = 963ns f H = HORIZONTAL SCAN FREQUENCY T±3ns p CGMS PEAK WHITE R = RUN-IN S = START CODE 5mV ± 25mV R S C LSB C C2 C3 C4 C5 C6 C7 C8 C9 C C C2 C3 MSB SYNC LEVEL 3.7µs 5.5µs ±.25µs p CGMS mV 7% ± % REF CRC SEQUENCE BIT BIT BIT 2 C C C2 C3 C4 C5 C6 C7 C8 C9 C C C2 C3 C4 C5 C6 C7 C8 C9 mv 3mV 4T 3.28µs ±9ns T±3ns 7.2µs ± 6ns 22T T = /(f H 65/58) = 78.93ns f H = HORIZONTAL SCAN FREQUENCY H p CGMS

68 ADV739/ADV739/ADV7392/ADV mV 7% ± % REF CRC SEQUENCE BIT BIT BIT 2 C C C2 C3 C4 C5 C6 C7 C8 C9 C C C2 C3 C4 C5 C6 C7 C8 C9 mv 3mV 4T 4.5µs ± 6ns T±3ns 22.84µs ±2ns 22T T = /(f H 22/77) =.38µs f H = HORIZONTAL SCAN FREQUENCY H i CGMS +7mV 7% ± % START BIT BIT 2 CRC SEQUENCE BIT 34 H H H2 H3 H4 H5 P P P2 P3 P4... P22 P23 P24 P25 P26 P27 mv 3mV NOTES. PLEASE REFER TO THE CEA-85-A SPECIFICATION FOR TIMING INFORMATION p CGMSB mV 7% ±% START BIT BIT 2 CRC SEQUENCE BIT 34 H H H2 H3 H4 H5 P P P2 P3 P4... P22 P23 P24 P25 P26 P27 mv 3mV NOTES. PLEASE REFER TO THE CEA-85-A SPECIFICATION FOR TIMING INFORMATION p8i CGMSB

69 2 SD ADV739/ADV739/ADV7392/ADV7393 x99 x9a x9b ADV739x ETSI WSS WSS 23 WSS ADV739x PALWSS 4 54 WSS 23 HSYNC 42.5µs 23 WSS x WSS xa WSS Bit Number Bit Description Setting Aspect Ratio, Format, 4:3, full format, N/A Position 4:9, letterbox, center 4:9, letterbox, top 6:9, letterbox, center 6:9, letterbox, top >6:9, letterbox, center 4:9, full format, center 6:, N/A, N/A Mode Camera mode Film mode Color Encoding Normal PAL Motion Adaptive ColorPlus Helper Signals Not present Present Reserved Teletext Subtitles No Yes Open Subtitles No Subtitles in active image area Subtitles out of active image area Reserved Surround Sound No Yes Copyright No copyright asserted or unknown Copyright asserted Copy Protection Copying not restricted Copying restricted 5mV RUN-IN SEQUENCE START CODE W W W2 W3 W4 W5 W6 W7 W8 W9 W W W2 W3 ACTIVE VIDEO.µs 38.4µs 42.5µs WSS

70 ADV739/ADV739/ADV7392/ADV SD x9 x94 ADV739x V x83 [6:5] SD x93 x94 ADV739x 284 SD x9 x FCC Code of Federal Regulations CFR Title 47 Section 5.9EIA-68 ADV739x VSYNC 2 2 TV Hello World 2 ADV739x ±.25µs 2.9µs 7 CYCLES OF.535MHz CLOCK RUN-IN TWO 7-BIT + PARITY ASCII CHARACTERS (DATA) 5 IRE S T A R T D TO D6 P A R I T Y D TO D6 P A R I T Y 4 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = F SC = MHz AMPLITUDE = 4 IRE.3µs µs BYTE µs BYTE SD NTSC

71 4 ADV739/ADV739/ADV7392/ADV7393 SD ADV739x SD 55 SD NTSC 75% YPrPb DAC DAC3 NTSC 55. SD NTSC Subaddress x x82 x84 Setting xc xc9 x4 CVBSS Y/C x82 xc9 xcb RGBYPrPb x2 5 SD NTSC 55 x2 x24 PAL x8 x F SC PAL F SC Subaddress Description Setting x8c F SC xcb x8d F SC x8a x8e F SC 2 x9 x8f F SC 3 x2a ED/HD ADV739x ED/HD 57ED 525p YPrPb DAC DAC3RGBYPrPb x ED 525p Subaddress x x x3 Setting xc x x5 ED 525p 57 x2 x24 ED 525p 57 x3 xd Y Cr Cbx36 x37 x38 525pED/HD 57 x3 [7:3] F SC F SC F SC F SC 2 F SC 3 F SC F SC 3

72 ADV739/ADV739/ADV7392/ADV SD CCIR-656 x8a XXXXX ADV739x SAV start of active video EAV end of active video 4 VSYNCHSYNC ANALOG VIDEO INPUT PIXELS NTSC/PAL M SYSTEM (525 LINES/6Hz) PAL SYSTEM (625 LINES/5Hz) Y C r Y EAV CODE F F END OF ACTIVE VIDEO LINE 2. X Y 8 8 F F A A A F F B B B SD 8 SAV CODE 8 F X C F Y b Y C r Y C b 4 CLOCK ANCILLARY DATA (HANC) 4 CLOCK 268 CLOCK 44 CLOCK 4 CLOCK 4 CLOCK 28 CLOCK 44 CLOCK START OF ACTIVE VIDEO LINE Y C C Y r b CCIR-656 x8a XXXXX ADV739x CCIR-656SAVEAV HFH HSYNC F VSYNC DISPLAY VERTICAL BLANK DISPLAY H F EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY H F ODD FIELD EVEN FIELD 3. SDNTSC

73 ADV739/ADV739/ADV7392/ADV7393 DISPLAY VERTICAL BLANK DISPL AY H F EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY H F ODD FIELD EVEN FIELD 4. SDPAL ANALOG VIDEO H F 5. SD x8a XXXXX ADV739xHSYNC ADV739x CCIR-624 HSYNC FIELDHSYNCVSYNC DISPLAY VERTICAL BLANK DISPLAY HSYNC FIELD EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY HSYNC FIELD ODD FIELD EVEN FIELD 6. SDNTSC

74 ADV739/ADV739/ADV7392/ADV7393 DISPLAY VERTICAL BLANK DISPLAY HSYNC FIELD EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY HSYNC FIELD ODD FIELD EVEN FIELD 7. SDPAL x8a XXXXX AD739xHSYNC ADV739x CCIR-624 HSYNC FIELDHSYNCVSYNC HSYNC FIELD PIXEL DATA Cb Y Cr Y 8. PAL = 32 CLOCK/2 NTSC = 22 CLOCK/2 SD x8A XXXXX AD739xHSYNC VSYNC HSYNC VSYNC ADV739x CCIR-624HSYNC VSYNC HSYNCVSYNC

75 ADV739/ADV739/ADV7392/ADV7393 DISPLAY VERTICAL BLANK DISPLAY HSYNC VSYNC EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY HSYNC VSYNC ODD FIELD EVEN FIELD 9. SD2NTSC DISPLAY VERTICAL BLANK DISPLAY HSYNC VSYNC EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY HSYNC VSYNC ODD FIELD EVEN FIELD. SD2PAL x8A XXXXX ADV739x HSYNCVSYNC HSYNC VSYNC ADV739x CCIR-624 HSYNC VSYNCHSYNCVSYNC HSYNC VSYNC PIXEL DATA Cb Y Cr Y. PAL = 32 CLOCK/2 NTSC = 22 CLOCK/2 SD

76 ADV739/ADV739/ADV7392/ADV7393 HSYNC VSYNC PAL = 864 CLOCK/2 NTSC = 858 CLOCK/2 PIXEL DATA Cb Y Cr Y Cb 2. PAL = 32 CLOCK/2 NTSC = 22 CLOCK/2 SD x8a XXXXXXXXXX ADV739x HSYNC ADV739x CCIR-624 HSYNC VSYNCHSYNCVSYNC DISPLAY VERTICAL BLANK DISPL AY HSYNC FIELD EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY HSYNC FIELD ODD FIELD EVEN FIELD SD3 NTSC DISPLAY VERTICAL BLANK DISPLAY HSYNC FIELD EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY HSYNC FIELD EVEN FIELD ODD FIELD SD3 PAL

77 ADV739/ADV739/ADV7392/ADV HD DISPLAY FIELD VERTICAL BLANKING INTERVAL VSYNC HSYNC DISPLAY FIELD 2 VERTICAL BLANKING INTERVAL VSYNC HSYNC 5. 8i HSYNC /VSYNC

78 ADV739/ADV739/ADV7392/ADV SD YPrPbSMPTE/EBU N % 6. Y NTSC 7. Pr NTSC 8. Pb NTSC 9. Y PAL 2. Pr PAL 2. Pb PAL WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 7mV WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 7mV mV 3mV WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 7mV WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 7mV mV 7mV WHITE YELLOW CYAN GREEN AGENT M A RED BLUE BLACK

79 ADV739/ADV739/ADV7392/ADV7393 ED/HD YPrPb INPUT CODE EIA-77.2, STANDARD FOR Y OUTPUT VOLTAGE INPUT CODE EIA-77.3, STANDARD FOR Y OUTPUT VOLTAGE mV 7mV mV 3mV EIA-77.2, STANDARD FOR Pr/Pb OUTPUT VOLTAGE EIA-77.3, STANDARD FOR Pr/Pb OUTPUT VOLTAGE mV 52 7mV 52 7mV EIA P/625P 24. EIA i/72P INPUT CODE 94 EIA-77., STANDARD FO R Y OUTPUT VOLTAGE 782mV INPUT CODE 23 Y OUTPUT LEVELS FOR FULL INPUT SELECTION OUTPUT VOLTAGE 74mV 7mV mV 286mV EIA-77., STANDARD FOR Pr/Pb OUTPUT VOLTAGE INPUT CODE Pr/Pb OUTPUT LEVELS FOR FULL INPUT SELECTION OUTPUT VOLTAGE mV 7mV mV EIA P/625P 25.

80 ADV739/ADV739/ADV7392/ADV7393 SD/ED/HD RGB % 75% R 7mV/525mV R 7mV/525mV 3mV 3mV G 7mV/525mV G 7mV/525mV 3mV 3mV B 7mV/525mV B 7mV/525mV 26. 3mV SD/ED RGBRGB mV 28. HD RGBRGB R 7mV/525mV 6mV R 7mV/525mV 3mV 3mV mv mv G 7mV/525mV 6mV G 7mV/525mV 3mV 3mV mv mv B 7mV/525mV 6mV B 7mV/525mV 3mV 3mV mv mv SD/ED RGBRGB 29. HD RGBRGB

81 ADV739/ADV739/ADV7392/ADV7393 SD VOLTS IRE:FLT VOLTS F L MICROSECONDS APL = 44.5% 525 LINE NTSC PRECISION MODE OFF SYNCHRONOUS SYNC = A SLOW CLAMP TO.V AT 6.72 µ s FRAMES SELECTED, 2 3. NTSC 75% L MICROSECONDS NOISE REDUCTION:.dB APL = 39.% 625 LINE NTSC NO FILTERING SLOW CLAMP TO. AT 6.72µs 33. PRECISION MODE OFF SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED, 2, 3, 4 PAL VOLTS IRE:FLT VOLTS F2 L MICROSECONDS NOISE REDUCTION: 5.5dB APL = 44.3% 525 LINE NTSC NO FILTERING PRECISION MODE OFF SYNCHRONOUS SYNC = SOURCE SLOW CLAMP TO.V AT 6.72 µ s FRAMES SELECTED, 2 3. NTSC L575 2 MICROSECONDS APL NEEDS SYNC SOURCE. NO BUNCH SIGNAL 625 LINE PAL NO FILTERING PRECISION MODE OFF SLOW CLAMP TO. AT 6.72µs SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED PAL VOLTS IRE:FLT.4 5 VOLTS F L MICROSECONDS NOISE REDUCTION: 5.5dB APL NEEDS SYNC SOURCE. 525 LINE NTSC NO FILTERING SLOW CLAMP TO. AT 6.72µs 32. PRECISION MODE OFF SYNCHRONOUS SYNC = B FRAMES SELECTED, 2 NTSC L575 2 APL NEEDS SYNC SOURCE. 625 LINE PAL NO FILTERING SLOW CLAMP TO. AT 6.72µs MICROSECONDS NO BUNCH SIGNAL 35. PRECISION MODE OFF SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED PAL