Nios II Ver. 7.1 2007 10 1. Nios II Nios II JTAG UART LED 8 PIO LED < > Quartus II SOPC Builder Nios II Quartus II.sof Nios II IDE Stratix II 2S60 RoHS Nios II Quartus II http://www.altera.com/literature/lit-nio2.jsp Quartus II NiosII IDE SOPC Builder HDL.sof.elf FPGA Page 1 of 21 Altima Corporation
2. 2-1. (Quartus II) Quartus II Quartus II File New Project Wizard New Project Wizard Introduction Next 1 ver. 7.1 2007 10 Page 2 of 21 Altima Corporation
Next 2 Family Stratix II Available devices EP2S60F672C3 Next 2 Finish ver. 7.1 2007 10 Page 3 of 21 Altima Corporation
2-2. Assignments Device Device and Pin Options Device and Pin Options Unused Pins Reserve all unused pins: As input tri-stated OK ver. 7.1 2007 10 Page 4 of 21 Altima Corporation
2-3. SOPC Builder HDL Quartus II Tools SOPC Builder SOPC Builder Create New System System Name SOPC Builder Target HDL Verilog VHDL SOPC Builder HDL SOPC Builder Memories and Memory Controllers On-Chip On-Chip Memory (RAM or ROM) On-Chip Memory (RAM or ROM) Block type M4K Total memory size 64 K Bytes Finish ver. 7.1 2007 10 Page 5 of 21 Altima Corporation
SOPC Builder Nios II Processor Nios II Processor Nios II Reset Vector Exception Vector onchip_mem Finish ver. 7.1 2007 10 Page 6 of 21 Altima Corporation
SOPC Builder Peripherals Microcontroller Peripherals PIO(Parallel I/O) Finish ver. 7.1 2007 10 Page 7 of 21 Altima Corporation
SOPC Builder Interface Protocols Serial JTAG UART Finish ver. 7.1 2007 10 Page 8 of 21 Altima Corporation
SOPC Builder Base Generate HDL Base Auto-Assign Base Addresses Base Generate Generate Exit ver. 7.1 2007 10 Page 9 of 21 Altima Corporation
2-4. Quartus II.bdf HDL Quartus II File New New Block Diagram/Schematic File OK Block1.bdf Symbol Project SOPC sopc_system OK ver. 7.1 2007 10 Page 10 of 21 Altima Corporation
Block1.bdf Symbol Name input OK SOPC Builder clk reset_n Name output Name not led clk reset_n led_pio[7..0] File Save As.bdf Quartus II Quartus II Processing Start Analysis & Elaboration ver. 7.1 2007 10 Page 11 of 21 Altima Corporation
Quartus II Assignments Pins Pin Planner Stratix II 2S60 RoHS clk led_pio[7] led_pio[6] led_pio[5] led_pio[4] led_pio[3] led_pio[2] led_pio[1] led_pio[0] reset_n B13 V17 AD18 AB17 V16 AA17 AD17 V14 W15 AA15 Location Quartus II Processing Start Compilation ver. 7.1 2007 10 Page 12 of 21 Altima Corporation
2-5. FPGA USB-Blaster TM Quartus II Programmer.sof FPGA Tools Programmer.sof Program/Configure Start 2-6. Nios II IDE Windows Nios II IDE Nios II IDE Quartus II workspace Nios II IDE File Switch Workspace Browse OK Nios II IDE Welcome Welcome Workbench ver. 7.1 2007 10 Page 13 of 21 Altima Corporation
Nios II IDE Nios II IDE File New Project New Project New Project Nios II C/C++ Application Next ver. 7.1 2007 10 Page 14 of 21 Altima Corporation
Name SOPC Builder System PTF File Browse.ptf Select Project Template Blank Project Finish ver. 7.1 2007 10 Page 15 of 21 Altima Corporation
Nios II Nios II IDE File New Source File New Source File Source Folder Browse _syslib Source File.c Finish Nios II IDE ver. 7.1 2007 10 Page 16 of 21 Altima Corporation
_syslib Properties onchip_mem OK Nios II IDE _syslib Build Project ver. 7.1 2007 10 Page 17 of 21 Altima Corporation
2-7. Nios II IDE _syslib Run As Nios II Hardware Console printf LED Nios II IDE _syslib Debug As Nios II Hardware ver. 7.1 2007 10 Page 18 of 21 Altima Corporation
Yes Nios II IDE ver. 7.1 2007 10 Page 19 of 21 Altima Corporation
ver. 7.1 2007 10 Page 20 of 21 Altima Corporation
2. 3. 4. 5. 6. ver. 7.1 2007 10 Page 21 of 21 Altima Corporation