PLDとFPGA

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1 PLDFPGA 2002/12

2 PLDFPGA PLD:Programmable Logic Device FPGA:Field Programmable Gate Array Field: Gate Array: LSI MPGA:Mask Programmable Gate Array» FPGA:»» 2

3 FPGA FPGALSI FPGA FPGA Altera, Xilinx FPGA DVD W-CDMA FPGA 3

4 (PLD) LSI MPD FPD: PLD PLA PLA:Programmable Logic Array GAL PLD PLD» AND-OR PAL:Programmable Array Logic»OR» GAL, PLD( ) FPGA PAL GA (MPGA) 4

5 PLD OR OR PAL OR AND AND DFF PLA, PAL GAL, PLD PLA, PAL GAL, PLD 5

6 PAL AB+AC A B C 6

7 FPGA (Field Programmable Gate Array) PLD MPGAMask Programmable Gate Array GA 7

8 FPGA 8

9 FPGA FPGA SRAM. EPROM, EEPROM.,. 9

10 FPGA :SRAM WL BL BL To Switch SRAM 1SRAM : 6Tr 10

11 FPGA (2) Floating Gate IN EPROM EEPROM OUT >100G A B A B open Apply 16V between A and B Antifuse T 11

12 SRAM FPGA FPGA: LUT Look-Up Table) 1 SRAM» ON,OFF SRAM 12

13 LUT(Look-up Table) SRAMFPGA A B C D A, B, C, D4 1 SRAM SRAM SRAM 1 (A B)&(C D) LUT

14 : SRAMFPGA 14

15 XILINX XC A CLB CLB CLB B C (LUT) (SRAM) FF CLB CLB CLB CLB CLB CLB D CLB CLB CLB CLB CLB: Configurable Logic Block 15

16 ALTERA FLEX (CPLD ) (LE) A B C D LAB (LAB LE) LUT FF (LE) (LAB) ( 1) LAB 16

17 FPGA SRAM EPROM EEPROM SRAM FPGA 0.15µm 17

18 FPGA FPGA2 XILINXALTERA Actel: antifuse, Mars Path-Finder Lucent:PCIATM FPGA Philips, Lattice: CPLD (Complex PLD) 18

19 XILINX CPLD XC9500 Flash MC (Glue Logic ) XCR3000 EEPROM MC FPGA XC4000 SRAM 13k 85k 3.3V SPARTAN SRAM 5k 200k ASIC VIRTEX SRAM 50k-10M FPGA, FPGA VIRTEXII SRAM? CPU 19

20 ALTERA MAX EEPROM MC ACEX SRAM 10k-100k FLEX SRAM 10k-250k APEX SRAM 30k-1500k SOPC(System on a Programmable Chip) Excalibur SRAM 100k-100k CPU 20

21 FPGA SRAMFPGA LUT RAM,ROM,CAM(Content Addressable Memory), FIFO, CPU LSI 1/10 ARM, MIPS 32bit 21

22 FPGA FLEX K (Embedded Array Block) SRAM LUT SRAM SRAM,FIFO, RAM, CAM LUT : (5bit4bit), 9 22

23 FPGA TAT(Turn-Around Time). ( ) IP(Intellectual Property)» (Hardcopy by ALTERA) 23

24 FPGA nand2 A C B HDL module nand_g(c,a,b); input A,B; output C; assign C=~(A&B); endmodule LSI module nand_g(c,a,b); input A,B;output C; nand2 I0(C,A,B); endmodule LUT FPGA FPGA LE LSI CAD FPGA FPGA 24

25 CADFPGA CAD Synopsys FPGA Compiler II Mentor Leonald Synplicity Synplify Synopsys(Viewlogic) WorkView Office FPGA ALTERA MAX+plus II Quartus, XILINX Alliance, Actel DeskTop FPGA Compiler IIVDEC FPGA See 25

26 FPGA circuit.acf FPGA Verilog-HDL FPGA SynplifyPro circuit.edf EDIF MAXPLUS2 RTL FPGA circuit.sof, ttf, pof SRAM RTL FPGA Power Medusa EA-40 26

HDL ( ) module calc(decimal,plus,minus,equal,clk,rst,ce,sign,overflow,out); module calc(decimal,plus,minus,equal,clk,rst,ce,sign,overflow,out); input [9:0] decimal; input [9:0] decimal; input

27 HDL ( ) module calc(decimal,plus,minus,equal,clk,rst,ce,sign,overflow,out); module calc(decimal,plus,minus,equal,clk,rst,ce,sign,overflow,out); input [9:0] decimal; input [9:0] decimal; input CLK,CE,RST,plus,minus,equal; input CLK,CE,RST,plus,minus,equal; output sign,overflow; output sign,overflow; output [6:0] out; output [6:0] out; wire [3:0] d; wire [3:0] d; wire [8:0] alu_out; wire [8:0] alu_out; reg [1:0] state; reg [1:0] state; reg [8:0] REGA, REGB; reg [8:0] REGA, REGB; reg [1:0] count; reg [1:0] count; reg add_or_sub; reg add_or_sub; assign d=dectobin(decimal); assign d=dectobin(decimal); CLK or negedge RST) CLK or negedge RST) begin begin if(!rst) if(!rst) begin begin REGA<=0;REGB<=0;count<=0; REGA<=0;REGB<=0;count<=0; add_or_sub<=0; add_or_sub<=0; state<=`decimal; state<=`decimal; end end else else HDL ( ) 27

28 FPGA FPGA FPGA Power Medusa CQ Flex10KE 28

Microsoft PowerPoint - FPGA

Microsoft PowerPoint - FPGA PLD と FPGA VLD 講習会京都大学小林和淑 1 PLD FPGA って何 PLD: Programmable Logic Device プログラム可能な論理素子 FPGA: Field Programmable Gate Array 野外でプログラム可能な門の隊列? Field: 設計現場 Gate Array: 論理ゲートをアレイ上に敷き詰めたLSI MPGA: Mask Programmable