お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com) 発行 ルネサスエレクトロニクス株式会社 (http://www.renesas.com) 問い合わせ先 http://japan.renesas.com/inquiry Not recommend for new design 2010 年 4 月 1 日ルネサスエレクトロニクス株式会社
Not recommend 2. 3. 4. 5. 6. 7. OA AV 8. 9. 10. RoHS 11. 12. for new design 1. 2. 1
HN58X2402SFPIAG HN58X2404SFPIAG Two-wire serial interface 2k EEPROM (256-word 8-bit) 4k EEPROM (512-word 8-bit) RJJ03C0117-0400 Rev.4.00 2005.07.13 HN58X24xxSFPIAG 2 EEPROM ROM MNOS CMOS 8 1.8V 5.5V 2 (I 2 C TM * 1 ) 400kHz 3µA (max) 1mA (max) 3mA (max) 8 10ms (2.7V 5.5V) 15ms (1.8V 2.7V) 10 5 10 SOP8 2,500IC/reel 1. I 2 C Philips Rev.4.00, 2005.07.13, page 1 of 16
Type No. Internal organization Operating voltage Frequency Package HN58X2402SFPIAGE 2k bit (256 8-bit) 1.8V to 5.5V 400kHz 150 mil 8-pin plastic SOP PRSP0008DF_B (FP-8DBV) HN58X2404SFPIAGE 4k bit (512 8-bit) 8-pin SOP A0 A1 A2 V SS 1 2 3 4 8 7 6 5 V CC WP SCL SDA (Top view) A0 to A2 SCL SDA WP V CC V SS Pin name Device address Serial clock input Serial data input/output Write protect Power supply Ground Function V CC High voltage generator V SS WP A0, A1, A2 SCL Control logic Address generator X decoder Y decoder Memory array Y-select & Sense amp. SDA Serial-parallel converter Rev.4.00, 2005.07.13, page 2 of 16
Parameter Symbol Value Unit Supply voltage relative to V SS V CC 0.6 to +7.0 V Input voltage relative to V SS Vin 0.5* 2 to +7.0* 3 V Operating temperature range* 1 Topr 40 to +85 C Storage temperature range Tstg 65 to +125 C 1. 2. 50ns 3.0V 3. V CC +1.0V DC Parameter Symbol Min Typ Max Unit Supply voltage V CC 1.8 5.5 V V SS 0 0 0 V Input high voltage V IH V CC 0.7 V CC + 1.0 V Input low voltage V IL 0.3* 1 V CC 0.3 V Operating temperature Topr 40 +85 C 1. 50ns 1.0V DC (Ta = 40 +85 C, V CC = 1.8 V 5.5V) Parameter Symbol Min Typ Max Unit Test conditions Input leakage current I LI 2.0 µa V CC = 5.5 V, Vin = 0 to 5.5 V (SCL, SDA) 20 µa V CC = 5.5 V, Vin = 0 to 5.5 V (A0 to A2, WP) Output leakage current I LO 2.0 µa V CC = 5.5 V, Vout = 0 to 5.5 V Standby V CC current I SB 1.0 3.0 µa Vin = V SS or V CC Read V CC current I CC1 1.0 ma V CC = 5.5 V, Read at 400kHz Write V CC current I CC2 3.0 ma V CC = 5.5 V, Write at 400kHz Output low voltage V OL2 0.4 V V CC = 4.5 to 5.5 V, I OL = 1.6mA V CC = 2.7 to 4.5 V, I OL = 0.8mA V CC = 1.8 to 2.7 V, I OL = 0.4mA V OL1 0.2 V V CC = 1.8 to 2.7 V, I OL = 0.2mA (Ta = +25 C, f = 1 MHz) Parameter Symbol Min Typ Max Unit Test conditions Input capacitance (A0 to A2, SCL, WP) Cin* 1 6.0 pf Vin = 0 V Output capacitance (SDA) C I/O * 1 6.0 pf Vout = 0 V 1. Rev.4.00, 2005.07.13, page 3 of 16
AC (Ta = 40 +85 C, V CC = 1.8 5.5 V) V IL = 0.2 V CC V IH = 0.8 V CC 20 ns 0.5 V CC 1TTL Gate + 100 pf Parameter Symbol Min Typ Max Unit Notes Clock frequency f SCL 400 khz Clock pulse width low t LOW 1200 ns Clock pulse width high t HIGH 600 ns Noise suppression time t I 50 ns 1 Access time t AA 100 900 ns Bus free time for next mode t BUF 1200 ns Start hold time t HD.STA 600 ns Start setup time t SU.STA 600 ns Data in hold time t HD.DAT 0 ns Data in setup time t SU.DAT 100 ns Input rise time t R 300 ns 1 Input fall time t F 300 ns 1 Stop setup time t SU.STO 600 ns Data out hold time t DH 50 ns Write protect hold time t HD.WP 1200 ns Write protect setup time t SU.WP 0 ns Write cycle time V CC = 2.7 V to 5.5 V t WC 10 ms 2 V CC = 1.8 V to 2.7 V t WC 15 ms 2 1. 2. t WC Rev.4.00, 2005.07.13, page 4 of 16
Bus Timing t F 1/f SCL t HIGH t LOW t R SCL t SU.STA t HD.STA t HD.DAT t SU.DAT tsu.sto SDA (in) t BUF t AA t DH SDA (out) t SU.WP thd.wp WP Write Cycle Timing Stop condition Start condition SCL SDA D0 in Write data (Address (n)) ACK t WC (Internally controlled) Rev.4.00, 2005.07.13, page 5 of 16
(SCL) 400kHz (SDA) DC V OL I OL SDA SDA SCL Low Data Validity (SDA data change timing waveform) SCL SDA Data change Data change SDA High Low Low High SCL Low Rev.4.00, 2005.07.13, page 6 of 16
(A0,A1,A2) 8 V CC V SS V CC V SS SDA V SS 4k A0 a8 Pin Connections for A0 to A2 Pin connection Memory size Max connect number A2 A1 A0 Notes 2k bit 8 V CC /V SS * 1 V CC /V SS V CC /V SS 4k bit 4 V CC /V SS V CC /V SS * 2 Use A0 for memory address a8 1. V CC /V SS V CC V SS V SS 2. WP High Write Protect Area Low High/Low WP WRITE WP Write Protect Area Write protect area WP pin status 2k bit 4k bit V IH Entire (2k bit) Entire (4k bit) Normal read/write operation V IL Rev.4.00, 2005.07.13, page 7 of 16
Read Write SCL High SDA High Low Start condition and stop condition SCL High SDA Low High Start condition and stop condition Read Read Write t WC Write cycle timing Start Condition and Stop Condition SCL SDA (in) Start condition Stop condition Rev.4.00, 2005.07.13, page 8 of 16
Acknowledge Read 8bit Acknowledge 8 SCL 9 0 9 Acknowledge EEPROM Write 8 9 EEPROM Acknowledge 0 Read 8 Acknowledge 0 EEPROM Read 8 Acknowledge 0 Acknowledge 0 EEPROM Read Acknowledge 0 Read Acknowledge 0 Acknowledge Timing Waveform SCL 1 2 8 9 SDA IN SDA OUT Acknowledge out Rev.4.00, 2005.07.13, page 9 of 16
Read Write 4bit 3bit Read/Write 1bit 3 4 1010 3 A2 A1 A0 8 A2 A0 High Low 4k 4k A2 A1 2bit 8 R/W(Read/Write) 0 Write 1 Read 1010 Read/Write Device Address Word Device address word (8-bit) Device code (fixed) Device address code* 1 R/W code* 2 2k 1 0 1 0 A2 A1 A0 R/W 4k 1 0 1 0 A2 A1 a8 R/W 1. A2 A0 a8 2. R/W= 1 Read R/W= 0 Write Rev.4.00, 2005.07.13, page 10 of 16
Write Byte Write Read/Write 0 8bit 9bit Acknowledge 0 Write 8bit Acknowledge 0 Write 8bit Write EEPROM Acknowledge 0 LSI SCL SDA Byte Write Operation 2k, 4k Start Device address 1010 W Memory address (n) a7 a6 a5 a4 a3 a2 a1 a0 Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK ACK R/W Stop Page Write 8 Page Write Page Write Byte Write (n) Write (Dn)9bit Acknowledge 0 Write (Dn)Write (Dn+1) Page Write Write (Dn+1) (a0 a2) (n+1) Write Write 8 Write (a0 a2) Roll Over Roll Over Write 2 ( ) Write Write Page Write Operation 2k, 4k Device address 1010 W Memory address (n) a7 a6 a5 a4 a3 a2 a1 a0 Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 Write data (n+m) D5 D4 D3 D2 D1 D0 Start ACK ACK ACK Stop R/W ACK Rev.4.00, 2005.07.13, page 11 of 16
Acknowledge Polling EEPROM Acknowledge Polling 8bit Acknowledge Polling Read/Write 0 9bit Acknowledge Acknowledge 1 Acknowledge 0 Acknowledge Polling Write Write Cycle Polling using ACK Write Cycle Polling using ACK Send write command Send stop condition to initiate write cycle Send start condition Send device address word with R/W = 0 ACK returned No Yes Next operation is addressing the memory No Yes Send memory address Send start condition Send stop condition Proceed write operation Proceed random address read operation Send stop condition Rev.4.00, 2005.07.13, page 12 of 16
Read Read Current Address Read Random Read Sequential Read 3 Read Write 8bit Read/Write 1 Current Address Read EEPROM Read Write (n) 1 (n+1)current Address Read (n+1) Read Write ( R/W= 1 ) Acknowledge 0 (n+1) 8bit Acknowledge 1 Acknowledge Read Read Current Address Roll Over 0 Write Current Address Roll Over Current Address OFF ON Current Address ON Read Random Read Current Address Read Operation 2k, 4k Start Device address * 1 1010 R Note: 1. Don t care bit for 4k. Read data (n+1) D7 D6 D5 D4 D3 D2 D1 D0 ACK R/W No ACK Stop Rev.4.00, 2005.07.13, page 13 of 16
Random Read Read Write Read R/W= 0 Acknowledge 0 Current Address Read Write Acknowledge 1 Acknowledge Read Random Read Operation 2k, 4k Device address Memory address (n) Device address @@@ # # # 1010 W 1010 R a7 a6 a5 a4 a3 a2 a1 a0 Read data (n) D7 D6 D5 D4 D3 D2 D1 D0 Start ACK R/W Start ACK ACK R/W No ACK Stop Dummy write Currect address read Note: 1. 2nd device address code (#) should be same as 1st (@). Sequential Read Read Current Address Read Random Read 8bit Acknowledge 0 8bit Acknowledge 0 0 Roll Over Roll Over Sequential Read Current Address Read Random Read Acknowledge 1 Acknowledge Sequential Read Operation 2k, 4k Device address 1010 R Read data (n) D7 D6 D5 D4 D3 D2 D1 D0 Read data (n+1) Read data (n+2) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Read data (n+m) D5 D4 D3 D2 D1 D0 Start ACK ACK ACK ACK No ACK R/W Stop Rev.4.00, 2005.07.13, page 14 of 16
On/Off On/Off Power on Reset Power on Reset On/Off SCL,SDA V CC V SS Off On On 0 V On 10µs Page Write 1 10 5 1% Byte Write 1 10 4 Page Write 10 4 10 SCL SDA 50ns 50ns 50ns Rev.4.00, 2005.07.13, page 15 of 16
E HN58X2402SFPIAGE / HN58X2404SFPIAGE (PRSP0008DF_B / Previous Code: FP-8DBV) JEITA Package Code P-SOP8-3.9x4.89-1.27 RENESAS Code PRSP0008DF-B Previous Code FP-8DBV MASS[Typ.] 0.08g *1 D 8 5 F bp *2 c E H 1 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Index mark Z 1 e 4 *3 b p x M Terminal cross section ( Ni/Pd/Au plating ) L1 Reference Symbol D E A 2 A 1 A b p 0.35 0.40 b 1 Dimension in Millimeters Min Nom Max 4.89 3.90 5.15 0.102 0.14 0.254 1.73 0.45 c 0.15 0.20 0.25 c 1 A θ 0 8 H E 5.84 6.02 6.20 θ e 1.27 A L x 0.25 y Detail F y Z L 0.10 0.69 0.406 0.60 0.889 L 1 1.06 Rev.4.00, 2005.07.13, page 16 of 16
Rev. 1.0 01. 3. 30 2.00 03. 10. 24 2 17 3.00 2004.12.14 2 16 4.00 2005.07.13 2 4 5 16 HN58X2402SFPIAGE, HN58X2404SFPIAGE FP-8DB FP-8DB, FP-8DBV HN58X2402SFPIAG, HN58X2404SFPIAG FP-8DB AC t HD.WP t SU.WP WP
100-0004 2-6-2 1. 1. 2. 3. (http://www.renesas.com) 4. 5. 6. 7. 8. http://www.renesas.com 100-0004 212-0058 190-0023 980-0013 970-8026 312-0034 950-0087 390-0815 460-0008 541-0044 920-0031 730-0036 680-0822 812-0011 2-6-2 () 890-12 ( ) 2-2-23 ( 2F) 1-1-20 ( 13F) 4-9 ( ) 832-2 ( 1F) 1-4-2 (3F) 1-2-11 (7F) -2-29 ( ) 4-1-1 ( ) 3-1-1 ( 8F) 5-25 ( 8F) 2-251 ( ) 2-17-1 (5F) (03) 5201-5350 (044) 549-1662 (042) 524-8701 (022) 221-1351 (0246) 22-3222 (029) 271-9411 (025) 241-4361 (0263) 33-6622 (052) 249-3330 (06) 6233-9500 (076) 233-5980 (082) 244-2570 (0857) 21-1915 (092) 481-7695 E-Mail: csc@renesas.com 2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 5.5