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R1RP0416D 4M High Speed SRAM (256-kword 16-bit) RJJ03C0095-0200 Rev. 2.00 2008.12.12 R1RP0416D 256k 16 4M RAM CMOS6 R1RP0416D L-Version,S-Version 400-mil 44 SOJ 400-mil 44 TSOPII 5.0V 5.0V ± 10% 10ns / 12ns (max) TTL 170mA / 160mA (max) TTL 40mA (max) CMOS 5mA (max) 1.0mA (max) (L-version) 0.5mA (max) (S-version) 0.5mA (max) (L-version) : 0.2mA (max) (S-version) 2V (min) (L-version,S-version) V CC V SS page 1 of 14
R1RP0416D Type No. Access time Version Package R1RP0416DGE-0PR 10 ns Normal R1RP0416DGE-2PR 12 ns Normal 400-mil 44-pin plastic SOJ (44P0K) R1RP0416DGE-2LR 12 ns L-Version R1RP0416DGE-2SR 12 ns S-Version R1RP0416DSB-0PR 10 ns Normal R1RP0416DSB-2PR 12 ns Normal 400-mil 44-pin plastic TSOPII (44P3W-H) R1RP0416DSB-2LR 12 ns L-Version R1RP0416DSB-2SR 12 ns S-Version page 2 of 14
R1RP0416D 44-pin SOJ 44-pin TSOP A0 A1 A2 A3 A4 CS# I/O1 I/O2 I/O3 I/O4 V CC V SS I/O5 I/O6 I/O7 I/O8 WE# A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE# UB# LB# I/O16 I/O15 I/O14 I/O13 V SS V CC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 A0 A1 A2 A3 A4 CS# I/O1 I/O2 I/O3 I/O4 V CC V SS I/O5 I/O6 I/O7 I/O8 WE# A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE# UB# LB# I/O16 I/O15 I/O14 I/O13 V SS V CC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 (Top View) (Top View) Pin name Function A0 to A17 Address input I/O1 to I/O16 Data input/output CS# Chip select OE# Output enable WE# Write enable UB# Upper byte select LB# Lower byte select V CC Power supply V SS Ground NC No connection page 3 of 14
R1RP0416D (LSB) A14 A13 A12 A5 A6 A7 A11 A10 A3 A1 (MSB) I/O1. I/O8 I/O9. I/O16 Row decoder CS Input data control 1024-row 32-column 8-block 16-bit (4,194,304 bits) Column I/O Column decoder CS Internal voltage generator V CC V SS WE# CS# LB# (LSB) A8 A9 A17 A15 A16 A0 A2 A4 (MSB) UB# OE# CS page 4 of 14
R1RP0416D CS# OE# WE# LB# UB# Mode V CC current I/O1 I/O8 I/O9 I/O16 Ref. cycle H Standby I SB, I SB1 High-Z High-Z L H H Output disable I CC High-Z High-Z L L H L L Read I CC Output Output Read cycle L L H L H Lower byte read I CC Output High-Z Read cycle L L H H L Upper byte read I CC High-Z Output Read cycle L L H H H I CC High-Z High-Z L L L L Write I CC Input Input Write cycle L L L H Lower byte write I CC Input High-Z Write cycle L L H L Upper byte write I CC High-Z Input Write cycle L L H H I CC High-Z High-Z H: V IH, L: V IL, : V IH or V IL Parameter Symbol Value Unit Supply voltage relative to V SS V CC 0.5 to +7.0 V Voltage on any pin relative to V SS V T 0.5* 1 to V CC + 0.5* 2 V Power dissipation P T 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg 55 to +125 C Storage temperature under bias Tbias 10 to +85 C 1. (under shoot) 6ns 2.0V 2. (over shoot) 6ns V CC + 2.0V DC (Ta = 0 to +70 C) Parameter Symbol Min Typ Max Unit Supply voltage V CC * 3 4.5 5.0 5.5 V V SS * 4 0 0 0 V Input voltage V IH 2.2 V CC + 0.5* 2 V V IL 0.5* 1 0.8 V 1. (under shoot) 6ns 2.0V 2. (over shoot) 6ns V CC + 2.0V 3. V CC 4. V SS page 5 of 14
R1RP0416D DC (Ta = 0 to +70 C, V CC = 5.0V ± 10%, V SS = 0 V) Parameter Symbol Min Max Unit Test conditions Input leakage current I LI 2 µa V IN = V SS to V CC Output leakage current I LO 2 µa V IN = V SS to V CC Operating power supply current 10ns cycle I CC 170 ma 12ns cycle I CC 160 ma Min cycle CS# = V IL, I OUT = 0 ma Other inputs = V IH /V IL Standby power supply current I SB 40 ma Min cycle, CS# = V IH, Other inputs = V IH /V IL I SB1 5 ma f = 0 MHz V CC CS# V CC 0.2 V, (1) 0 V V IN 0.2 V or (2) V CC V IN V CC 0.2 V * 1 1.0* 1 ma * 2 0.5* 2 ma Output voltage V OL 0.4 V I OL = 8 ma 1. L 2. S V OH 2.4 V I OH = 4 ma (Ta = +25 C, f = 1.0MHz) Parameter Symbol Min Max Unit Test conditions Input capacitance* 1 C IN 6 pf V IN = 0 V Input/output capacitance* 1 C I/O 8 pf V I/O = 0 V 1. page 6 of 14
R1RP0416D AC (Ta = 0 to +70 C, V CC = 5.0V ± 10%, unless otherwise noted.) 3.0V/0.0V 3ns 1.5V 1.5 V 5 V D OUT Zo = 50 Ω RL = 50 Ω D OUT 480 Ω 30 pf 255 Ω 5 pf Output load (A) Output load (B) (for t CLZ, t OLZ, t BLZ, t CHZ, t OHZ, t BHZ, t WHZ, and t OW ) R1RP0416D 10ns 12ns Parameter Symbol Min Max Min Max Unit Notes Read cycle time t RC 10 12 ns Address access time t AA 10 12 ns Chip select access time t ACS 10 12 ns Output enable to output valid t OE 5 6 ns Byte select to output valid t BA 5 6 ns Output hold from address change t OH 3 3 ns Chip select to output in low-z t CLZ 3 3 ns 1 Output enable to output in low-z t OLZ 0 0 ns 1 Byte select to output in low-z t BLZ 0 0 ns 1 Chip deselect to output in high-z t CHZ 5 6 ns 1 Output disable to output in high-z t OHZ 5 6 ns 1 Byte deselect to output in high-z t BHZ 5 6 ns 1 page 7 of 14
R1RP0416D 10ns R1RP0416D 12ns Parameter Symbol Min Max Min Max Unit Notes Write cycle time t WC 10 12 ns Address valid to end of write t AW 7 8 ns Chip select to end of write t CW 7 8 ns 8 Write pulse width t WP 7 8 ns 7 Byte select to end of write t BW 7 8 ns Address setup time t AS 0 0 ns 5 Write recovery time t WR 0 0 ns 6 Data to write time overlap t DW 5 6 ns Data hold from write time t DH 0 0 ns Write disable to output in low-z t OW 3 3 ns 1 Output disable to output in high-z t OHZ 5 6 ns 1 Write enable to output in high-z t WHZ 5 6 ns 1 1. B±200mV 2. CS# LB# UB# low WE# low WE# high-z 3. WE# CS# high 4. CS# OE# LB# UB# low I/O 5. t AS CS# WE# LB# UB# low 6. t WR CS# WE# LB# UB# high 7. CS# lowwe# lowlb# UB# low t WP CS# low WE# low LB# UB# low CS# high WE# high LB# UB# high 8. t CW CS# low page 8 of 14
R1RP0416D (1) (WE# = V IH ) t RC Address Valid address t AA t ACS CS# t OE t CHZ * 1 OE# t BA t OHZ * 1 LB#, UB# t BLZ * 1 t OLZ * 1 t BHZ * 1 t OH t CLZ * 1 D OUT High impedance * 4 Valid data * 4 page 9 of 14
R1RP0416D (2) (WE# = V IH, LB# = V IL, UB# = V IL ) t RC Address CS# Valid address t AA t ACS t OE t OH t CHZ * 1 t OHZ * 1 OE# t OLZ * 1 t CLZ * 1 D OUT High impedance* 4 * 4 Valid data page 10 of 14
R1RP0416D (1) (WE# Controlled) t WC Address Valid address t AW t WR WE#* 3 t AS t WP t CW CS#* 3 OE# t BW LB#, UB# t WHZ t OLZ t OHZ t OW D OUT High impedance * 2 t DW t DH D IN Valid data page 11 of 14
R1RP0416D (2) (CS# Controlled) t WC Address Valid address t AW t WR t AS t WP WE# * 3 t CW CS# * 3 OE# t BW LB#, UB# t WHZ t OHZ t OLZ t OW D OUT High impedance * 4 * 2 t DW t DH D IN Valid data page 12 of 14
R1RP0416D (3) (LB#, UB# Controlled, OE# = V IH ) t WC Address Valid address t AW t WP t WR WE#* 3 t CW CS#* 3 t AS t BW UB# (LB#) t BW LB# (UB#) t DW t DH D IN -UB (D IN -LB) Valid data t DW t DH D IN -LB (D IN -UB) Valid data D OUT High impedance page 13 of 14
R1RP0416D (Ta = 0 to +70 C) L /S Parameter Symbol Min Max Unit Test conditions V CC for data retention V DR 2.0 V V CC CS# V CC 0.2 V, (1) 0 V V IN 0.2 V or (2) V CC V IN V CC 0.2 V Data retention current L-Version I CCDR 500 S-Version I CCDR 200 µa V CC = 3 V V CC CS# V CC 0.2 V, (1) 0 V V IN 0.2 V or (2) V CC V IN V CC 0.2 V Chip deselect to data retention time t CDR 0 ns See retention waveform Operation recovery time t R 5 ms V CC 4.5 V t CDR Data retention mode t R 2.2 V V DR CS# 0 V V CC CS# V CC 0.2 V page 14 of 14
R1RP0416D Rev. 0.01 Sep. 30, 2003 1.00 2004.03.12 2.00 2008.12.12 P2 P2 P6 P7 P8 P14
100-0004 2-6-2 100-0004 190-0023 980-0013 970-8026 312-0034 950-0087 390-0815 460-0008 541-0044 920-0031 730-0036 812-0011 2-6-2 () 2-2-23 () 1-1-20 () 120 () 832-2 () 1-4-2 () 1-2-11 () 4-2-29 () 4-1-1 () 3-1-1 () 5-25 () 2-17-1 () http://www.renesas.com (03) 5201-5350 (042) 524-8701 (022) 221-1351 (0246) 22-3222 (029) 271-9411 (025) 241-4361 (0263) 33-6622 (052) 249-3330 (06) 6233-9500 (076) 233-5980 (082) 244-2570 (092) 481-7695 E-Mail: csc@renesas.com 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 10.1