XAPP485 (v1.1) 2006 11 10 R : Spartan-3E FPGA Spartan-3E FPGA 666Mbps 1:7 : Nick Sawyer (v1.1) Spartan -3E 666 / (Mbps) 1:7 Spartan-3E 4 5 666Mbps 1/7 Spartan-3E FPGA DCM ( ) DFS ( ) 3.5 DDR ( ) 1:7 DDR Spartan-3E FPGA DFS Spartan-3E FPGA -4 622Mbps -5 666Mbps Clock Clock 4- or 5-bit LVDS Data Spartan-3E Receiver Macro 28- or 35-bit Received Data 1 : 1:7 XAPP485_01_021206 ( 4 ) 2 2 7 4 5 2006 Xilinx, Inc. All Rights Reserved. XILINX Xilinx Xilinx Xilinx Xilinx Inc. : Xilinx Xilinx Xilinx XAPP485 (v1.1) 2006 11 10 japan.xilinx.com 1
R 4-Bit Data Framing Rx Clock 16 20 24 0 4 8 12 16 20 24 0 4 8 Data Line 0 17 21 25 1 5 9 13 17 21 25 1 5 9 18 22 26 2 6 10 14 18 22 26 2 6 10 19 23 27 3 7 11 15 19 23 27 3 7 11 Data Line 1 Data Line 2 Data Line 3 28 bits in one data word 5-Bit Data Framing 20 25 30 0 5 10 15 20 25 30 0 5 10 Data Line 0 21 26 31 1 6 11 16 21 26 31 1 6 11 22 27 32 2 7 12 17 22 27 32 2 7 12 23 28 33 3 8 13 18 23 28 33 3 8 13 24 29 34 4 9 14 19 24 29 34 4 9 14 Data Line 1 Data Line 2 Data Line 3 Data Line 4 35 bits in one data word X485_02_032606 2 : 4 5 DFS / (IOB) DDR DCM CC (Clock Capable) IOB (GCLK ) Spartan-3E (I/O 0) (I/O 2) 2 I/O 0 Spartan-3E FPGA IOB IOB 2 2 japan.xilinx.com XAPP485 (v1.1) 2006 11 10
R 1 DFS 3.5 ( 90 ) ISE 8.1 SP3 55 ( ) ISE 110 DFS ZIP 1 FPGA (P) DCM (T) (V) 9 DDR 1 1 Spartan-3E 2 1 1 1 DFS 2 2 DFS CLKFX CLKFX180 180 2 2 DFS 333MHz ( 666Mbps) -4 622Mbps DFS FPGA DFS 5MHz ( 17.5Mbps) 3 2 3.5 ( 1 ) Rx Clock Rxclock35 Rxclock35not 3 : X485_03_03260 XAPP485 (v1.1) 2006 11 10 japan.xilinx.com 3
R IOB DDR 4 5 4 M=7 D=2 DCM CLK0 CLKFX rxclk rxclk35 CLKFX180 rxclk35not rxclk35not Rx Clock In IOB DDR Flip-Flops 2 State Machine CE Data In rxclk35 5 10 Parallel Registers 40 35 35 dataout 4 : Spartan-3E 1:7 (5 ) X485_04_031206 2 rxclk35 10 (5 ) 8 (4 ) 3.5 2 35 (5 ) 28 (4 ) 5 1 40 30 4 32 24 (ps) ASSP RSKM 2 5 RSKM 4 japan.xilinx.com XAPP485 (v1.1) 2006 11 10
R Bit Period Clock Uncertainty/2 RSKM Sample Window RSKM 5 : (RSKM) Clock Uncertainty/2 X485_07_032606 1. 1 T SAMP VLDS Spartan-3E 600ps a. IOB b. 2 c. d. IOB 50ps 2. 1 CLKOUT_PER_JITT_FX_35 T J35 Spartan-3E FPGA Spartan-3E 400ps + 2 ( ) a. DFS 3.5 DFS b. ( ) T J35 (150ps) c. PCB d. FPGA 12 40MHz 25 e. I/O 40MHz 40 SSO ( ) f. 4 FT256 XAPP485 (v1.1) 2006 11 10 japan.xilinx.com 5
R RSKM Excel (xapp485.zip) 5 RSKM 600Mbps DFS 300MHz 1666ps 1/600Mbps ( ps) T SAMP 600ps T J35 400 + 0.02 (10 6 / 300) ps 500ps PCB = 100ps RSKM 1666ps 1/600Mbps ( ps) T SAMP 600ps T J35 400 + 0.02 (10 6 /300) ps = 600ps 2 300ps RSKM DS312 : Spartan-3E -4-5 Spartan-3E 1 1 : RSKM CLKOUT_PER_JITT_FX_35 (T J35 ) T SAMP CLKFX_MULTIPLY = 7 CLKFX_DIVIDE = 2 DCM CLKFX/CLKFX180 4 PCB FT256 150ps 40MHz 25% SSO ( ) 40MHz 40 IOB 2 I/O -5-4 ±[CLKFX 2 + 400] ps 600 ps 4 5 Verilog VHDL (xapp485.zip) (UCF ) / ZIP / spartan3e.serdes71@xilinx.com E ( ) BGA VQ100 TQ144 PQ208 QFP (Quad Flat Pack) 6 japan.xilinx.com XAPP485 (v1.1) 2006 11 10
R 2 500Mbps I/O DCM 4 5 DC spartan3e.serdes71@xilinx.com E ( ) ISE 8.1 SP2 Synplicity 8.4 ISE VHDL Verilog 2 1. ISE (Synplicity ) [Synthesize-XST] [Properties] [Keep Hierarchy] [Yes] 2. ISE ignore_keep_hierarchy mapper ( Synplicity ) [Implement Design] [Map] [Properties] [Other Map Command Line Options] ignore_keep_hierarchy (*.UCF) RLOC_ORIGIN I/O 0 4 4 x CLB 3 ( 6 ) 5 4 x CLB 4 ( 7 ) LVDS 100Ω PCB DIFF_TERM IOB FPGA DIFF_TERM 120Ω LVDS Spartan-3E FPGA DIFF_TERM XAPP485 (v1.1) 2006 11 10 japan.xilinx.com 7
R RLOC_ORIGIN 6 : 4 Spartan-3E X485_05_021206 RLOC_ORIGIN 7 : 5 Spartan-3E X485_06_021206 8 japan.xilinx.com XAPP485 (v1.1) 2006 11 10
R ( ) 7 Low High DCM 3.5 IOB 8 9 DCM_SP RXCLK35 RXCLK35 IOB FF MON RXCLK PSCLK PSEN PSINCDEC RXCLK35NOT SYSCLK CTLCLK PSDONE LOCKEDIN SYSRST RST auto_phase_align_se3 LOCKEDOUT X485_08_110306 8 : (after IOB sample) RXCLK35 Sample Point = 0 Extra delay inserted into the clock by the DCM when the phase value is incremented 9 : (RXCLK35) Sample Point = 0 X485_09_110606 (DCM ) 10 DCM (n 1 ) XAPP485 (v1.1) 2006 11 10 japan.xilinx.com 9
R (after IOB sample) RXCLK35 Sample Point = 0 Extra delay inserted into the clock by the DCM when the phase value is incremented Sample Point = 1 10 : 0 1 X485_10_110606 11 IOB (n 2 ) n 1 n 2 1 (after IOB sample) RXCLK35 Sample Point = 0 Extra delay inserted into the clock by the DCM when the phase value is incremented Sample Point = 1 11 : 0 1 2 X485_11_110606 Spartan-3E FPGA Spartan-3 FPGA ( ) Spartan-3E Spartan-3 Spartan-3E 25ps n 1 n 2 n 1 n 2 (n 3 ) LOCKEDOUT High 12 10 japan.xilinx.com XAPP485 (v1.1) 2006 11 10
R First edge found at value 59 (decimal) Second edge found at value 119 (decimal) DCM decrements to 90 (decimal) = (59+119)/2 X485_12_110306 12 : xapp485.zip n 1 n 2 n 3 BCD FPGA FPGA (BCD 50 ) PicoBlaze Spartan-3E FPGA 1:7 666Mbps ( 2 ) 2 : VQ TQ PQ CP FT FG -4 500Mbps 622Mbps -5 500Mbps 666Mbps XAPP485 (v1.1) 2006 11 10 japan.xilinx.com 11
R 2006/04/03 1.0 2006/11/10 1.1 8.2.03 12 japan.xilinx.com XAPP485 (v1.1) 2006 11 10