Application Report JAJA206 V+ R 5 V BIAS Q 6 Q R R 2 Q 2 Q 4 R 4 R 3 Q 3 V BIAS2 Q 5 R 6 V
Ω Q V GS + R Q 4 V+ Q 2 Q 3 + V BE V R 2 Q 5 R Op Amp + Q 6 V BE R 3 Q 7 R 4 R 2 A A 2 Buffer 2
± Ω Ω R G V+ Q.4.2 k = 0.35, T = 5.6ns Z OUT = re + R G + rb β(ω) β(o) β(ω) = ω + j ωβ ω ωβ = t β(o) Z OUT = re + R G + rb β(o) C L R L + j ω (R G + rb) ω t Relative Amplitude.0 0.8 0.6 0.4 0.2 0 k = 0.5, T =.9ns k = 0.44, T = 4.7ns 0 2 3 4 5 6 7 8 9 Time (ns) Z OUT = R EQ + j ω L EQ R O k = ( k 2 ) sin 2π ( /2 k2 ) [ 2 t T +cos 2π ( k 2 ) 2 t T ] e 2πk(t/T) R O Where: T = 2π (L EQ C L ) 2 R EQ k = + [ L EQ R L C L R G + rb R EQ = re + β(o) R G + rb L EQ = ωt ] T 4π T V V Cable Input V/2 V Received V/2 V/2 Reflected V/2 f T = GHz R G = 50Ω f T = 5GHz R G = 50Ω f T = 5GHz R G = 50Ω V rb = 50 rb = 50 rb = 50 T T re = 5 C L = 50pF re = 5 C L = 50pF re = 5 C L = 50pF β(o) = 00 β(o) = 00 β(o) = 00 k = 0.35 k = 0.44 k = 0.5 T = 5.6ns T = 4.7ns T =.9ns 3
V+ R 5 R 6 R 7 Q 4 Q 5 Q 8 Q 9 R 9 C C 2 Q 6 Q 7 To V To V +In Q 2 Pole-Zero Comp Q 3 Integrator Compensation Q 0 C 3 Q 4 R R 2 R 3 In Q R 0 Q 2 Q Q 5 V BIAS Q 3 R R 8 R 9 V µ µ 4
I I 2 V+ Case 2 Case Case ζ = 0.2 C2 Q 3 Aβ Case 2 ζ = 0.8 C A Q 4 f f 2 f 2 In Q Q 2 +In f Case G T Case 2 V G = β Aβ + Aβ e O (t) f Case A(ω) = A(o) ( + j ω ω ω ) ( + j ω 2 ) Pole Second Due to Pole Integrator Case 2 I I 2 V+ G = β G = β ω 2 ω + j + A(o) β ω ω 2 ω ω 2 ωn 2 ( + 2ζ ω ωn ) A(o) β ( ) ω 2 In Q R C A Q 2 +In where ωn = A(o) β ω ω 2 Step Response : ω ζ = + ω 2 2 A(o) β ω ω 2 t ζωnt e 0 (t) = e 0 (t) [ sin (ωn ζ2 t + cos ζ)] β ζ 2 G = β A(ω) = V Aβ + Aβ S A(o) ( + ω ' ) S S S ( + ω ) ( + ω ) ( + ω 0 ) 2-Pole Amplifier Pole-Zero Network 5
ω > ω ' A A ω < ω ' A A ω 0 ω ω 2 ω 0 ω ω 2 G = β A(ω) = ( Aβ + Aβ S + ω ) ( A(o) ) + S ω 2 ( ( ) + S ω S + ω 0 ) Tail e ( + Aβ) ω 0 ( ) t ω ' ω ω e ω t For simplicity assume A(o) ω 0 >> ω 2. ( A(o) + S ) ω A(ω) = ( ( S S + + ω ) ω 0 ) If ω ω : G = Step Response: e OUT e IN β (t) = Aβ + Aβ β ( Aβ + Aβ ( ) + S ω S + ω ) ( + S ( + Aβ) ω 0 [ ω ω e ω ω t e ( + Aβ) ω 0 t ] ) e OUT e IN (t) = β Aβ + Aβ e ( + Aβ) ω ω 0t [ ' ω e ] ω t ω 6
V+ R R 2 Q 4 Q 5 V BIAS Q 6 Q 0 R 8 In Q R 3 R 4 Q2 +In Q 7 R 9 Q Q 3 V BIAS Q 8 Q 9 C COMP V R BIAS 5 R 6 R 7 V V+ R 6 R R 3 R 4 R 5 R 9 R 0 Logic Out Q 6 R R 2 R 7 R 8 Q 5 Q 6 V BIAS Q 3 Q 4 Q 7 Q 8 Q 3 Q 4 Q 5 +In Q Q 2 In Q 9 Q Q 2 Q 0 I 5 To V+ I I 2 I 3 I 6 I 4 V 7
V+ Offset R R 2 0.4mV Q V 3 Q 4 BIAS 20µs Q Q 2 0 ma V At t < 0 At t > 0 Due to thermal time constant, temp. of Q and Q 2 doesn t change quickly. Temp Q2 = θ JA X P = 00 /W X 0.00W = 0. dv BE V BE = dt µ µ t Power in Q = 2mW Power in Q 2 = 0 Power in Q = Q 2 = mw X T = 2mV/ = 0.mV X 0. = 0.mV 8
C S Rg A A 2 A 3 A 4 G = G X G 2 X G 3 X G 4 = 7 X 7 X 7 X 35 = 2,000 82dB Bω/STAGE = 225MHz 82dB ØSHIFT = 4 X 45 = 80 70dB G T Loop Gain = Open Loop Gain Insertion Gain 00MHz 70dB 20 log 2π Rg f C S 0 f 225MHz 70dB 20 log 2π (300)(225 X 0 6 ) X (0. X 0 2 ) Phase ( φ ) 96 80 70dB 27dB = 43dB When φ = 0, oscillation occurs. f (Hz) 7 Gain* = R L re * 3rd Stage = R L 0.026 I V L = 0.026 Since the gain is proportional to I, a 43dB gain reduction occurs when: I @ Balance I @ Unbalance = 4 V BE = 26 ln I @ Balance I @ Unbalance Overdrive for 43dB gain reduction: V OVERDRIVE = 7 V BE 7 3 = 7 = 29mV 29 7 3 = 375µV V L A A 2 A 3 Q Q 2 V I R L V+ V O µ 9
V+ R 3 R R 2 V BIAS Q 7 Q 8 Q 5 Q 6 To Output Stage Q To Output Stage Q +In Q 3 Q 4 In I Q Q I 2 2 Latch Enable Q 9 Q 0 Latch Enable ( ) (+) I 3 V EFS e(t) = sin 2π ft 2 EFS = Full Scale ADC Range e IN d e(t) f EFS π cos 2π ft, dt d e(t) dt f = EFS π d e(t) dt f EFS π e OUT V e IN T/H e OUT Assume maximum allowable change during ADC conversion time. T = /2LSB and EFS = 2 N LSB where N is the number of bit ADC. fs /2LSB f = T 2 N = LSB π π 2 (N + ) T As an example, let N = 2 and T = µs: /2LSB f MAX = T 2 N = 38.9Hz LSB π With a sample/hold, the maximum frequency would be 500kHz. Fourier Transform of Output tf S T T V E O (f) = Ve j2πft dt = (e j2πft ) j2πf o o E O (f) E O (o) V = πf e j2πft 2j = VejπfT sin π ft πf = e jπft sin π ft π ft Ve jπft = πf (e jπft e jπft ) 2j Magnitude ( ) sin π f = e jπ(f/fs) fs ( πf ) fs Phase 0
0dB A(f) 3.9dB Input Signal Track/Hold Output fs/2 fs A(f) = sin π f fs π f fs Frequency Sampling Signal +5 5 Sampling Signal A ± On Off 0V 7.5V π π
V ON V OFF S V G G D C Allowed Error = X 0.0% = 0V X 0.0% = mv S G V GATE D C GD 0 7.5 C C GD V OFFSET = C + C GD A A Track Hold X V GATE, if C GD = 0.5pF C = 0.009µF V O V O V OFFSET Track µ µ 0.5 X 0 2 V OFFSET = 0.009 X 0 6 X 7.5 = mv +5V In V G + 5V C A V O +0 C A 7.5 5 X 0.5 X 0 2 V OFF = 0.009 X 0 6 = 0.83mV On Off V G 5V In V G 5V + C A V O R ON +0 C A 7.5 5 X 0.5 X 0 2 V OFF = 0.009 X 0 6 = 0.28mV Small Signal Bandwidth = 2π R ON C I = 2π (50) 0.009 X 0 6 = 354kHz Vt = 2.5 2
C DS R 2 R 3 0V V FEEDTHROUGH = = 7.5V C DS C + C DS V FT X C 0. X 0 2 A X 0 = µvp-p 0.009 X 0 6 2 + 0. X 0 Logic Input Q Q 2 R Logic Noise = Q 3 Logic Threshold Noise Density X = 50nV Hz BW D D 2 R 4 Q 4 To T/H Gate Circuits V X 300 X 0 6 = 0.87mV Logic Input Logic Output Threshold Noise Aperture Jitter = Logic Rate of Change = 0.87mV 0.4V/ns = 2.2ps Threshold Variation π π π 3
Input Input to Sample/Hold Sampling Signal Jitter Output Noise Input to Switch Driver Gate Signal Aperture Delay Input Sampling Signal Aperture Jitter Output Range of Outputs Due to Aperture Jitter Aperture Induced Noise = Signal Rate of Change Aperture Time = E FS π f t a = 4096 π 0 X 0 6 2.2 X 0 2 = 0.28LSB For f = 0MHz E FS = 2 2 t a = 2.2ps µ µ µ µ µ 4
+5 Q 3 +5V 5 C A V O Track/Hold Signal In R Q 6 747 6.8V V BIAS Q 2 V V GATE I D C I G A V O I D + I G S/H Output Sample Pulse Droop Rate = I C = I D + I G C = 50pA + 50pA 0.009µF = 0.0µV/µs µµ ± µµ V = I dt = C V I = t C C It I DSS I DSS I V O V DS V GATE 5
V 2 = 5 sin 2 π ft V Linear Settling Slew Rate = I DSS C Linear Response V = V 2 ( e ) t/r ON C = 25 X 0 3 = 2.8V/µs 0.009 X 0 6 de dt µ µ µ µ µ = V 2 e t/r ONC R ON C When de/dt = Slew Rate, response follows exponential: I DSS C Slew Time V 2 = R ON C Slew Time = Linear: V 2 = I DSS R ON = 25 X 0 3 X 50 =.25V (0.25) 2.8V/µs = 3.µs.249 =.25 ( e t/(50)(0.009 X 0 6 ) ).25 t = (50) (0.009 X 0 6 ) In = 3.2µs 0.00 Acquisition Time = Slew Time + Linear = 3. + 3.2 = 6.3µs Slew Rate = d dt = 5.2πf cos 2π ft Max Max f = Slew Rate (5) (2π) = 2.8V/µs 0π = 89.kHz π π π µ µ µ ± 6
± S Q D A C C 2 D Track/Hold Signal Q 2 S Q R S A C C SS C RSS C 2 Q 2 C RSS2 = V G C RSS C RSS C ( C RSS + C C ) 0.5 ( 450 ) = 7.5 (0.05 + 0.05) =.9mV V GATE 7
V C Q V G 300ns 424ns C A C 2 Q 2 µ R C R Q R/2 Q 2 C Sampling Signal (a) R C R R ON V O t = (2R ON + R)C (b) 8
µ Ω µ E Amplifier will slew until slew rate = T T = (2 R ON + R F ) C = (2 X 50 + 300) 60pF = 24ns 200V E = T X Slew Rate = 24 X 0 9 X 0 6 = 4.8V Acquisition Time = Feedthrough = 0.6Vp-p x Input E Slew Rate + T In E Error 0 4.8 4V = + 24ns In 200V/µs 0.00V = 26ns + 203ns + 229ns 0.pF 60pF Input Clamped by Diode Feedthrough Capacitance = mvp-p Feedback Capacitance Ω ± Ω ± 9
V+ I Q Q 2 R Buffer CR CR 2 High Speed Op Amp CR 3 CR 4 C A R 2 Q 3 Q 4 I V I I 2 V+ V V OFF = V G X (C D C D2 ) C = 2(0.025) 40 =.3mV V G C D C D2 V G C V OFF 20
V+ I Q Q 2 V G V G T V G2 V OFF Q 3 Q 4 V G2 C V V OFF = I 2 I x T C = 5 x 0 3 x 50 x 0 2 40 x 0 2 = 6.3mV µ µ R C V C V C2 R R/2 = Ve t/rc C 2 Track to Hold Settling C 3 = V ( e t/rc ) Track to Hold Settling 2
µ C C 5mA V FEEDTHROUGH = C 2(0.0) 40 R 200Ω R 2 200Ω E Amplifier will slew until slew rate = T T = 2π Bω = 2π 80 X 0 6 =.99ns = 0.5mV E = T Slew Rate =.99 X 0 9 300V/µs = 0.6V E Acquisition Time = Input E Slew Rate + T In Error 2 0.6 0.6 = +.99ns In 300V/µs 0.0002 = 4.7ns + 5.9ns = 20.6ns Full Power Bandwidth = Slew Rate (V PEAK )(2π) = 300V/µs ()(2π) = 47.7MHz Track/Hold T/H Gate V OFFSET T/H Gate Delay Line Comparator 22
± µ I OUT I OUT Bit Bit 2 Bit 3 Bit 4 Bit Bit 2 Q Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 V LOGIC REF 0mA 5mA 2.5mA.25mA 9.8µA 4.9µA V BIAS R R 2 R 3 R 4 23
V+ DAC Out 2R 2R 2R R I REF R R R R R Q Bit Bit 2 Bit 3 Bit Bit 2 Logic Ref R C R C R C R C R C R C V+ I REF I REF I OUT I = β + β ( ) I 2 = β + β I REF 2 I REF Q Bit Input Q 4 Q 5 V BE + I 2 R = V BE2 + I 3 R 2 If V BE = V BE2 and R = R 2, I I 4 Q 2 Q 3 + + V BE V BE2 I 2 I 3 R R 2 V V BIAS V BIAS I 2 = I 3 β I 4 = ( β + ) I 3 2 β I OUT = ( β + ) I 4 = β β I ( β + ) 3 = ( β + ) 2 2 β I OUT = ( β + ) I 2 = β β + ( β + ) ( β ) I OUT = I REF 2 I 2 2 I REF 24
Ω ± Ω I I 2 Input Output Q Q 2 C TE C TE C SUB C OB I Set Properly Q 3 I 3 I Set Too Low Circuit Fragment I = C V T = pf V ns = ma 25
V V 0 0.8.7 6.8 7.6 8.5 Q 8.8V Q 2 6.8V 8.V I kω I 2 0V V REF.3V Logic Reference 0.7VQ 3 V BIAS 5mA Transistor.25mA Transistor R.25mA 3.5V R = 3.5 0.7.25mA = 2.24kΩ V BIAS2 V BIAS Q 7 Q 3 Q 5 Q 4 Q 6 7.5V DAC Out R 4 250Ω 25Ω.25kΩ 25Ω 25Ω 25Ω R Q Q 2 Bit Bit 2 Bit 3 Bit 4 Bit N 5mA 2.5mA.25mA.25mA.25mA V BIAS3 R 2 R 3 5V 26
Ω Ω β β µ µ V+ V O I REF I β ± ± β Ω Q Q 4 V BIAS Q 2 Q 3 V+ R L = 250Ω V O R R 2 R OUT V DAC Error = R R + V RE B + 2 IR B = 0.5ppm/ + 0.36ppm/ + 0.47ppm/ V Q Q 2 I V BIAS R V 2 R OUT = β Q 2 On R OUT = Q 2 Off VA I = 50 200 0mA = 3MΩ =.33ppm/ V 27
Improper Connection R I = I + I 2 + I 3 + I 4 + + I 2 Resistance in Ground Line Proper Connection R 2R 2R 2R R R R I I 2 I 3 I 4 I 2 Offset for Single Current Source V MSB = R(I/2) + RI I I Offset for Multiple V MSB = R ( + R () I 2 2048 ) Current Source ± Ω ± Ω µ 28
V+ Q 3 Q 5 Q 4 V BIAS Q 6 R L C L R 4 R 0.0 Bias Q V REF C L Q 2 Digital Delay 0.0 R 2 R 3 Settling Time = Digital Delay + Ladder Response = 3ns + R L C L ln = 26ns ( V ) 0.0% = 3ns + (250Ω)(0pF) ln (+0.0%) DAC Out Data Skew Digital Input 0 Before Change During Glitch Data Skew 000 0000 0000 After Change 29
V P Data Skew V P R i (t) C Word 4 Word M Word M Word M + Word 3 e O (t) T Word 2 Word e O (t) = V P T R C t (T/R C) = (V P T) 2π f O e 2π f O t e O (t) dt = V P T RC RC ( e (T/RC) ) = V P T o o 234 Clock M M M + DAC Output Track/Hold Command Deglitched Output at Track/Hold Output Clock Counter ROM Glitch Register Clock DAC Hold Track DAC Track Hold Track Hold T/H Signal Filter 30
± Ref Analog V OFF R C M V OFF R C M + R Comparator Reference = V LADDER ± V OFF Analog Input Ref R R 2 R 3 R (2 M 2) R (2 M ) R (2 M ) +Ref Clock 2 Comparator Stages 2 M 2 2 M Linear to Binary Encoder Output Stages (Output Register) B B N B N 3
Q Ø Q 2 Ø2 V OFF V OFF π π CMOS Comparator Q 3 Ø2 A Digital Out Ω Ω Buffer R Flash Encoder 32
33 www.tij.co.jp µ µ µ Analog Input Digital Analog Converter Latches Shift Register Clock Convert Command Digital Output Comparator R R Analog Input Strobe Input +V REF Flash ADC Flash ADC
DAC = 2.20V Logic DAC Full Scale = 4.096V Comparator COMPARATOR DIGITAL TRIAL DAC INPUT OUTPUT 2.048 0.072 2 2.048 +.024 0.952 0 3 2.048 + 0.52 0.440 0 4 2.048 + 0.256 0.84 0 5 2.048 + 0.28 0.056 0 6 2.048 + 0.064 +0.008 7 2.2 + 0.032 0.024 0 8 2.2 + 0.06 0.008 0 9 2.2 + 0.008 +0.000 0 2.20 + 0.004 0.004 0 2.20 + 0.002 0.002 0 2 2.20 + 0.00 0.00 0 Analog In = 2.20V Digital Out 000 000 000 V O Start Bit Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 0 Bit Bit 2 DAC Comparator 34
DAC Analog Input DAC Output Comparator Output Analog % 0.% 0.0% Error Comparator µ 2.5 Input Accuracy (LSB) 2.0.5.0 0.5 Sub-Ranging Successive Approximation DAC DAC R Comparator Comparator V O V O 0.8.0.2.4.6.8 Conversion Time (µs) Input 35
µ e IN Sample and Hold MSB Flash Encoder M Bits DAC Amp LSB Flash Encoder L Bits Digital Error Corrector (Adder) Digital Output From S/H e IN MSB Flash Encoder DAC e IN + e m (Analog) + Amp LSB Flash Encoder Digital Error Corrector (Adder) Digital Output e IN + e m (Digital) System Input MSB Flash Out Input to LSB Flash Output from LSB Flash Digital Output e IN e IN + e m, e m = MSB Flash Error e IN (e IN + e m ) = e m e m + e d, e d = LSB Flash Error e IN + e m + ( e m + e d ) = e IN e d 36
Original Waveform Sampled Waveform dv Input dt Delay Line Strobe E n Aperture Jitter = dv dt Device Under Test E n Oscilloscope Comparator Integrator Device Under Test Test Signal Generator Strobe Digitally Programmable Delay R C Computer A DVM 37
Analog Input f 2 Sampling Signal f + f ADC 2 Register DAC Oscilloscope f Resampling Signal (f S + f) f S C Analog In ADC Under Test Digital Comparator R A Computer DVM (ANJ-057A) 38
IMPORTANT NOTICE 200.