BIST LSI LSI LSI (DDP) BIST Ring-STP (BIST) BIST LSI e-shuttle 65nm 12Layer CMOS Cadence Verilog-XL 100MHz 16M Packet/sec LSI 5 1 BIST i

20 BIST LSI LSI Implementation of Self-Timed Ultra High Speed BIST Circuit 1090384 2009 3 5

BIST LSI LSI LSI (DDP) BIST Ring-STP (BIST) BIST LSI e-shuttle 65nm 12Layer CMOS Cadence Verilog-XL 100MHz 16M Packet/sec LSI 5 1 BIST i

Abstract LSI Implementation of Self-Timed Ultra High Speed BIST Circuit Hiroki MIYAMOTO Recently, a large scale and speed-up of LSI has been accelerated rapidly. However, power consumption is increased making to a large scale and speeding up, and the growing difficulty of complication and the operation verification of the design is generated. The major cause is synchronous architecture that operates based on global area clock signals. On the other hand, the Data-Driven Processor (DDP) can reduce power consumption, and the design can be localized. Because global area clock signals are not used. However, even if the Self-Timed Pipeline is used, the growing difficulty of the operation verification cannot be reduced. In a clock synchronous circuit, the operation verification has been simplified as a Design for Testability(DFT). On the other hand, DFT cannot be used with STP. In this dissertation, the main suggestion is the circuit design of the Built-in Self- Test(BIST) for the Self-Timed Pipeline. In addition, the evaluations of effectiveness are evaluated by the simulation. The library used for the simulation is e-shuttle 65nm 12Layer CMOS standard cell library. In addition, the simulator used Verilog-XL of the Cadence Design Systems. The results of the simulation when the circuit operated at 100MHz is 16M Packet/sec. Moreover, the circuit size was about 1/5 of the LSI. key words Self-Timed Pipeline, DDP, DFT, BIST ii

1 1 2 4 2.1...................................... 4 2.2....................... 4 2.2.1............................ 4 2.2.2 STP............................. 6 2.3.............................. 8 2.3.1............................ 8 2.3.2 BIST................................. 9 2.4............... 10 2.5...................................... 11 3 BIST 12 3.1...................................... 12 3.2................................. 12 3.3 BIST................................... 13 3.3.1 Generator............................. 13 3.3.2 Comparator............................ 17 3.3.3 STPFIFO............................. 19 3.4 LSI................................... 20 3.5...................................... 21 4 22 4.1...................................... 22 iii

4.2................................ 22 4.3................................... 23 4.4................................... 24 4.5................................... 24 4.6...................................... 26 5 27 30 31 iv

1.1...................... 1 2.1 STP.................................. 5 2.2 STP.......................... 6 2.3 DDMP................................. 7 2.4................................ 8 2.5 BIST...................................... 9 3.1................................. 12 3.2 BIST.................................... 14 3.3 Generator................................. 15 3.4 VHS............................ 16 3.5 VD................................... 16 3.6 Comparator................................ 17 3.7 POWERLOAD................................ 18 3.8 STPFIFO............................... 19 3.9 LSI............................. 20 4.1 (Generator)...................... 23 4.2 (Comparator)..................... 23 v

4.1 ( )........................... 24 4.2 ( ).......................... 25 4.3 ( )............................... 25 vi

1 LSI 1970 2000 LSI 1.1 1970 LSI 400kHz 2,300 3GHz 8 Transistors Frequency 1.1 I. II. III. I. [1] II. LSI System On a 1

Chip(SoC) LSI LSI III. 2. SoC LSI (Self- Timed Pipeline : STP) [2] [3] STP (SEND ) (ACK ) ( ) STP [4] STP LSI [5] (Built-In Self Test : BIST) LSI ( ) LSI BIST LSI 2 2

STP BIST BIST BIST 5 2 BIST 3 BIST 4 BIST 5 3

2 2.1 STP STP LSI LSI STP BIST BIST STP 2.2 2.2.1 STP SEND ACK STP 2.1 4

2.2 Pipeline Stage Packet DLi-1 Logic Logic DLi Logic Logic DLi+1 SENDi-1 SENDi SENDi+1 SENDi+2 ACKi-1 Ci-1 ACKi Ci ACKi+1 Ci+1 ACKi+2 Master Reset DL : Data Latch C : C-element 2.1 STP STP 2.1 (DL) Logic DL (C : C-element) 2.1 DL Logic C Logic 2.2 Master Reset C ACK 1. C C i C i 1 SEND C i+1 ACK DL CK 2. DL i DL i 1 DL i 3. C i C i 1 ACK C i+1 SEND 4. SEND 5

2.2 Master Reset (0) SEND0 (1) ACK0 To DL1 SEND1 (2) (3) (4) ACK1 To DL2 SEND2 (3) (2) (4) 2.2 STP ACK DL STP 2.2.2 STP DDMP DDMP 2.3 (Ring) (M : Merge) STP MM 6

2.2 M MM M : Merge MM : Matching Memory ALU : Arithmetic Logic Unit PS : Program Storage B : Branch ALU B PS 2.3 DDMP (MM : Matching Memory) M ALU (ALU: Arithmetic Logic Unit) MM PS (PS : Program Storage) DDMP ALU B (B : Branch) DDMP 60 STP 7

2.3 2.3 (Design For Testability : DFT) DFT (Built-In Self Test : BIST) BIST 2.3.1 2.4 LSI Clock Circuit FF FF FF FF FF Parameter Scan Circuit Result FF : Scan Flip-Flop 2.4 8

2.3 LSI (Circuit) (FF) (Scan Circuit) LSI (Clock) (Parameter) Result LSI BIST BIST 2.3.2 BIST BIST 2.5 LSI Circuit BIST Pattern Pattern Parameter Test Pattern Generator Test Pattern Validator Result 2.5 BIST 9

2.4 LSI (Circuit) BIST (BIST) LSI LSI (TestPattern Generator) (Test Pattern Validator) BIST (Test Pattern Validator) LSI 2.4 STP STP STP LSI BIST BIST BIST 10

2.5 2.5 DDMP BIST 2 BIST BIST BIST LSI 11

3 BIST 3.1 STP LSI LSI 3.2 3.1 CORE Mode BIST RING Interval BISTGEN 40 Stage Ring-STP Result BISTCOMP V DDB V DDC V min V SS V DDO (for I/O) 3.1 12

3.3 BIST BIST BIST RING RING : 40 Ring-STP Logic : ( 1 ) : LSI MODE Interval BIST 3.3 BIST BIST 3.2 BIST 2 BIST 3 Generator Comparator STPFIFO Generator Comparator STPFIFO Generator Comparator STPFIFO 3.3.1 Generator Generator 3.3 VHS(Virtual Hand-Shake) M (M-series Generator) (C : C-element) STPFIFO 13

3.3 BIST BIST Generator STPFIFO 40 packets RING M-series Generator DL DL VHS C C C VD STPFIFO SEND ACK Comparator 40 results DL DL Compare Matching C C C STPFIFO VHS : Virtual Hand-Shake DL : Data Latch C: C-element VD : Variable Delay SEND ACK 3.2 BIST (VD : Variable Delay) LSI (CLK) (STARTKEY) (COUNTKEY) (INTERVAL) VHS M-series Generator C VD (C : C-element) C DL DL C C SEND ACK DL M (M-series Generator) 14

3.3 BIST STPFIFO 40 packets INTERVAL M-series Generator DL DL 194 CLK COUNTKEY STARTKEY RESET VHS C C C VD SEND ACK VHS : Virtual Hand-Shake DL : Data Latch C: C-element VD : Variable Delay CLK : Clock 3.3 Generator BIST 2 LSI M (Maximal-Length Sequences/M-Series) (LFSR) (VHS : Virtual Hand-Shake) STP BIST M M 1 (VHS : Virtual Hand-Shake) STP 3.4 (SINI) STARTKEY STARTKEY SEND (SSA) ACK (SWAA) ACK SEND (SSN) ACK (SWAN) ACK Completion 15

3.3 BIST Not STARTKEY Assert SINI STARTKEY Assert SSA SEND Assert SWAA Not ACK Assert Send Completion ACK Assert SCOM ACK Negate SWAN SEND Negate SSN Not ACK Negate SINI : Initial SSA : SEND Assertion SWAA : Wait ACK Assertion SSN : SEND Negation SWAN : Wait ACK Negation SCOM : Send Completion 3.4 VHS (SCOM) (VD : Variable Delay) INTERVAL IN OUT D MUX D MUX D MUX 3.5 VD CPU STP 16

3.3 BIST (VD) 3.5 MUX INTERVAL 3.3.2 Comparator Generator 3.6 194 From Generator STPFIFO 40 results PL Result DL DL Compare Matching From RING 194 C C C SEND ACK DL : Data Latch C : C-element PL : POWERLOAD 3.6 Comparator Generator (PL : POW- ERLOAD) Generator RING (Matching) Generator RING (Compare) STPFIFO LSI 17

3.3 BIST Result PL Matching Compare (PL : POWERLOAD) Packet 192 GD ADDER 16 16 Packet 192 GD : Gray code Decoder 3.7 POWERLOAD RING 1 BIST POWERLOAD 3.7 (GD) 40 (ADDER) RING 194bit RING 192bit 12 3.7 16bit (Matching) 18

3.3 BIST RING BIST Generator RING Generator (Compare) RING Generator (Result ) 3.3.3 STPFIFO STPFIFO 3.8 40 Packets Packet DL DL DL Packet 194 or 1 194 or 1 SEND C C DL : Data Latch C: C-element C ACK 3.8 STPFIFO STPFIFO (DL) (C) FIFO(First In, First Out) STPFIFO C STPFIFO BIST STPFIFO STPFIFO 19

3.4 LSI 194bit 1bit (DL) STPFIFO 3.4 LSI BIST RING LSI 3.9 Generator BIST Comparator 3.9 LSI BIST 3.9 BIST Generator Comparator 20

3.5 3.5 BIST BIST LSI RING BIST BIST 21

4 4.1 BIST LSI BIST BIST BIST 4.2 LSI : Cadence Verilog-XL : 1ps : e-shuttle 65nm 12Layer CMOS : Synopsys Astro : Synopsys Design Compiler 22

4.3 4.3 BIST Generator Comparator 4.1 4.2 4.1 Generator 4.2 Comparator Generator 2 Comparator 1 Set Hand Shake 4.1 (Generator) Result 4.2 (Comparator) 4.1 (Set) STARTKEY Generator 2 4.2 RING BIST Generator Comparator 23

4.4 4.4 4.1 6 3 Generator 6 6 100MHz Generator 17M packet/sec 4.5 4.3-4.2 4.1 ( ) (µm 2 ) Generator 39311.28 Comparator 6195.6 STPFIFO 42027.48 4.1 4.2 4.3 STPFIFO 4.3 BIST Generator Comparator STPFIFO STPFIFO 24

4.5 4.2 ( ) (µm 2 ) Generator 88646.40 Comparator 7879.68 STPFIFO 78796.80 4.3 ( ) Generator 9961 M 280 STPFIFO 9345 336 Comparator 3073 Matching 448 STPFIFO 1526 Compare 257 STPFIFO 9345 16 BIST 22395 Generator Comparator STPFIFO STPFIFO 194bit 1bit 3 1 STPFIFO 4.2 BIST 4 1 4.3 10 1 25

4.6 4.6 BIST BIST 100MHz 17M packet/sec 6 /packet STPFIFO STPFIFO BIST 4 1 10 1 26

5 LSI STP STP STP BIST BIST STP STP BIST LSI BIST 3 Generator Generator RING Comparator Generator Comparator STPFIFO Generetor BIST 100MHz 17M packet/sec 6 27

/packet STPFIFO STPFIFO BIST 4 1 10 1 LSI LSI 4 1 BIST LSI BIST BIST STPFIFO 4.4 STPFIFO RING RING STPFIFO CPU BIST STPFIFO Generator STPFIFO RING BIST RING BIST STPFIFO BIST LSI BIST RING 1 M RING RING 28

100MHz 17M packet/sec 6 /packet STP DDMP LSI BIST LSI LSI LSI LSI LSI STP STP 29

, LSI., 1 JST/CREST 3 30

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