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4... 4... 4... 5 6... 6... 6 isplever... 6... 7... 8... 8... 8 (NCD)... 9 (.vcd)... 10... 11...11... 12 Power Summary... 16 Logic Block... 19 Clocks... 20 I/O... 20 I/O Term... 21 Block RAM... 22 DSP... 24 PLL/DLL/DQSDLL... 24 MACO... 25 SERDES... 25 Graph... 27 Report... 28 30 Appendix 31 Activity Factor... 31 EBR()Activity Factor... 31 VCD (Value Change Dump)... 32 2
JA... 33 35 3
Sep.2008 3 2 1 isplever 1 Web Power Model NCD TWR Power Calculator Device database VCD (AF) PEP RPT.PEP ;.PER ; 1-1 4
1. Estimation 2. Calculation NCD (AF: Activity Factor) 3. Calculation VCD 1-1 Estimation Calculation NCD NCD NCD NCD TWR VCD (AF) TWR VCD 5
LatticeECP/EC, LatticeECP2/M, LatticeXP, LatticeXP2, MachXO, LatticeSC/M isplever isplever isplever isplever (Project Navigator) 2-1 (Project Navigator isplever Project Navigator ) 2-1 isplever(project Navigator) [Tool] []( ) 2-2 6
2-2 Windows [] => [] => [Lattice Semiconductor] => [Accessories] [] 2-2 2-3 7
NCD (NCD isplever ) [File] [New ]( ) 2-4 2-4 New Project Project Name: Project Directory: NCD File: NCD (Power Project File:.pep) (Power Project File:.pep) [File] [Open Project]( 2-5 ) 8
2-5 (NCD) FPGA (NCD: native circuit description) (NCD isplever ) NCD 1. [File] [Open Design File ] 2. 2-6 NCD 2-6 NCD 9
3. NCD NCD (NCD ) (.vcd) (.vcd: value change dump) Frequency AF% (Activity Factor) AF (vcd isplever ).vcd 1. [File] [Open Simulation File ] 2. 2-7.vcd 2-7.vcd 3..vcd Module Name in VCD:.vcd Frequency AF% 4. Case Sensitive.vcd 5..vcd AF%.vcd Frequency AF% 6. (.vcd AF% ) 10
2-8 2-8 NCD NCD NCD NCD Software Mode: Estimation NCD Calculation 8 11
3 [Edit] 2-9 Activity Factor Settings (%): 2-10 Activity Factor Settings 12
Frequency Settings: (.twr) Frequency (.twr isplever Power Calculator ) 2-11 Frequency Settings Frequency Default (MHz): Use TWR: (.twr) Frequency Minimum of Preference And Trace: Trace Report (.twr).twr Actual Frequency.twr Always Use Preference: Trace Report (.twr).twr Always Use Trace: Trace Report (.twr).twr Actual Frequency.twr 13
Estimation Mode: Estimation Medium Low High Medium 2-12 Estimation Mode Setting Graph Setting: XY Power vs. VCC Supply Voltage Power vs. Ambient TemperaturePower vs. Frequency 3 typical worst case 2 Power by Section: Y Total Power Logic Block Total Power X VCC Lower Limit Upper Limit X Resolution Lower Limit Upper Limit Nominal +/-5% Lower Limit 1.1628 Upper Limit 1.2348 Resolution 0.0144 Resolution Power by Temperature: Y Total Power Logic Block Total Power X Ambient Temperature FPGA Lower Limit Upper Limit X Resolution Lower Limit Upper Limit FPGA Resolution 10 Lower Limit -10 Upper Limit 100 Resolution 22 Resolution 14
Power by Frequency: Y Total Power Logic Block Total Power X No Clocks Found! Lower Limit Upper Limit X Resolution Lower Limit 0MHz Upper Limit 10000MHz Lower Limit 10MHz Upper Limit 100MHz Resolution 20 Resolution 2-13 Graph Settings 15
Power Summary 2-14 Power Summary Power Summary Family: SC, ECP2M Device: LFE2M35E Package Type: Speed Grade: Operating Condition: Part Name: Process Type Typical Worst 16
Power Summary Environment Ambient Temperature FPGA Thermal Profile 2-15Thermal Profile 2-15 Thermal Profile Use Thermal Models Board Selection: JEDEC Board (2S2P) JEDEC JEDEC 27mm 3 x 3 27mm 4 x 4 Theta JA (Junction-to-Ambient) Theta JC (Junction-to-Case) Theta JC Theta JA Small Board 68 x 68 Theta JB Medium Board 812 x 812 Theta JB Large Board 14 x 14 Theta JB 17
Heat Sink Selection: No Heat Sink Theta JA Airflow Selection No Heat Sink Low-Profile Heat Sink 12mm Medium-Profile Heat Sink 21mm High-Profile Heat Sink 25mm Custom-Profile Heat Sink Enter Theta-SA For Custom Heat Sink Theta SA Theta SA Airflow Selection: FPGA LFM (Linear Feet per Minute)0 LFM (0 m/s), 200 LFM (1 m/s), 500 LFM (2.5 m/s) 3 Custom-Profile Heat Sink Effective Theta JA Theta JA User Defined Theta JA Effective Effective Theta JA Use Thermal Models Thermal Profile Power Summary Environment Effective Theta JA, Junction Temperature, Maximum Safe Ambient Typical VCC121.2V I/O DC NCD FPGA (In-Rush Current) SC/M 18
Logic Block 2-16 Logic Block Logic Block Clock Name: Freq. (MHz): AF (%): 10% # Logic LUTs: LUT # Dist RAM Slices: # Ripple Slices: # Registers: F/F Dyn. Pwr(W): Total Dynamic Power: NCD Row Row Add Row Row Logic Block Row Row Add Row XXXX XXXX Row 2-17 Row 19
Clocks 2-18 Clock Clocks I/O 2-19 I/O I/O Clock Name: Type: I/O Register: Freq. (MHz): AF (%): Input Freq. (MHz): Input AF (%): Output Freq. (MHz): Output AF (%): # I/P: I/O # I/P # O/P # Bidi LVCMOS _8 (ma) I/O 20
# O/P: # Bidi: Duty Cycle (%): I/O Cload (pf): Dyn. Pwr(W): Total Dynamic Power: I/O I/O Term 2-20 I/O Term Type: I/O # I/P: I/O # O/P: I/O # Bidi: I/O Duty Cycle (%): I/O Rth (Ohm): Vth (V): Termination Power(W): Total Termination Power(W): I/O 21
Block RAM 2-21 Block RAM SP RAM: Single Port RAM Clock Name: # EBR Blocks: EBR Freq. (MHz): AF (%): Dyn. Pwr(W): 2-22 Single Port RAM 22
DP RAM: Pseudo Dual Port RAM Rd Clock Name: Rd Clk Freq. (MHz): Rd AF (%): # EBR Blocks: EBR Wr Clock Name: Wr Clk Freq. (MHz): Wr AF (%): Dyn. Pwr(W): 2-23 Pseudo Dual Port RAM DP RAM True: True Dual Port RAM Clock A Name: A CLK A Freq. (MHz): A CLK A Rd AF (%): A CLK A Wr AF (%): A # EBR Blocks: EBR Clock B Name: B CLK B Freq. (MHz): B CLK B Rd AF (%): B CLK B Wr AF (%): B Dyn. Pwr(W): 2-24 True Dual Port RAM Total Dynamic Power: EBR 23
DSP 2-25 DSP Clock Name: DSP Freq. (MHz): DSP AF (%): DSP Type: DSP Dyn. Pwr(W): Total Dynamic Power: DSP PLL/DLL/DQSDLL 2-26 PLL/DLL/DQSDLL PLL/DLL Clock Name: Freq. (MHz): PLL/DLL/DQSDLL: PLL/DLL/DQSDLL Dyn. Pwr(W): Total Dynamic Power: PLL/DLL/DQSDLL 24
MACO MACO SCM 2-27 MACO Clock Name: MACO Freq. (MHz): MACO AF (%): MACO Type: MACO MACO: MACO Dyn. Pwr(W): Total Dynamic Power: MACO SERDES SERDES ECP2M SC/M ECP2M SC/M 2-28 2-29 2-28 SERDES (ECP2M) ECP2M Clock Name: SERDES Freq. (MHz): SERDES #Channels: SERDES Mode: SERDES Dyn. Pwr(W): Total Dynamic Power: SERDES 25
2-29 SERDES (SC/M) SC/M Clock Name: SERDES Freq. (MHz): SERDES #Channels: SERDES Gearing Ratio: SERDES TX Pre-emphasis: TX Dyn. Pwr(W): Total Dynamic Power: SERDES 26
Graph 2-30 Edit Graph Settings 14 2-31 Graph 27
Report 2-32 2-33 2-32 Reports (1) 28
2-33 Reports (2) 29
Reports View HTML Report 2-34 HTML 2-34 HTML Help [Help] Help 30
Appendix Activity Factor AF (Activity Factor, AF 100% AF 50% AF PFUI/O 15% 25% EBR() Activity Factor 31
VCD (Value Change Dump) ALDEC Active-HDL VCD VCD IEEE 1364 Verilog Verilog VCD Active-HDL Verilog VHDL Active-HDL VCD VHDL, Verilog, VCD VCD # Generate VCD file vcd file output.vcd : VCD vcd add -r /top_testbench/top/* : VCD -r /top_testbench/top/* Active-HDL ModelSim VCD isplever Classic isplever Starter Active-HDL Lattice Web Edition VCD VCD VCD VCD 32
JA JAsmall board JAThermal Profile Thermal Profile 33
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5-1 Ver1.0 2007/09 Ver1.1 2008/02 isplever7.0 sp2 PLL M, N, V Ver1.2 2008/03 Board Selection Heat sink Section Air flow m/s VCD Ver1.3 2008/06 isplever7.1 2008/09 isplever7.1 SP01 ThetaJA 35