N conf N prog N input (1) T eva T eva T sim N conf N prog N input (1) T sim 2.2 T sim 1),17) 3),9),11),13) 10),12),14),19) Eeckh
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- れんま ふくだ
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1 Vol. 52 No (Dec. 2011) 1, 2, Reusing Simulation Results for Cache Miss Rate Prediction Takatsugu Ono, 1, 2, 1 Koji Inoue 3 and Kazuaki Murakami 3 This paper proposes cache miss rate prediction technique reusing simulation results. In order to determine the best cache configuration, designers have to evaluate many cache configurations with many benchmark programs and its input data sets. Similar memory access patterns appear in different input data sets of the same program. We can expect almost the same simulation results if the patterns are similar. However, a conventional approach has to simulate the similar patterns. In this paper, we attempt to predict cache miss rate by means of reusing simulation results and the similarity of memory access patterns. In our evaluation, it is observed that the proposed approach is able to predict the cache miss rate in high accuracy ) 1 1 Graduate School of Information Science and Electrical Engineering, Kyushu University 2 Research Fellow of the Japan Society for the Promotion of Science 3 Faculty of Information Science and Electrical Engineering, Kyushu University 1 Presently with FUJITSU LABORATORIES LTD c 2011 Information Processing Society of Japan
2 N conf N prog N input (1) T eva T eva T sim N conf N prog N input (1) T sim 2.2 T sim 1),17) 3),9),11),13) 10),12),14),19) Eeckhout 4) (1) T input 20 PCA Principal Components Analysis Zhong 20) T input reuse distance 2) Zhong N conf Mattson 1 8) Hill Mattson 1 6) (1) T sim N conf T sim 1 N conf Hoste 7) Hoste Hoste
3 Fig. 1 Database generation phase Fig. 2 Cache miss rate prediction phase
4 Fig. 3 Memory access characterization V Tt V Dt S s (2) E 2 S s S s = 1 E(V Tt,V Dt ) 1 2 V Tt (2)
5 3176 V Tt i V Dt V Dt i n S l (3) S l = 1 n i=0 E(VT t i,vd t i ) (3) n =1 1 n cmr (4) p miss access p miss i access i i p miss access 1M access 1M interval (4) ( interval ) p miss i=1 i cmr = interval 100 (4) access i=1 i L (4) A B (5) r s r s =1 6 c i=1 d2 i (5) c 3 c c d i r s T conv (1) (6) T conv = T sim eva N input p N conf (6) T sim eva N input p T r (7) T r = T db + T p (7) T db T p T db T p (8) (9) T db = T e db + T sim db N conf (8) T p =(T e p + T ref ) N input p (9) T e db T e p T sim db T ref T r <T conv (6) (7) T sim db <T sim eva N input p T e db +(T e p + T ref ) N input p N conf N input p =1 (10)
6 3177 T sim db <T sim eva (10) L1 ARM MiBench 5) 22 SPEC ) 2 MiBench small large 2 small large (10) 5) small large small large 1 1 SPEC2000 TEST TRAIN TEST TRAIN 200 M 1G 1 4 SimpleScalar 15) LRU 1 Table 1 The number of load and store instructions. adpcm enc 100,225,935 5,163,299 adpcm dec 100,225,934 5,163,298 bitcount 183,398,225 12,244,947 blowfish enc 388,428,071 37,357,266 blowfish dec 388,428,173 37,357,368 crc32 984,771,274 50,664,607 dijkstra 117,292,392 26,984,841 ghostscript 377,061, ,562,633 ispell 443,500,551 4,528,209 jpeg enc 39,215,368 10,474,944 jpeg dec 11,170,434 3,011,954 lame 631,310,799 51,913,283 mad 111,406,837 9,367,397 patricia 257,227,891 41,837,353 rijndael enc 183,336,669 17,613,572 rijndael dec 172,151,637 16,539,079 rsynth 479,539,354 33,077,063 sha 36,587,102 3,522,046 tiff2bw 58,298,542 14,176,275 tiff2rgba 101,512,239 24,635,729 tiffdither 258,000,394 85,607,511 tiffmedian 207,312,939 56,940, vpr 308,508,083 61,243, art 278,327,002 55,987,182 1M (2) 16 B 32 B 64 B 128 B 256 B 512 B 1,024 B 32 B
7 small large Fig. 4 Cache miss rate of small and large input data. Fig. 5 5 Cache miss rate prediction accuracy of all programs. 2 Table 2 Cache configuration. B KB B 4KB 4 jpeg enc jpeg dec tiff2rgba tiffmedian 179.art rijndael enc 6 rijndael enc Fig. 6 Cache miss rate prediction accuracy of all cache configurations (rijndael enc). 6 x y z 16 B 32 B
8 tiffdither lame patricia rijndael enc jpeg enc tiffmedian tiffdither lame 2 8 patricia rijndael enc jpeg enc tiffmedian 7 tiffmedian Fig. 7 Cache miss rate prediction accuracy of all cache configurations (tiffmedian). 64 B 5 tiffmedian jpeg enc tiffmedian (3) n=1 jpeg enc tiffmedian tiffmedian 7 9 bitcount 0%
9 3180 Fig. 9 9 Spearman rank-correlation coefficients in each programs. Fig Relation between the number of cache configurations and prediction time. Fig. 8 8 Relation between similarity and error. bitcount T conv T p tiff2bw large small T sim eva T sim db tiff2bw small large ) (10) SimpleScalar sim-cache sim-cache 1 T p (9) N conf
10 Fig. 11 Relation between the number of inputs and prediction time. T e p sim-cache T sim eva T e p 5 6 tiff2bw 11 T conv T r T sim eva T sim db tiff2bw (10) 1 N conf large T sim eva small T sim db T sim eva (10) T r T conv T sim db tiff2bw NEDO ) Chiou, D., Sunwoo, D., Kim, J., Patil, N.A., Reinhart, W., Johnson, D.E., Keefe, J. and Angepat, H.: FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators, MICRO 07: Proc. 40th Annual IEEE/ACM International Symposium on Microarchitecture, pp , IEEE Computer Society, Washington, DC, USA (online), DOI: (2007). 2) Ding, C. and Zhong, Y.: Predicting whole-program locality through reuse distance analysis, PLDI 03: Proc. ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation, pp , ACM, New York, NY, USA (online), DOI: (2003). 3) Eeckhout, L., Bell, R.H., Jr., Stougie, B., Bosschere, K.D. and John, L.K.: Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor De-
11 3182 sign Studies, ISCA 04: Proc. 31st Annual International Symposium on Computer Architecture, p.350, IEEE Computer Society, Washington, DC, USA (2004). 4) Eeckhout, L., Vandierendonck, H. and Bosschere, K.D.: Workload Design: Selecting Representative Program-Input Pairs, PACT 02: Proc International Conference on Parallel Architectures and Compilation Techniques, pp.83 94, IEEE Computer Society, Washington, DC, USA (2002). 5) Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T. and Brown, R.B.: MiBench: A free, commercially representative embedded benchmark suite, IEEE 4th Annual Workshop on Workload Characterization (Dec. 2001). 6) Hill, M.D. and Smith, A.J.: Evaluating Associativity in CPU Caches, IEEE Trans. Comput., Vol.38, No.12, pp (online), DOI: (1989). 7) Hoste, K., Phansalkar, A., Eeckhout, L., Georges, A., John, L.K. and Bosschere, K.D.: Performance prediction based on inherent program similarity, PACT 06: Proc. 15th International Conference on Parallel Architectures and Compilation Techniques, pp , ACM, New York, NY, USA (online), DOI: (2006). 8) Mattson, R.L., Gecsei, J., Slutz, D.R. and Traiger, I.L.: Evaluation Techniques for Storage Hierarchies, IBM System Journal, Vol.9, No.2, pp (1970). 9) Nussbaum, S. and Smith, J.E.: Modeling Superscalar Processors via Statistical Simulation, PACT 01: Proc International Conference on Parallel Architectures and Compilation Techniques, pp.15 24, IEEE Computer Society, Washington, DC, USA (2001). 10) Vol.48, No.19, pp (2007). 11) Oskin, M., Chong, F.T. and Farrens, M.: HLS: Combining statistical and symbolic simulation to guide microprocessor designs, ISCA 00: Proc. 27th Annual International Symposium on Computer Architecture, pp.71 82, ACM, New York, NY, USA (online), DOI: (2000). 12) Patil, H., Cohn, R., Charney, M., Kapoor, R., Sun, A. and Karunanidhi, A.: Pinpointing Representative Portions of Large Intel R Itanium R Programs with Dynamic Instrumentation, MICRO 37: Proc. 37th Annual IEEE/ACM International Symposium on Microarchitecture, pp.81 92, IEEE Computer Society, Washington, DC, USA (online), DOI: (2004). 13) Robert, H., Bell, J. and John, L.K.: Improved Automatic Testcase Synthesis for Performance Model Validation, ICS 05: Proc. 19th Annual International Conference on Supercomputing, pp , ACM Press, New York, NY, USA (online), DOI: (2005). 14) Sherwood, T., Perelman, E., Hamerly, G. and Calder, B.: Automatically Characterizing Large Scale Program Behavior, ASPLOS-X: Proc. 10th International Conference on Architectural Support for Programming Languages and Operating Systems, pp.45 57, ACM Press, New York, NY, USA (online), DOI: (2002). 15) SimpleScalar Simulation Tools for Microprocessor and System Evaluation, available from 16) SPEC, available from 17) Vol.46, No.12, pp (2005). 18) Wilton, S.J.E. and Jouppi, N.P.: Cacti: An Enhanced Cache Access and Cycle Time Model, IEEE Journal of Solid-State Circuits, Vol.31, pp (1996). 19) Wunderlich, R.E., Wenisch, T.F., Falsafi, B. and Hoe, J.C.: SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling., Proc. 30th International Symposium on Computer Architecture, pp (2003). 20) Zhong, Y., Dropsho, S.G. and Ding, C.: Miss Rate Prediction across All Program Inputs, PACT 03: Proc. 12th International Conference on Parallel Architectures and Compilation Techniques, p.79, IEEE Computer Society, Washington, DC, USA (2003). ( ) ( ) PD 22 IEEE
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