Vol.-ARC-8 No.8 Vol.-OS- No.8 // DRAM DRAM DRAM DRAM ) DRAM. DRAM. ) DRAM DRAM DRAM DRAM DRAM SRAM DRAM MB B MB DRAM SRAM.. DRAM DRAM SRAM DRAM SRAM C

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1 IPSJ SIG Technical Report Vol.-ARC-8 No.8 Vol.-OS- No.8 // DRAM- DRAM DRAM DRAM % % On-Chip Memory Architecture for DRAM Stacking Microprocessors SHINYA HASHIGUCHI, TAKATSUGU ONO, KOJI INOUE and KAZUAKI MURAKAMI In this paper, we propose a new architecture that can achieve high memory performance without large footprint overhead for DRAM-stacked processors. D stacked DRAM caches can dramatically reduce off chip memory accesses. However, this approach degrades performance in some cases because increasing cache size makes access time longer to solve this problems. Our approach selectively leverages the stacked DRAM cache based on the valiation of working set sizes. The results of our quantitative evaluation showed that the proposed approach achieves % of memory performance gain in static control method and % in dynamic control method.. SI SI DRAM DRAM TSV Through Silicon Via ))) SI TSV ) DRAM DRAM DRAM SRAM DRAM MB DRAM DRAM 8- Graduate School of Information Science and Electrical Engineering, Kyushu University Motooka Nishi-ku Fukuoka 8- JAPAN s-hashiguchi,ono@c.csce.kyush-u.ac.jp 8- Faculty of Information Science and Electrical Engineering, Kyushu University Motooka Nishi-ku Fukuoka 8- JAPAN inoue,murakami@i.csce.kyush-u.ac.jp c Information Processing Society of Japan

2 Vol.-ARC-8 No.8 Vol.-OS- No.8 // DRAM DRAM DRAM DRAM ) DRAM. DRAM. ) DRAM DRAM DRAM DRAM DRAM SRAM DRAM MB B MB DRAM SRAM.. DRAM DRAM SRAM DRAM SRAM Cache SRAM Core ベースプロセッサ ( 次元実装 ) TagRAM SRAM DataCache DRAM Core DRAM スタック法 ( 次元実装 ) DRAM DRAM DRAM DRAM DRAM AMAT Average Memory Access Time AMAT [cycles] = HT + MR (HT + MR MMAT ) () HT /HT / [cycles] MR /MR / MMAT [cycles] DRAM HT MR MMAT HT MR HT BASE MR BASE DRAM HT DRAM MR DRAM HT BASE HT DRAM, MR BASE HT DRAM () DRAM ()

3 Vol.-ARC-8 No.8 Vol.-OS- No.8 // HT BASE + MR BASE MMAT > HT DRAM + MR DRAM MMAT() () MR BASE MR DRAM > HT DRAM HT BASE MMAT DRAM MR REDUCT ION HT DRAM HT BASE HT OV ERHEAD DRAM. DRAM MB DRAM MB 8 B MMAT. DRAM DRAM DRAM DRAM HT OVERHEAD MR REDUCTION DRAM MB 8MB.swim,.mgrid,.applu, 8.equake U, FMM MB FFT MB.gzip Raytrace MB DRAM () 8 ] [ % 率スミュシッャキャ.gzip 8.wupwise.swim.mgrid.applu.mesa.art 8.mcf 8.equake 88.ammp.bzip.twolf.apsi MB MB 8MB MB MB MB 8MB キャッシュ容量 SPEC CPU ] [ % 率スミュシッャキャ Cholesky FFT U Barnes FMM Ocean Raytrace WaterSpatial MB MB 8MB MB MB MB 8MB キャッシュ容量 Splash. MR REDUCTION HT OVERHEAD DRAM Profit DRAM Profit = MT REDUCTION HT OVERHEAD () MT REDUCTION = MR REDUCTION MMAT Profit. DRAM HT OVERHEAD DRAM DRAM Ocean MB

Vol.-ARC-8 No.8 Vol.-OS- No.8 // ス / セ数 8 スミュシクアュシッッャャキキ万 Profit 8 MR _REDUCTI ON [points].applu.mesa 8.equake.mgrid U.swim FMM Ocean 8.wupwise 8.mcf.bzip WaterSpatial Cholesky 88.

4 Vol.-ARC-8 No.8 Vol.-OS- No.8 // ス / セ数 8 スミュシクアュシッッャャキキ万 Profit 8 MR _REDUCTI ON [points].applu.mesa 8.equake.mgrid U.swim FMM Ocean 8.wupwise 8.mcf.bzip WaterSpatial Cholesky 88.ammp Barnes FFT.gzip HT D [cc] Raytrace.art _OVERHEA.twolf.apsi MR REDUCTION HT OVERHEAD P rofit MB MB 区間 Ocean 8 ィテルナペスミベースプロセッサ区間 DRAM スタック法 Ocean MB DRAM HT + MR MMAT DRAM 8 未使用 Cache (SRAM) Core キャッシュモード切り替え Data Cache (DRAM) Tag RAM (SRAM) タグモード DRAM... DRAM SRAM DRAM. DRAM SRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM Core

5 Vol.-ARC-8 No.8 Vol.-OS- No.8 // デコーダキャッシュモード時データが格納される領域タグタグタグフィールド下層 SARM( 容量 : CS デコーダラインサイズ : S 連想度 : WS ) ビットアドレス ( 物理アドレス ) インデックスフィールド - lgs - IS - lgd - ID IS ID lg S lg オフセットフィールド D 上層 DARM( 容量 : CD ラインサイズ : D 連想度 : WD ) キャッシュモード時タグが格納される領域 Way 下層 SRAM ( ウェイセットアソシアティブ SRAM キャッシュ ) 8. Way 上層 DRAM ( ウェイセットアソシアティブ DRAM キャッシュ ) DRAM DRAM DRAM SRAM 8 DRAM DRAM DRAM C S C D S D W S W D S CS IS = lg S WS CD ID = lg D WD MUX S S -lgs - IS Data (SRAM) - lg S - IS - lg S - IS = = Hit/Miss (SRAM) IS - lg D - ID CD S WS lg CS D WD -lg D - ID = MUX = ID - lg D - ID Hit/Miss (DRAM) D D MUX D Data (DRAM) DRAM DRAM MUX MUX C D S W S C S D W D I S I S C D S W S C S D W D W D DRAM 8

6 Vol.-ARC-8 No.8 Vol.-OS- No.8 // SRAM DRAM C S S W S C D I S I D D W D DRAM C DW S C S W D ( lg D lgi D) S DRAM. DRAM? DRAM. DRAM DRAM DRAM. DRAM MB B DRAM MB B DRAM.8MB %... D-BASE. SRAM D-CONV. DRAM DRAM SRAM / DRAM D-HYBRID-STATIC

7 Vol.-ARC-8 No.8 Vol.-OS- No.8 // / KB 8 B clock cycle clock cycles - B - B D-BASE D-CONV MB MB 8 8 B B clock cycles clock cycles Splash Cholesky tk. FFT M data points U matrix Barnes K particles FMM K particles Ocean 8 8 ocean Raytrace balls WaterSpatial molecules D-HYBRID-DYNAMIC M ) () AMAT ) SPEC-CPU ) train Splash ) 8. D-BASE D-CONV, D-HYBRID-STATIC D-HYBRID- DYNAMIC. 比上. 向能. 性. D-BASE D-CONV D-HYBRID-STATIC D-HYBRID-DYNAMIC ベンチマークプログラム SPEC CPU DRAM D-CONV.gzip Cholesky FFT.. () MR BASE MR DRAM >. () D-CONV DRAM % MB MB D-HYBRID-STATIC DRAM D-CONV

8 Vol.-ARC-8 No.8 Vol.-OS- No.8 //. 比上向能性.. D-BASE D-CONV D-HYBRID-STATIC D-HYBRID-DYNAMIC ベンチマークプログラム Splash Splash Rate tag Cholesky FFT U Barnes FMM Ocean Raytrace WaterSpatial Rate tag [%] D-BASE D-BASE % D-CONV % D-HYBRID-DYNAMIC 8.mcf 88.ammp Ocean D-HYBRID-STATIC D-BASE 8% D-CONV % 8.mcf D-HYBRID-STATIC % 8.mcf Splash D-HYBRID-DYNAMIC Rate tag Ocean FMM % % FMM % D-HYBRID-DYNAMIC. DRAM % % SI (NEDO) ) Binkert, N.., Dreslinski, R.G., Hsu,.R., im, K.T., Saidi, A.G. and Reinhardt, S.K.: The M Simulator: Modeling Networked Systems, IEEE Micro, Vol., No., pp. (). ) Black, B., Annavaram, M., Brekelbaum, N., DeVale, J., Jiang,., oh, G. H., McCaule, D., Morrow, P., Nelson, D.W., Pantuso, D., Reed, P., Rupley, J., Shankar, S., Shen, J. and Webb, C.: Die Stacking (D) Microarchitecture, MICRO : Proceedings of the th Annual IEEE/ACM International Symposium on Microarchitecture, IEEE Computer Society, pp. (). ) Jin, Z. and Cheng, A.C.: Evolutionary Benchmark Subsetting, IEEE Micro, Vol.8, No., pp. (8). ) oh, G.H.: D-Stacked Memory Architectures for Multi-core Processors, SIGARCH Comput. Archit. News, Vol., No., pp. (8). ) Puttaswamy, K. and oh, G.H.: Implementing Caches in a D Technology for High Performance Processors, ICCD : Proceedings of the International Conference on Computer Design, IEEE Computer Society, pp. (). ) Woo, S.C., Ohara, M., Torrie, E., Singh, J.P. and Gupta, A.: The SPASH- programs: characterization and methodological considerations, ISCA : Proceedings of the nd annual international symposium on Computer architecture, ACM, pp. (). 8

DRAM L2 L2 DRAM L2 DRAM L2 RAM DRAM 3 DRAM 3. 1 DRAM SRAM/DRAM 2. SRAM/DRAM DRAM LLC Last Level Cache 2 2) DRAM 1(A) (B) LLC L2 DRAM DRAM L2 SRAM DRAM

DRAM L2 L2 DRAM L2 DRAM L2 RAM DRAM 3 DRAM 3. 1 DRAM SRAM/DRAM 2. SRAM/DRAM DRAM LLC Last Level Cache 2 2) DRAM 1(A) (B) LLC L2 DRAM DRAM L2 SRAM DRAM SRAM/DRAM 1 1 2 2 3 DRAM DRAM 2 SRAM/DRAM 1) 1) L2 3.01 1.17 Run-time Operation-Mode Management on SRAM/DRAM Hybrid Cache SHINYA HASHIGUCHI, 1 NAOTO FUKUMOTO, 1 KOJI INOUE 2 and KAZUAKI MURAKAMI 2 3D stacked