/ SimpleScalar 4.0 CPU SimpleScalar/ARM 11) 1 2 MiBench Version ) basicmath B-4Way B-4WAY basicmath Fi
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1 Vol. 52 No (Dec. 2011) 1 1 / Cache Fill Control Method for Embedded Processors Tomoaki Ukezono 1 and Kiyofumi Tanaka 1 Recently, the number of tasks and data sets that are dealt with in embedded systems are increasing as embedded applications are enlarged. It is difficult to implement large cache memories in accordance with these applications, since embedded systems are often required to be inexpensive. In this paper, we propose and discuss control of filling for cache memories with a small-sized buffer. The proposed method selects fill targets (conventional cache memories or small buffers) by knowing access locality in the caches. This can alleviate performance degradation when small cache memories deal with large program binaries and data sets School of Information Science, Japan Advanced Institute of Science and Technology / OS RISC SH-2A 1) ARM 2) ) 1 4),5) ARM TCM: tightly coupled memories Cell BE SPE LS 6) StrongARM 7) 32-way XScale 8) 32-way CAM 9) 3160 c 2011 Information Processing Society of Japan
2 / SimpleScalar 4.0 CPU SimpleScalar/ARM 11) 1 2 MiBench Version ) basicmath B-4Way B-4WAY basicmath Fig. 1 Miss rates of each block address in 512 B-4WAY cache for basicmath.
3 KB-4WAY basicmath Fig. 2 Miss rates of each block address in 4 KB-4WAY cache for on basicmath ,000 1,500, KB-4Way 4,000 10, (1) 1 2 (2) (3) (4) 1/2 (5) Way / / /
4 Fig. 3 An overview of proposed cache memory system. FTS Fill Target Selector FTS FTS FTS 3.2 FTS FTS FTS FTS FTS 10) % 1% FTS 2.2 FTS 4 FTS 2 block1 block block4 block1 block2 block1 block2 block3 block4 1 FTS block3 block4 block1 block2 block3 block4 block3 block4 block1 block2 1 1 block3 block4 block3 block4
5 victim cache FTS SimpleScalar MiBench Version ) MiBench HP 13) ARM automotive 3 consumer 4 network 2 office 4 security 2 telecom 1 16 automotive 3 consumer 8 network 2 office 4 security 2 telecom 3 22 large 4 4 Fig. 4 An overview of alleviation of slashing using a small buffer SimpleScalar/ARM 11) SimpleScalar/ARM 16 / 512 1K 2K K 2K 4K KB 4.2 victim cache 14) victim cache victim cache victim cache victim cache victim cache
6 victim cache victim cache 1 victim cache victim victim cache victim cache victim cache 1 2 victim cache 3 2 victim cache victim victim 3 victim cache 2K basicmath 6.6% basicmath susan djpeg lame ghostscript ispell rsynth blowfish rijindael 512 1K 1K rijindael 65% 5 Fig. 5 Miss rates of instruction cache.
7 Fig. 6 Miss rates of data cache. victim cache % 1K 1.5% 2K 2.8% 1.83% % 1K 25.8% 2K 19.2% 21.99% victim cache ) victim 5 4K 4 12 victim cache susan djpeg ghostscript ispell rsynth rijndael 65% victim cache % 1K 9.6% 2K 10.2% 4K 5.9% 8.00% % 1K 15.5% 2K 18.9% 4K 10.0% 14.70% victim cache 1 dijkstra 1KB
8 dijkstra 1K dijkstra 1 2 dijkstra 5. FTS or 3.2 1% CPU FTS CPU 5.1 FTS 4 FTS 8 FTS 1 AND victim cache 1 CPU victim cache 16) FTS FTS victim cache FTS Fig KB-4WAY Variation in miss rates of 1 KB-4WAY cache by increasing buffer entries. 1 victim cache victimcache victim cache
9 3168 Coretex A-15 21) PtoP CPU PtoP 8 FTS Fig. 8 Detailed circuit schematic of FTS. /victim FTS LSI 8 FTS victim cache LSI FTS 5.2 FTS 3.2 FTS CPU 128 HyperTransport 17) QPI 18) PtoP Point to Point PtoP ARM PtoP AMBA4 19),20) AMBA4 HyperTransport HyperTransport HyperTransport 2 CPU DRAM CPU FTS DRAM DRAM DRAM DRAM 1 1
10 PtoP PtoP 22) PtoP CPU DRAM PtoP victim cache victim cache 4.2 victim cache victim cache victim cache victim cache victim cache 2 Time Based Load Filter TBLF 15) TBLF Load Buffer LB L1 LB victim cache LB Access Interval victim cache TBLF LB LB TBLF LB % 14.70%
11 B ) SH-2A SH2A-FPU Rev.3.00 (2005). 2) Seal, D., ARM Limited: ARM Architecture Reference Manual, 2nd ed., Addison- Wesley (2000). 3) 2009 ESS 2009 pp (2009). 4) Wolfe, A. and Chanin, A.: Executing Compressed Programs on an Embedded RISC Architecture, Proc. Intl. Symp. on Microarchitecture, pp (1992). 5) Lefurgy, C., Bird, P., Chen, I.-C. and Mudge, T.: Improving Code Density Using Compression Techniques, Proc. Intl. Symp. on Microarchitecture, pp (1997). 6) Pham, D. et al.: The Design and Implementation of a First-Generation CELL Processor, IEEE Intl. Solid-State Circuits Conference, pp (2005). 7) Montanaro, J. et al.: A 160-MHz, 32-b, 0.5-W, CMOS RISC Microprocessor. 8) Intel Corporation: Intel XScale Microarchitecture, Technical Summary (2000). 9) Veidenbaum, A. and Nicolaescu, D.: Low Energy, Highly-Associative Cache Design for Embedded Processors, Proc. Intl. Conf. on Computer Design (ICCD), pp (2004).
12 ) 2010 ESS 2010 pp (2010). 11) available from 12) Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T. and Brown, R.B.: MiBench: A free, commercially representative embedded benchmark suite, Proc. IEEE International Workshop on In Workload Characterization 2001 (WWC- 4 ) (2001). 13) available from 14) Jouppi, N.P.: Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, Proc. Intl. Symp. on Computer Architecture, pp (1990). 15) Time Based Filter ARC-152 Vol.2003, No.27, pp (2003). 16) AMD Athlon TM Processor and AMD Duron TM Processor with Full-Speed On-Die L2 Cache, A White Papaer by AMD (2000), available from datasheetarchive.com/pdf-datasheets/datasheets-1/dsa-4978.html. 17) HyperTransport TM Technology I/O Link, A White Paper by AMD (2001), available from A HTWhite Paper v1.1.pdf. 18) Intel R QuickPath Architecture: A new system architecture for unleashing the performace of future generations of Intel R multi-core microprocessors, A White Paper by Intel (2008), available from whitepaper.pdf. 19) AMBA AXI and ACE Protocol Specification (2011), available from arm.com/download/arm and AMBA Architecture/ AR500-DA r0p0-00bet0/IHI0022D2c amba axi protocol spec beta.pdf. 20) AMBA R 4 AXI4 TM, AXI4-Lite TM, and AXI4-Stream TM Protocol Assertions, A User Guide by ARM R (2010), available from download.tm?pv= ) Brian Carlson, Going beyond a faster horse to transform mobile devices, A White Paper by Texas Instruments (2011), available from pdfs/wtbu/swpt048.pdf. 22) Intel R E7520 Memory Controller Hub (MCH) Datasheet, A Detasheet by Intel Corporation (2005), available from pdf. ( ) ( ) IEEE-CS ACM
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2017 (411824) 16.16% Abstract Multi-core processor is common technique for high computing performance. In many multi-core processor architectures, all processors share L2 and last level cache memory. Thus,
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Vol. 52 No. 1 257 268 (Jan. 2011) 1 2, 1 1 measurement. In this paper, a dynamic road map making system is proposed. The proposition system uses probe-cars which has an in-vehicle camera and a GPS receiver.
Kochi University of Technology Aca Title 省 電 力 セルフタイム 回 路 に 関 する 研 究 Author(s) 岩 田, 誠, 宮 城, 桂, 三 宮, 秀 次, 西 川, 博 昭 Citation 高 知 工 科 大 学 紀 要, 10(1): 95-102 Date of 2013-07-20 issue URL http://hdl.handle.net/10173/1082
12) NP 2 MCI MCI 1 START Simple Triage And Rapid Treatment 3) START MCI c 2010 Information Processing Society of Japan
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24 Development of the programming s learning tool for children be derived from maze 1130353 2013 3 1 ,,,,., C Java,,.,,.,., 1 6 1 2.,,.,, i Abstract Development of the programming s learning tool for children
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