Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessor Takahiro SASAKI, Tomohiro INOUE, Nobuhiko OMORI, Tetsuo HIRONAKA, Han
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1 Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessor Takahiro SASAKI, Tomohiro INOUE, Nobuhiko OMORI, Tetsuo HIRONAKA, Hans J. MATTAUSCH, and Tetsushi KOIDE µm CMOS kbyte 16 kbyte 16 kbyte 64 kbyte 1. 1 Graduate School of Information Sciences, Hiroshima City University, Ozuka-Higashi, Asa-Minami-ku, Hiroshima-shi, Japan Research Center for Nanodevices and Systems, Hiroshima University, Kagamiyama, Higashi-hiroshima-shi, Japan (On-chip Multiprocessor) (Symmetric Multiprocessor; SMP) (Coherency) 350 D I Vol. J87 D I No. 3 pp
2 1 2 1 CMOS 0.5 µm kbyte 16 kbyte CMOS 8 CMOS 0.5 µm LU SMP PE (Processing Element) L1 L2 Illinois [3] Dragon [4], MOESI [5] [6] Fig. 1 Multiprocessor architecture with distributed cache. 351
3 2004/3 Vol. J87 D I No [7] [7] NEC Merlot [8] Merlot Merlot 1 PE 8 Merlot 1 [8] 2. 3 psas [9], [10] CPU CPU [9] [10] (threshold) [10] LSI 3. L1 L2 2 1 [11] 1GHz CPU L1 1 L2 2 L2 PE L1 L2 352
4 2 L2 Fig. 2 Multiprocessor architecture with shared L2 cache. L1 L1 L1 L1 L2 L CMOS 0.5 µm Fig. 3 Multiport memory cell approach. 4 Fig. 4 Ports vs. chip size (Multiport memory cell approach)
5 2004/3 Vol. J87 D I No (Hierarchical Multiport Memory Architecture; HMA) [1] 5 5 Fig. 5 Hierarchical multiport memory N (1-to-N-Port Transition) 2 (Conflict Resolver) 1 N N CMOS 0.5 µm LSI [2] 6 Fig. 6 Multibank memory with crossbar network and hierarchical multiport memory. 354
6 7 Fig. 7 Chip size of hierarchical multiport memory and multiport memory cell approach. 8 1 SRAM Fig. 8 Access time of single port memory and hierarchical multiport memory. 7 7 HMA MP-Cell kbit [2] SRAM SPICE 8 8 SRAM-Read 1 SRAM HMA-Read SRAM-Write 1 SRAM HMA-Write 8 1 SRAM 0.9 ns 0.6 ns 1 N 64 kbit SRAM kbit [2] [7] 355
7 2004/3 Vol. J87 D I No. 3 1 Table 1 Parameters and its default values for simulation with shared L2 cache. 8 8 L1 32 kbyte/pe L1 4 L1 8word L1 1cycle L2 256 kbyte/pe L2 8 L2 8word L2 4cycle CPU L2 6cycle L bank 20 cycle 4 *1: Bank ) 3. 1 Bank 2) 3. 2 MP-Cell 3) 2. 1 Distrib 3 Distrib Dragon 1 RISC C Sun UltraSPARC-III SPLASH2 [12] LU RAYTRACE LU RAYTRACE gcc Sun WorkShop 6.0 LU LU RAY- TRACE SPLASH2 teapot SMALL Distrib MP-Cell [13] CMOS 0.5 µm LU LU L (a) kbyte 256 kbyte RAYTARCE 356
8 9 Fig. 9 (LU) Processors vs. processing time (LU). 10 Fig. 10 (LU) Cache size vs. processing time (LU) Distrib Bank MP-Cell Bank MP-Cell Bank MP-Cell (b) kbyte/pe 16 kbyte L kbyte L LU kbyte/pe LU 128 kbyte LU kbyte/pe 128 kbyte Bank MP-Cell kbyte/pe 256 kbyte/pe L2 11 Bank 357
9 2004/3 Vol. J87 D I No. 3 (a) 64 kbyte/pe 12 Fig. 12 (LU) Chip size vs. processing time (LU). (b) 256 kbyte/pe 11 (LU) Fig. 11 Cache latency vs. processing time (LU). MP-Cell (a) 64 kbyte/pe (b) 256 kbyte/pe 6 (c) kbyte/pe 12 Distrib 128 kbyte/pe Bank 64 kbyte/pe MP-Cell 16 kbyte/pe Distrib MP-Cell 89.6 Bank 85.0 Bank RAYTRACE RAYTRACE LU RAYTRACE LU 67.9 LU L (a) (b)
10 13 (RAYTRACE) Fig. 13 Processors vs. processing time (RAYTRACE). 15 Fig. 15 (RAYTRACE) Chip size vs. processing time (RAYTRACE). 14 (RAYTRACE) Fig. 14 Cache size vs. processing time (RAYTRACE) Distrib Bank MP-Cell MP- Cell Bank Bank MP-Cell (c) Bank MP-Cell 15 MP-Cell Bank Bank 128 kbyte/pe MP-Cell 91.2 Bank 88.8 Bank
11 2004/3 Vol. J87 D I No. 3 (a) Bank Distrib MP-Cell 16 Bank kbyte/pe MP-Cell [2] (b) Distrib MP-Cell 256 kbyte/pe Bank 256 kbyte/pe 256 kbyte/pe 16 Fig. 16 Processors vs. processing time (HIMENO benchmark). 17 Fig. 17 Processors vs. processing time (HIMENO benchmark). 360
12 18 Fig. 18 Cache size vs. processing time (HIMENO benchmark). 20 Fig. 20 Chip size vs. processing time (HIMENO benchmark). 19 Fig. 19 Cache size vs. cache hit ratio (HIMENO benchmark). 256 kbyte/pe kbyte/pe kbyte/pe 1024 kbyte/pe Distrib kbyte/pe Bank (c)
13 2004/3 Vol. J87 D I No. 3 Bank 5. CPU 1) 2) L2 8 CMOS 0.5 µm LU IP 5 23rd European Solid-State Circuits Conference (ES- SCIRC 97), pp , [2] CAS , [3] M.S. Papamarcos and J.H. Patel, A low-overhead coherence solution for multiprocessors with private cache memories, Proc. 11th International Symposium of Computer Architecture, pp , [4] J. Archibald and J.-L. Baer, Cache coherence protocols: Evaluation using a multiprocessor simulation model, ACM Trans. Computer Systems, vol.4, pp , [5] P. Sweazey and A.J. Smith, A class of compatible cache consistency protocols and their support by the IEEE Futurebus, Proc. 13th International Symposium on Computer Architecture, vol.14, no.2, pp , [6] D. Chaiken, J. Kubiatowicz, and A. Agarwal, LimitLESS directories: A scalable cache coherence scheme, Proc. Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS IV), pp , [7] B.A. Nayfeh, L. Hammond, and K. Olukotun, Evaluation of design alternatives for a multiprocessor microprocessor, Proc. 23rd International Symposium on Computer Architecture, pp.67 77, [8] ARC ARC-139, pp , [9] vol.40, no.5, pp , [10] (D-I), vol.j83- D-I, no.7, pp , July [11] G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker, and P. Roussel, The microarchitecture of the Pentium4 processor, Intel Technology Journal, pp.1 13, [12] S.C. Woo, M. Ohara, E. Torrie, J.P. Singh, and A. Gupta, The SPLASH-2 programs: Characterization and methodological considerations, Proc. 22nd International Symposium on Computer Architecture (ISCA 95), pp.24 36, [13] J.L. Miller, J. Conary, and D. DiMarco, A 16 GB/s, 0.18 µm cache tile for integrated L2 caches from 256 KB to 2 MB, Symposium on VLSI Circuits, [1] H.J. Mattausch, Hierarchical N-port memory architecture based on 1-port memory cells, Proc. 362
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