DRAM L2 L2 DRAM L2 DRAM L2 RAM DRAM 3 DRAM 3. 1 DRAM SRAM/DRAM 2. SRAM/DRAM DRAM LLC Last Level Cache 2 2) DRAM 1(A) (B) LLC L2 DRAM DRAM L2 SRAM DRAM

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1 SRAM/DRAM DRAM DRAM 2 SRAM/DRAM 1) 1) L Run-time Operation-Mode Management on SRAM/DRAM Hybrid Cache SHINYA HASHIGUCHI, 1 NAOTO FUKUMOTO, 1 KOJI INOUE 2 and KAZUAKI MURAKAMI 2 3D stacked DRAM caches can dramatically reduce off-chip memory accesses. However, this approach degrades performance in some cases because increasing cache size makes access time longer. To solve this issue, we propose dynamically controlled SRAM/DRAM Hybrid Cache. Hybrid Cache supports two operation modes: fast, small SRAM cache mode, and slow, larage DRAM cache mode. The cache attempts to select an appropriate mode based on memory access behavior at run time. This paper proposes an algorithm for the mode selection. Our evaluation results show that we can achieve speed-up 3.01X in maximum and 1.17X in average DRAM 3 DRAM TSV Through Silicon Via 2)3) 3 SRAM/DRAM 1) DRAM SRAM DRAM 1) L2 SRAM DRAM Graduate School of Information Science and Electrical Engineering, Kyushu University 2 Faculty of Information Science and Electrical Engineering, Kyushu University 1

2 DRAM L2 L2 DRAM L2 DRAM L2 RAM DRAM 3 DRAM 3. 1 DRAM SRAM/DRAM 2. SRAM/DRAM DRAM LLC Last Level Cache 2 2) DRAM 1(A) (B) LLC L2 DRAM DRAM L2 SRAM DRAM (C) 1) 2 SRAM SRAM L2 DRAM L2 DRAM DRAM L2 SRAM L1 3.1 SRAM DRAM (?) (?) 1 2

PC 3.2 ( 1 ) L2 L2 ( 2 ) L2 L2 L2 / ( 3 ) / 1) ( 4 ) L2 2 L2 L2 ( ) 2 L1 mcf 3.

3 PC 3.2 ( 1 ) L2 L2 ( 2 ) L2 L2 L2 / ( 3 ) / 1) ( 4 ) L2 2 L2 L2 ( ) 2 L1 mcf L1 twolf SRAM DRAM ( ) 2 3 SPEC CPU 2000 mcf twolf L1 ( L2 L2 ) L L1 mcf twolf 3.4 1) 2) 3.3 L2 ( ) 2 N N+1 3

4 L2 4.2 HTL2 DRAM HTL2 SRAM if MR L2 SRAM MR L2 DRAM > MMAT then DramMode, else SramMode HT L2 SRAM /HT L2 DRAM SRAM/DRAM [cycles] MR L2 SRAM /MR L2 DRAM SRAM/DRAM MMAT [cycles] HT L2 DRAM HT L2 SRAM MMAT MR L2 SRAM MR L2 DRAM L2 L2 DRAM SRAM SRAM DRAM SRAM / SRAM L2 SRAM DRAM DRAM L2 32MB DRAM 64B 2.5MB 4) L N SRAM 3.2 ( 1 ) N SRAM DRAM SRAM L2 ( MR L2 SRAM ) DRAM L2 ( MR L2 DRAM ) 3.4 N+1 (SRAM ) ( 2 ) N+1 SRAM N N+2 SRAM ( 3 ) N+2 DRAM SRAM L2 / N+3 DRAM DRAM SRAM ( 4 ) N+3 DRAM M-1 4

5 ( 5 ) M L2 / M M5 5) AMAT(=L1 L2 ) L1 / 32KB 2 64B, )6)7) SPEC-CPU2000 8) train Splash2 9)?? Cholesky tk29.0 FFT 4M data points LU matrix Barnes 32K particles FMM 64K particles Ocean ocean WaterSpatial 4096 molecules 18 DRAM-STACK DRAM DRAM ( 1(B) L2 32MB 64B 8 L2 28 D-HYBRID ( 1(C)) 3.3 DRAM L2 32MB 64B 8 28 SRAM L2 2MB 64B 8 6 L2 L2 ( SRAM 32K DRAM 512K ) D-HYBRID-IDEAL ( 1(C)) D-HYBRID 1 L ] c 4.7 [ T A 4.6 M A K 200K 500K 1M 2M 5M 10M 1 区間の長さ (L2 ( キャッシュアクセス数 ) DRAM-STACK D-HYBRID-IDEAL D-HYBRID ] 15 c [ T A 14 M A K 200K 500K 1M 2M 5M 10M 1 区間の長さ (L2 ( キャッシュアクセス数 ) ] c 2.7 [ T A 2.5 M A K 200K 500K 1M 2M 5M 10M 1 区間の長さ (L2 ( キャッシュアクセス数 ) (a) FFT (b) mcf (c) bzip (AMAT ) 5 ( L2 ) D-HYBRID-IDEAL D-HYBRID D-HYBRID-IDEAL 1 mcf bzip2 100K 200K 5M 10M FFT D-HYBRID-IDEAL D-HYBRID 3 D-HYBRID 1 5M

6 DRAM-STACK gzip, art, twolf, apsi art 3.3 apsi 1.6 D-HYBRID-IDEAL 5. 3 DRAM SRAM/DRAM SRAM/DTAM 17 LSI (NEDO) 1),,,, 3 DRAM,, Vol. 2009-ARC-183, No.16, 2009 4. 2) Black, B., Annavaram, M.

6 6 DRAM-STACK gzip, art, twolf, apsi art 3.3 apsi 1.6 D-HYBRID-IDEAL 5. 3 DRAM SRAM/DRAM SRAM/DTAM 17 LSI (NEDO) 1),,,, 3 DRAM,, Vol ARC-183, No.16, ) Black, B., Annavaram, M., Brekelbau, N., DeVale, J., Jiang, L., Loh, G. H., McCauley, D., Morrow, P., Nelson, D.W., Pantuso, D., Reed, P., Rupley, J., Shankar, S., Shen, J. and Webb, C.: Die Stacking (3D) Microarchitecture, MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, IEEE Computer Society, pp (2006). 3) Loh, G.H.: 3D-Stacked Memory Architectures for Multi-core Processors, SIGARCH Comput. Archit. News, Vol.36, No.3, pp (2008). 4) Qureshi, M.K. and Patt, Y.N.: Utility-Based Cache Partitioning: A Low-Overhead, High- Performance, Runtime Mechanism to Partition Shared Caches, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 39, Washington, DC, USA, IEEE Computer Society, pp (2006). 5) Binkert, N.L., Dreslinski, R.G., Hsu, L.R., Lim, K.T., Saidi, A.G. and Reinhardt, S.K.: The M5 Simulator: Modeling Networked Systems, IEEE Micro, Vol.26, No.4, pp (2006). 6) Loi, G. L., Agrawal, B., Srivastava, N., Lin, S.-C., Sherwood, T. and Banerjee, K.: A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy, DAC 06: Proceedings of the 43rd annual Design Automation Conference, New York, NY, USA, ACM, pp (2006). 7) Thoziyoor, S., Muralimanohar, N., Ahn, J.H. and Jouppi, N.P.: CACTI5.1, Technical report, HP Lab (2008). 8) Henning, J. L.: SPEC CPU2000: Measuring CPU Performance in the New Millennium, Computer, Vol.33, pp (2000). 9) Woo, S. C., Ohara, M., Torrie, E., Singh, J. P. and Gupta, A.: The SPLASH-2 Programs: Characterization and Methodological Considerations, ISCA 95: Proceedings of the 22nd annual international symposium on Computer architecture, ACM, pp (1995). 6

Vol.-ARC-8 No.8 Vol.-OS- No.8 // DRAM DRAM DRAM DRAM ) DRAM. DRAM. ) DRAM DRAM DRAM DRAM DRAM SRAM DRAM MB B MB DRAM SRAM.. DRAM DRAM SRAM DRAM SRAM C

IPSJ SIG Technical Report Vol.-ARC-8 No.8 Vol.-OS- No.8 // DRAM- DRAM DRAM DRAM % % On-Chip Memory Architecture for DRAM Stacking Microprocessors SHINYA HASHIGUCHI, TAKATSUGU ONO, KOJI INOUE and KAZUAKI