2 76 MPU (MEF mask error factors) nm 9nmCD 14nmCD 2003 MEF 1.0(alt-PSM ) nmCD 5.5nmCD MPU OPC PSM 193nm 157nm 157nm (ROI) 193nm 157nm Ca

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1 CD 15 ITWG International technology working group[ ] ESH Environment, Safety, and Health[ ] TWG RET resolution enhancement techniques OAI off-axis illumination PSM phase shifting masks OPC optical proximity correction (Immersion 45nm RET (NA) 65nm OPC 32nm EUV extreme ultraviolet lithography EPL electron projection lithography (Imprint Lithography) NGL (Next Generation Lithography) (NGL)

2 2 76 MPU (MEF mask error factors) nm 9nmCD 14nmCD 2003 MEF 1.0(alt-PSM ) nmCD 5.5nmCD MPU OPC PSM 193nm 157nm 157nm (ROI) 193nm 157nm CaF2 LER( line edge roughness )

3 nm nm EUV EPL ( ) (ROI: Return on Investment) RET EUV 1.8 nm (3 ) < 19 nm OPC (Optical Pattern Correction) ArF F2 (CaF 2 ) LER SEM 30 nm. 010 <45 nm 5 NGL ( ) 7nm 7.2nm <30nm ROI ROI LER <1 nm (3 sigma) <7.2 nm SEM scanning electron microscope

4 4 77a, 77b 78a, 78b, 78c 79a, 79b, 79c MPU MEF CD MPU ( ) LER NGL EUV EPL 79a b c NGL 45nm EUV EPL NGL NGL NGL

5 5 77a Lithography Technology Requirements Near-term Year of Production Technology Node hp90 hp65 DRAM DRAM ½ Pitch (nm) Contact in resist (nm) Contact after etch (nm) Overlay CD control (3 sigma) (nm) MPU MPU/ASCI Metal 1 (M1) ½ pitch (nm) MPU ½ Pitch (nm) (uncontacted gate) MPU gate in resist (nm) MPU gate length after etch (nm) Contact in resist (nm) Contact after etch (nm) Gate CD control (3 sigma) (nm) ASIC/LP ASIC ½ Pitch (nm) (uncontacted gate) ASIC/LP gate in resist (nm) ASIC/LP gate length after etch (nm) Contact in resist (nm) Contact after etch (nm) CD control (3 sigma) (nm) Chip size (mm 2 ) DRAM, introduction DRAM, production MPU, high volume at introduction MPU, high volume at production MPU, high performance ASIC Minimum field area Wafer size (diameter, mm) Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

6 6 77b Lithography Technology Requirements Long-term Year of Production Technology Node hp45 hp32 hp22 DRAM DRAM ½ Pitch (nm) Contact in resist (nm) Contact after etch (m) Overlay CD control (3 sigma) (nm) MPU MPU/ASCI Metal 1 (M1) ½ pitch (nm) MPU ½ Pitch (nm) (uncontacted gate) MPU gate in resist (nm) MPU gate length after etch (nm) Contact in resist (nm) Contact after etch (nm) CD control (3 sigma) (nm) ASIC/LP ASIC ½ Pitch (nm) (uncontacted gate) ASIC/LP gate in resist (nm) ASIC/LP gate length after etch (nm) Contact in resist (nm) Contact after etch (nm) CD control (3 sigma) (nm) Chip size (mm 2 ) DRAM, introduction DRAM, production MPU, high volume at introduction MPU, high volume at production MPU, high performance ASIC Minimum field area Wafer size (diameter, mm) Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known 77a 77b : [1] ( ) [2] 2/3 1/3 MPU 80% 20% DRAM ASIC ±15% MPU ±10%

7 7 78a Resist Requirements Near-term Year of Production Technology Node hp90 hp65 DRAM ½ Pitch (nm) MPU/ASIC Metal 1 (M1) ½ Pitch (nm) MPU/ASIC ½ Pitch (nm) (un-contacted gate) MPU Gate in resist Length (nm) MPU Gate Length after etch (nm) Resist Characteristics * Resist meets requirements for gate resolution and gate CD control (nm, 3 sigma) ** Resist thickness (nm, imaging layer) *** Ultra thin resist thickness (nm)**** PEB temperature sensitivity (nm/c) Backside particles (particles/m2 at critical size, nm) Defects in spin-coated resist films #/cm (size in nm) Defects in patterned resist films, gates, contacts, etc. #/cm (size in nm) Line Width Roughness (nm, 3 sigma) <8% of CD ****** Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

8 8 78b Resist Requirements Long-term Year of Production Technology Node hp45 hp32 hp22 DRAM ½ Pitch (nm) MPU/ASIC Metal 1 (M1) ½ Pitch (nm) MPU/ASIC ½ Pitch (nm) MPU Printed Gate Length (nm) MPU Physical Gate Length (nm) Resist Characteristics * Resist meets requirements for resolution and gate CD Control (nm, 3 sigma) ** Resist thickness (nm, imaging layer) *** Ultra thin resist thickness (nm)*** PEB temperature sensitivity (nm/c) Backside particles (particles/m 2 at critical size, nm) Defects in spin-coated resist films #/cm (size in nm) Defects in patterned resist films for gates, contacts, etc. #/cm (size in nm) Line Width Roughness (nm, 3 sigma) <8% of CD ****** Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

9 9 78c Resist Sensitivities Exposure Technology Sensitivity 78a 78b : 248 nm mj/ cm nm mj/ cm nm 5 15 mj/ cm 2 Extreme Ultraviolet at 13.5 nm 2 15 mj/ cm 2 Electron Beam Projection at 100 kv ***** 2 10 uc/ cm 2 E-beam Direct Write at 50 kv ***** 5 10 uc/ cm 2 ***** * ( ) ** *** 2.5:1 4:1 **** ***** 1 ****** LWR (Line Width Roughness) spatial frequences 3σ P 0. 5X j P X LWR=SQRT(2)*LER : [A] [B] 90±2 [C] 130 [D] (PHOST: poly hydroxystyrene) [E] [F] <1000pptM [G] Metal < 5ppb [H] 2 (molecules/cm 2 sec) 157nm <1e12 EUV <5e13 EPL [I] 2 Si (molecules/cm 2 sec) 157nm <1e8 EUV <5e13 EPL 1

10 10 79a Optical Mask Requirements Year of Production Technology Node hp90 hp65 DRAM ½ Pitch (nm) MPU/ASIC ½ Pitch (nm) MPU Printed Gate Length (nm) MPU Physical Gate Length (nm) Wafer minimum half pitch (nm) Wafer minimum line (nm, in resist) [A] Wafer minimum line (nm, post etch) Overlay Wafer minimum contact hole (nm, post etch) Magnification [B] Mask nominal image size (nm) [C] Mask minimum primary feature size [D] Mask OPC feature size (nm) clear Mask sub-resolution feature size (nm) opaque [E] Image placement (nm, multi-point) [F] CD uniformity allocation to mask (assumption) MEF isolated lines, binary [G] CD uniformity (nm, 3 sigma) isolated lines (MPU gates), binary mask [H] MEF isolated lines, alternating phase shift [G] CD uniformity (nm, 3 sigma) isolated lines (MPU gates), alternating phase shift mask [I] MEF dense lines [G] CD uniformity (nm, 3 sigma) dense lines (DRAM half pitch), binary or attenuated phase shift mask [J] MEF contacts [G] CD uniformity (nm, 3 sigma), contact/vias [K] Linearity (nm) [L] CD mean to target (nm) [M] Defect size (nm) [N] * Substrate form factor Blank flatness (nm, peak-valley) [O] Transmission uniformity to mask (pellicle and clear feature) (±% 3 sigma) Data volume (GB) [P] Mask design grid (nm) [Q] % Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

11 11 79a Optical Mask Requirements (continued) Year of Production Technology Node hp90 hp65 DRAM ½ Pitch (nm) MPU/ASIC ½ Pitch (nm) MPU Printed Gate Length (nm) MPU Physical Gate Length (nm) Attenuated PSM transmission mean deviation from target (± % of target) [R] Attenuated PSM transmission uniformity (±% of target) [R] Attenuated PSM phase mean deviation from 180º (± degree) [S] Alternating PSM phase mean deviation from nominal phase angle target 180º degrees (± degree) [S] Alternating PSM phase uniformity (± degree) [T] Nominal reflectivity (%) [U] 20% 20% 15% 15% 15% 10% 10% Mask materials and substrates Absorber on fused silica, except for 157 nm optical that will be absorber on fluorine doped, low OH fused silica substrate. Strategy for protecting mask from defects (Exposure tool dependent) Pellicle for optical masks down to 193 nm. Modified fused silica pellicles have demonstrated feasibility for 157- nm scanners, and removable pellicles might be useful for small lot production. Research continues on organic membrane pellicles materials in a search for viable solutions. Primary PSM choices are attenuated shifter and alternating aperture 70% Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known 79a Optical Mask requirements : [A] Wafer Minimum Line Size: ( ) [B] Magnification: N: [C] Mask Nominal Image Size: 4X [D] Mask Minimum Primary Feature Size: OPC [E] Mask Sub-Resolution Feature Size: [F] Image Placement: (X Y) [G] MEF(Mask Error Factor) MEF 1 [H] CD Uniformity: 3σ X Y

12 12 [I] CD Uniformity: 3σ X Y [J] CD Uniformiyt: 3σ X Y [K] CD Uniformity: 3σ [L] Linearity: 3/2 [M] CD Mean to Target: ( - )/ [N] Defect Size: 10% [O] Blank Flatness: 6 110mmx110mm nm [P] Data Volume: [Q] Mask Design Grid: [R] Transmission: % [S] Phase: 2 [T] Alt PSM [U] ( )

13 13 79b EUVL Mask Requirements Year of Production Technology Node hp45 hp32 hp22 DRAM ½ Pitch (nm) Wafer minimum half pitch (nm) Wafer minimum line (nm, in resist) [A] Wafer minimum line (nm, post etch) Overlay Wafer minimum contact hole (nm, after etch) Generic Mask Requirements Magnification [B] Mask nominal image size (nm) [C] Mask minimum primary feature size [D] Image placement (nm, multi-point) [E] CD Uniformity (nm, 3 sigma) [F] Isolated lines (MPU gates) Dense lines DRAM (half pitch) Contact/vias Linearity (nm) [G] CD mean to target (nm) [H] Defect size (nm) [I] Data volume (GB) [J] Mask design grid (nm) [K] Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

14 14 79b EUVL Mask Requirements (continued) Year of Production Technology Node hp45 hp32 hp22 DRAM ½ Pitch (nm) EUVL-specific Mask Requirements Substrate defect size (nm) [L] Mean peak reflectivity 65% 66% 66% 67% 67% 67% 67% 67% Peak reflectivity uniformity (% 3 sigma absolute) 0.58% 0.56% 0.54% 0.48% 0.42% 0.36% 0.30% 0.24% Reflected centroid wavelength uniformity (nm 3 sigma) [M] Minimum absorber sidewall angle (degrees) Absorber sidewall angle tolerance (± degrees) Absorber LER (3 sigma nm) [N] Mask substrate flatness (nm peak-to-valley) [O] Maximum aspect ratio of absorber stack Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known 79b EUV Mask requirements : EUVL [A] Wafer Minimum Line Size: ( ) [B] Magnification: N: [C] Mask Nominal Image Size: N [D] Mask Minimum Primary Feature Size: OPC [E] Image Placement: (X Y) [F] CD Uniformity: 3σ X Y : ( ) ( ) [G] Linearity: 3/2

15 15 [H] CD Mean to Target: Σ( - )/ [I] Defect Size: 10% [J] Data Volume: [K] Mask Design Grid: [L] Substrate Defect Size: [M] [N] Line edge roughness (LER): σ [O] Mask Substrate Flatness: 5mm nm peak-to-valley

16 16 79c EPL Mask Requirements Year of Production Technology Node hp45 hp32 hp22 DRAM ½ Pitch (nm) Wafer minimum half pitch (nm) [A] Wafer minimum line (nm, in resist) Wafer minimum line (nm, post etch) Overlay Wafer minimum contact hole (nm, post etch) Generic mask requirements Magnification [B] Mask minimum image size (nm) [C] Image placement error in sub-field (nm, multi-point) [D] Sub-field placement error on mask (nm, 3 sigma, non-linear term) [E] CD Uniformity (nm, 3 sigma) [F] Isolated lines (MPU gates) Dense lines (DRAM half pitch) Contact/vias Linearity (nm) [G] CD mean to target (nm) [H] Pattern corner rounding (nm) Defect size (nm) [I] Data volume (GB) [J] Mask design grid (nm) [K] EPL-specific Mask Requirements Mask type Mem-bra ne [T] Stencil [U] Mem-bra ne [T] Stencil [U] Mem-bra ne [T] Stencil [U] Clear area transmission factor [L] 50% 100% 50% 100% 50% 100% 70% 100% 70% 100% 70% 100% 70% 100% 70% 100% Membrane thickness uniformity (3 sigma %) [M] Membrane thickness uniformity in sub-field (3 sigma %) [N] Mem-bra ne [T] Stencil [U] Mem-bra ne [T] Stencil [U] Mem-bra ne [T] Stencil [U] Mem-bra ne [T] Stencil [U] Mem-bra ne [T] 2% N/A 2% N/A 2% N/A 2% N/A 2% N/A 2% N/A 2% N/A 2% N/A 1% N/A 1% N/A 1% N/A 1% N/A 1% N/A 1% N/A 1% N/A 1% N/A Membrane mean thickness error (%) [O] 10% N/A 10% N/A 10% N/A 10% N/A 10% N/A 10% N/A 10% N/A 10% N/A Scatterer thickness uniformity in mask (3 sigma %) [P] 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% Scatterer mean thickness error (%) [Q] 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% Pattern sidewall angle (degrees) Stencil [U] Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

17 17 79c EPL Mask Requirements (continued) Year of Production Technology Node hp45 hp32 hp22 DRAM ½ Pitch (nm) Pattern sidewall angle tolerance (+ degrees) [R] Scatterer/stencil LER ( 3 sigma nm) [S] Mask substrate flatness (micron peak-to-valley) Mask flatness within a sub-field (micron peak-to-valley) Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known 79c EPL Mask requirements : EPL ( 1mm ) Si ( ) [A] Wafer Minimum Feature Size: ( ) [B] Magnification: N: [C] Mask Minimum Image Size: ( ) [D] Image Placement Error in Sub-field: 3σ 1mm [E] Sub-field Placement in Mask: (X,Y) 3σ EPL [F] CD Uniformity: 3σ X Y : [G] Linearity: 3/2 [H] CD Mean to Target: Σ( - )/ [I] Defect Size: 10% [J] Data Volume: [K] Mask Design Grid:

18 18 [L] Clear Area Transmission Factor: - ( 6 8mrad) [M] Membrane Thickness Uniformity in Mask: 3σ [N] Membrane Thickness Uniformity in Sub-field: 3σ 1mm [O] Membrane Mean Thickness Error: [P] Scatterer Thickness Uniformity in Mask: 3σ [Q] Scatterer Mean Thickness Error: [R] Pattern Sidewall Angle: [S] Scatterer/stencil LER: σ [T] [U]

19 nm NGL 45nm 248nm 193nm 193nm 193nm 157nm Immersion Lithography 193nm 45nm 157nm 157nm 32nm 157nm NGL (NGL) 45nm NGL ( ) EUV EPL (ML2) Imprint PEL(proximity electron lithography ) ( IPL( ion projection lithography ) PXL proximity x-ray lithography 18nm PXL IPL 32nm ML2 ML2

20 20 Technology Node hp90 hp65 hp45 hp32 hp22 hp nm + RET Technology Options at Technology Nodes (DRAM Half-Pitch, nm) nm + RET + litho-friendly designs 157 nm + RET + litho-friendly designs Narrow 193 nm immersion lithography options EPL, PEL 157 nm + RET + litho-friendly designs Immersion 193 nm lithography + RET + litho-friendly designs EPL, PEL ML2 EUV 157 nm immersion + RET + litho-friendly designs EPL, imprint lithography ML2 Narrow options Narrow options DRAM Half-pitch (dense lines) 22 EUV, EPL ML2, imprint lithography Innovative technology Narrow options 16 Innovative technology ML2, EUV + RET Narrow options Research Required Development Underway Qualification/Pre-Production Continuous Improvement This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. Technologies shown in italics have only single region support. RET resolution enhancement technology EUV extreme ultraviolet EPL electron projection lithography ML2 maskless lithography PEL proximity electron lithography STRJ WG5 Lithography 45nm Potential Solution EUVL 53 Lithography Exposure Tool Potential Solutions ESH PFOS perfluorooctyl sulfonates

21 21 ES&H Metrology 20% CD 3D 65nm CD CD Scatterometry SPM (LER) / OPC NGL LER /

22 22 Modeling Simulation ITWG PIDS FEP 2 EPL CD

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ｽﾗｲﾄﾞﾀｲﾄﾙなし WG5: ArF NGL STRJ WS: March 5, 2004, WG5 Lithography 2 WG5 27 STRJ WS: March 5, 2004, WG5 Lithography 3 Outline 1. ITRS Lithography Roadmap 2. ArF (193nm), ArF F 2 (157nm),EUVL PEL (Leepl), EPL, ML2 Imprint,