45nm以降に向けたリソグラフィ技術 －ArF液浸への期待とその後の展開－
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1 1 45nm ArF WG5
2 WG5 2
3 Update Potential Solutions ArF EUV (ML2)
4 Update Potential Solutions - Potential Solutions CD (total CD control) 4nm(3s) CD "Red" 2005 Changes to coloring, footnotes, etc. (2005 updates probable) LWR/LER APC
5 5 Potential Solutions (,, ) IC N+3 WG Potential Solutions
6 Lithography Potential Solutions in 2004 Update Technology Options at Technology Nodes (DRAM Half-Pitch, nm) 2004 Lithography 2004 exposure tool Technology Node nm nm + LFD 193nm immersion PEL 193nm immersion + LFD EUV ML2, 157nm immersion, PEL hp90 hp65 hp45 hp32 hp22 hp16 potential solutions EUV 193nm immersion + LFD 157nm immersion + LFD, ML2 Imprint EUV Innovative 157nm or 193 nm immersion ML2 Imprint, innovative technology Innovative technology ML2, EUV + RET, imprint DRAM Half-pitch (dense lines) RET = Resolution enhancement technology LFD = Lithography friendly design rules ML2 = Maskless lithography Research Required Development Underway Qualification/ Pre-Production Continuous Improvement Notes: EPL is a potential solution at the 65, 45 and 32-nm nodes for one geographical region, and PEL is a potential solution at the 32-nm node for one geographical region. RET will be used with all optical lithography solutions, including with immersion; therefore, it is not explicitly noted.
7 Transition of ITRS Litho Potential Solutions 2004 Update 2003 Edition 2001 Edition ArF+PSM KrF+PSM ML2 EUV F 2 + LFD+Immersion ArF +LFD+Immersion PEL PEL EPL PEL PXL IPL F 2 +PSM EPL ML2 PEL F 2 +RET+LFD+Immersion ArF+RET+LFD+Immersion 65@ EUV EPL ML2 45@ EUV 32@ RET 20 7 Innovation Imprint +RET Innovative Immersion Innovation Imprint Innovation 22@2016
8 8 Potential Solutions ArF NA 1.3 hp45-65nm NA:>1.5 hp32nm F2 ArF Backup EUV hp32nm ML2 Maskless Lithography) hp32nm hp16nm Innovative technology
9 - 9
10 10 - σ
11 11 Potential Solutions ArF NA EUV (ML2)
12 12 ( ) (index = n) Projection optics Wafer stage ( ) Wafer NA = n sin θ = k1 λ / NA = k1 λ / (n sin θ) = k1 (λ/n) / sin θ DOF = k2 (λ/n) / 2 (1-cos θ ) ~ k2 (λ/n) / sin 2 θ = k2 n λ / NA 2 NA
13 ArF 90nm Iso Line, with Topcoat Dry (Dose: 170 J/m2) DOF=0.25um B.F Immersion (Dose: 140 J/m2) DOF=0.40um Condition Illumi: NA0.75 2/3Annular Mask: Att.PSM CANON Substrate: Bare-Si BARC: AR46(30nm) Courtesy of Canon Resist:ARX-2014 (130nm) / JSR TARC:TCX001(29nm) / JSR Development: 60sec 13
14 ArF - 65nm L&S - Focus Dynamic exposure Mask:6% Attn-PSM, Dipole illumination (NA=0.85, σ =0.93) Resist TArF-P6111 (t =170nm), Top coat TSP-3A (t = 34nm) 65nm L/S, DOF=750nm with Dipole illumination Courtesy of Nikon 14
15 15 K1
16 (λ/n) NA = n sin θ Resolution = k 1 λ / NA = k 1 (λ/n) / sin θ * * JSR ArF F2 16
17 n Glass = n Air = 1.00 n H2O = 1.44 n fluid = 1.64 n H2O = 1.44 n Resist =
18 18 NA>1.5 θ flude n Glass θ grass n fluid θ Resist n Resist NA = n grass sinθ grass = n fluid sinθ fluid = n Resist sinθ Resist NA (
19 32nm L/S ArF Immersion Lithography 32nm NA:1.5 by Canon interferometric exposure in JSR s High Refractive Index Fluid Courtesy of JSR and Canon 19
20 NA NA=1.50, n_fluid=1.65 Dipole (4/5 Annular 30 ), Att. PSM CD_DOF(µm) S-Polarized 0.8 σ= σ= σ= σ= L/S(nm) CD_DOF(µm) Unpolarized 0.8 σ= σ= σ= σ= L/S(nm) Courtesy of Canon 20
21 21
22 22 ArF ArF '04 NA 0.75~0.85 '05M~E NA: 0.93~ ~ 65nm Memory Logic '06M~'07B NA: 1.2~ ~ 55nm ('09 NA: ~ 45nm ) ArF ArF
23 23 EUV (1) ITRS 32nm/22nm 45nm nd EUV (13.4nm) OPC RET ISMT( ) VNL(Virtual National Laboratories), Intel( MET) MEDIA+, IMEC ASML EUVA ASET
24 EUV (2) EUV 10-20W 40-70W 115W MET Micro Exposure Tool) / Intel ( ) '05 ASML. Nikon Canon '06-'07 EUV 50 24
25 ML2(Maskless Lithography) (SoC) Time-to-Market (ES ) EB EB 2 (2-4 ) '07~'08 β 25
26 26 ML2 Multi e-beam System NEDO 50kV 32x32 ~2 wph MCC / 50kV 16 ~10 wph PML2 LEICA/IMS 100kV ~29000 ~5 wph MAPPER MAPPER Lithography 5kV ~10 wph
27 Multi e-beam system NEDO Project) Electron High speed blanking Multi beam deflection Reduction optics 32x32=1024beams Beam pitch : 2µm on wafer Source: NEDO HP Report No
28 CPU 1 st Generation MCC System with 16CCs GUN HV Controller (4x4) CC Lens Controller Digital Control Circuits Electron Gun (4x4) Blanking Deflectors CC-2 Rack CC-1 Rack High speed digital circuits for each CC ( DATA memory, PG, PC, CLK etc.) are in a rack of size about 400x400x400 mm 3. * Identical 16 racks for 16CC system. * Digital circuits ; 3000x1000x2000mm 3. Stage Controller CC-16 Rack 300mm Wafer Rectangular Apertures (4x4) Pre. Mask Deflector CP Masks (mounted on separated stage) Post Mask Deflectors Round Apertures Major Deflector (200x200 um 2 ) Minor Deflector (10x10 um 2 ) Position Sensor Wafer Stage 28
29 Throughput Estimation for 1 st MCC System Estimation of Throughput for 65nm Device VSB Flashes No. on 300mm Wafer(Gshots) 16CCs-VSB (WPH) 16CCs-VSB (WPH) Contact Via (Ave.) Wiring (Ave.) CCs 300 mm interval 75mm Isolation Gate Throughput (WPH) Dependent on CP patterns prepared on CP mask. Total VSB Flashes (G shots) 29
30 30 ArF ArF EUV ArF hp65nm hp45nm hp32nm EUV 32nm ML2
ｽﾗｲﾄﾞ ﾀｲﾄﾙなし
WG5: ArF NGL STRJ WS: March 5, 2004, WG5 Lithography 2 WG5 27 STRJ WS: March 5, 2004, WG5 Lithography 3 Outline 1. ITRS Lithography Roadmap 2. ArF (193nm), ArF F 2 (157nm),EUVL PEL (Leepl), EPL, ML2 Imprint,
第3節
Prolith 3.1 Post Exposure Bake PEB PC 1970 F.H.Dill [1-2] PC Aerial Image Image in Resist Latent Image before PEB Resist Profile Develop Time Contours Latent Image after PEB 1 NA PEB [3-4] NA Cr 2 3 (b)
2 76 MPU (MEF mask error factors) nm 9nmCD 14nmCD 2003 MEF 1.0(alt-PSM ) nmCD 5.5nmCD MPU OPC PSM 193nm 157nm 157nm (ROI) 193nm 157nm Ca
1 2003 2 CD 15 ITWG International technology working group[ ] ESH Environment, Safety, and Health[ ] TWG RET resolution enhancement techniques OAI off-axis illumination PSM phase shifting masks OPC optical
スライド 1
リソグラフィの最新状況 WG5 ( リソグラフィ WG) ルネサスエレクトロニクス ( 株 ) 内山貴之 - 内容 - WG5( リソグラフィ WG) の活動体制 ITRS 2011 リソグラフィの概要 リソグラフィの最新状況 まとめ 1 略語 NA Numerical Aperture CD Critical Dimension CDU CD Uniformity DOF Depth of Focus
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SoC -SWG ATE -SWG 2004 2005 1 SEAJ 2 VLSI 3 How can we improve manageability of the divergence between validation and manufacturing equipment? What is the cost and capability optimal SOC test approach?
13 EUVA EUV EUVLL (NEDO) EUV (EUVA) 10 EUVA EUV W EUV EUV LPP EUV DPP EUVA 2 Selete 26nm IMEC EUVA NEDO
13 EUVA EUV EUVLL 2002 6 (NEDO) EUV (EUVA) 10 EUVA 2002 2005 EUV 2007 2 2005 1050W EUV EUV LPP EUV DPP EUVA 2 Selete 26nm IMEC 1 2008 2010 EUVA NEDO EUVA EUV 2006 Selete EUVA 1. EUVA 436nm 365nm 1/17 KrF
テストコスト抑制のための技術課題－DFTとATEの観点から
2 -at -talk -talk -drop 3 4 5 6 7 Year of Production 2003 2004 2005 2006 2007 2008 Embedded Cores Standardization of core Standard format Standard format Standard format Extension to Extension to test
Original (English version) Copyright 2001 Semiconductor Industry Association All rights reserved ITRS 2706 Montopolis Drive Austin, Texas
INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2001 EDITION EECA, European Electronic Component Manufacturers Association () JEITA, Japan Electronics and Information Technology Industries Association
Potential Solutions
ITRS 2004 Update ITRS 2004 12 1 2004 ITRS Update,, - P. Gargini - - W. Arden - - H. Sohn - P. Gargini - 2004 ITRS Update 2004 Update Technology Node DRAM M1 2003 ITRS (hpxx ) 2004 Update Technology Node
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微細化は終わり? ー リソグラフィ技術の最新動向 ー WG5 ( リソグラフィ Working Group) 富士通セミコンダクター ( 株 ) 千々松達夫 - 内容 - WG5 の活動体制 デバイスメーカー微細化の状況 リソ微細化技術の状況 まとめ 1 WG5( リソグラフィ WG) の活動体制 -JEITA 半導体部会 / 関連会社 - 千々松達夫 / リーダー ( 富士通セミコンタ クター )
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1 2005 ArF(193 nm) CoO(Cost of Owership) CD(Critical Dimension) (Difficult Challenges) (Potential Solutions) 15 ITWG International technology working group[ ] FEP(Front End Processing) ESH Environment,
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/ Lithography Conventional DRC+Lithographic DRC (Metrology: SEM OPE ) CD-SEM IP CD-SEM Hot Spot 1 DRC: Design Rule Check CD-SEM: Critical Dimension-Scanning Electron Microscope Hot spot: Systematic defect:
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