16 2 27 0044095
1 1 1 3 FPGA 2 IF 3 IF BER BER i
1 1 2 7 2.1...................... 7 2.1.1 A/D,D/A............................ 9 2.1.2 CPU............................... 10 2.2............................ 11 2.2.1............................ 11 2.2.2 Digital Down Conversion(DDC).................... 12 2.2.3 Numerical Controlled Oscillator(NCO) Mixer............ 14 2.2.4 Low Pass Filter(LPF)......................... 14 3 16 3.1................................ 16 3.1.1.............................. 16 3.1.2............................ 17 3.1.3............................... 18 3.1.4.......................... 20 3.1.5................................. 22 3.2...................................... 26 3.2.1.................... 27 3.2.2.............................. 28 3.3 IF....................... 29 3.3.1.......................... 34 3.3.2 BER................... 34 3.3.3......................... 35 3.3.4 BER......................... 37 4 41 ii
42 43 iii
1 PHS LAN (SDR:Software Defined Radio) SDR 1 ( 1.1) 1.1: 1
SDR 1 1.2 Channel 1 Channel 2 1.2: 3 [ch/hz/m 2 ] [bit/s/hz/m 2 ] 2
10 200g 1.3 (ASK:Amplitude Shift Keying) (FSK:Frequency Shift Keying) (PSK:Phase Shift Keying) A cos(ω c t) S ASK (t) = A m (t) cos(ω c t) (1.1) S FSK (t) = A cos((ω c + ω m (t))t) (1.2) S PSK (t) = A cos(ω c t + θ m (t)) (1.3) ASK FSK ASK PSK ASK FSK (C/N) 3
PSK AWGN (BER) 1.4 BER (QAM:Quadrature Amplitude Modulation) APSK PSK QAM PSK C/N BPSK QPSK π/4shiftdqpsk 16QAM 4 3 1 0 1 1 0 Am(t)cos(ωct) Acos(ωct + θm(t) ) Acos((ωc + ωm (t)) t ) 1.3: 2 4
10-2 10-3 BER 10 10-4 -5 10-6 10-7 4 6 8 10 12 14 16 18 SNR (db) 1.4: BER FPGA FPGA(Field Programable Gate Array) FPGA SRAM SRAM 1.5 HDL(Hardware Discription Language) VHDL 5
IOB Logic Block 1.5: FPGA FPGA ASIC(Application Specific Integrated Circuit) LSI ASIC FPGA ASIC FPGA 2 IF 3 IF BER BER 4 6
2 (Anarog to Digital Convertion;ADC) A/D (Digital to Anarog Convertion;DAC) D/A IF(Intermediate Frequency) 2.1 A/D 4 A/D 2.1 RF(Radio Frequency) DBF IF IF A/D IF FPGA (DDC) I,Q(In-phase,Quadrature-phase) CPU(Central Processing Unit) PC 7
RF DBF IF A/D FPGA CPU PC 2.1: 2.2 A/D,D/A CPU 2 2.3 2.2: 8
A/D,D/A D/A FPGA RF DBF IF A/D CPU FPGA CPU PC 2.3: 2.1.1 A/D,D/A 2.4 4 A/D 2 D/A 2 DAC 4 ADC 1 DAC IF D/A 14bit A/D IF ADC 12bit IF FPGA DDC A/D D/A 40MHz 9
FPGA DA1 DA2 AD1 AD2 AD3AD4AD4 2.4: A/D,D/A 2.1.2 CPU CPU Hitachi SH4 200MHz Transmission Control Protocol/Internet Protocol(TCP/IP) Ethernet port(100base-t) OS NetBSD PC 2.5 10
CPU FPGA 2.5: CPU 2.2 2.2.1 RF IF IF RF 0 DC IF 2.6 (a) RF A/D I,Q 11
RF A/D (b) RF IF A/D Low-IF I,Q IF A/D (c) IF I,Q A/D I,Q A/D (a) RF A/D RF I FPGA CPU Q Baseband (b) RF Down Conversion IF A/D IF I FPGA CPU Q Baseband (c) RF Down Conversion IF I A/D A/D Q Baseband FPGA CPU 2.6: 2.2.2 Digital Down Conversion(DDC) 40MHz 2.6 (b) Low-IF 10MHz IF 4 IF Numerical Controlled Oscillator(NCO) Mixer Low Pass Filter(LPF) Digital Down Conversion(DDC) I,Q DDC 12
2.7 A/D IF x IF (n) 90 x IF (n) =x I (n) cos ω c n + jx Q (n) sin ω c n (2.1) x I (n) x Q (n) x IF (n) I Q ω c IF x IF (n) [cos ω c n j sin ω c n] x IF (n) = x IF(n)[cos ω c n j sin ω c n] (2.2) = 1 2 [x I(n)+x I (n) cos 2ω c n jx I (n) sin 2ω c n jx Q (n)+x Q (n) sin 2ω c n + jx Q (n) cos 2ω c n] (2.3) x IF (n) LPF x LP F (n) = 1 2 [x I(n) jx Q (n)] (2.4) IF I,Q DDC 2.7 cos (ωc n) LPF xi (n) x(n) IF A/D NCO LPF - jsin (ωc n) xq (n) f c f c f s f c 2 f c 2.7: Digital Down Conversion 13
2.2.3 Numerical Controlled Oscillator(NCO) Mixer DDC 2.7 LO sin,cos NCO Mixer NCO 2.8 cos ωn = {1, 0, 1, 0}, sin ωn = {0, 1, 0, 1} Mixer IF I,Q CLK (4 IF) x(n) -1-1 x(n) 0 - x(n) 0 0 - x(n) 0 x(n) I Q x(n) cos( 2π n) 4 2π x(n) -sin( n) 4 x(n) x(n-3) -x(n-2) x(n-1) x(n) 2π x(n) cos( n) 4 2π x(n) -sin( n) 4 x(n-3) 0 -x(n-1) 0 0 -x(n-2) 0 x(n) 2.8: NCO Mixer 2.2.4 Low Pass Filter(LPF) 2.3 2.4 NCO Mixer I,Q 2.7 I,Q LPF LPF FIR(Finite Impulse Response) 8 8 y(n) = h(n)x(n) (2.5) n=1 14
y(n) x(n) h(n) FIR 2.9, 2.10 140 120 100 Time Step 80 60 40 20 0 1 2 3 4 5 6 7 8 Time Step 2.9: LPF 60 Time Step 40 Magnitude (db) 20 0 Time Step -20-40 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) 2.10: LPF 15
3 I,Q CPU IF IF 3.1 D/A IF D/A IF IF MATLAB 3.1.1 3.1 bit 2bit S/P(Serial to Parallel) BPSK QPSK π/4dqpsk 16QAM LO IF DAC IF A/D ADC IF IF NCO LO I,Q LPF I,Q 16
CPU P/S(Parallel to Serial) BPSK S/P,P/S I,Q Binary Data Serial/Parallel (2bit) BPSK : Serial Maping QPSK π/4shiftdqpsk BPSK 16QAM Filtering (Up Sampling) NCO D/A Binary Data Parallel/Serial (2bit) BPSK : Serial Demaping Filtering A/D NCO 3.1: 3.1.2 D/A IF 1 A/D D/A D/A A/D BPSK QPSK π/4dqpsk 16QAM 3.2 BPSK Sync (32 bit) Data (104 bit) QPSK π/4dqpsk Sync (32 bit) Sync (32 bit) Data (240 bit) Data (240 bit) 136 symbol 16 QAM Sync (32 bit) Data (512 bit) 3.2: 17
32bit 1 bit 136 ( 3.1) 3.1: bit, symbol, frame [bit/symbol] [bit/frame] [symbol/frame] BPSK 1 136 136 QPSK 2 272 136 π/4dqpsk 2 272 136 16QAM 4 544 136 3.1.3 3.1 1 bit bit BPSK 3.3 1bit (0,1) (0,π) 2 QPSK 2bit (00,01,11,10) (π/4, 3π/4, 3π/4, π/4) 4 3.4 π/4dqpsk 2bit (00,01,11,10) (π/4, 3π/4, 3π/4, π/4) 3.5 16QAM 1 4bit QPSK (00,01,11,10) 2bit I Q I,Q (-3,-1,1,3) 4 3.6 18
Q Q 01 1 00 1-1 0 1 I -1 1 I 11-1 10 3.3: BPSK 3.4: QPSK -1 1 01 Q 11 00 10 1 I Q 3 1-3 -1 1 3-1 10 11 01 I -1 3.5: π/4dqpsk -3 00 01 11 10 3.6: 16QAM 00 19
3.1.4 2 (ISI:Inter Symbol Interference) ISI T ( 0) 2MHz 40MHz D/A 20 MATLAB α=0.5 2 81 20 20 20 3.7 I,Q 1 19 0 3.8 3.9 Amplitude 1 0-1 [2MHz] t (Sample) [40MHz] 3.7: 20
1 0.8 Amplitude 0.6 0.4 Magnitude (db) 0.2 0-0.2 0 10 20 30 40 50 60 70 80 40 20 0-20 -40-60 -80 Time (sample) 3.8: -100 0 2 4 6 8 10 12 14 16 18 20 Freqency [MHz] 3.9: 21
3.1.5 BPSK BPSK 1bit (1,0) NRZ(NonReturn to Zero) (-1,1) Q 3.3 3.1.4 136bit 2720 3.10 BPSK I(n) IF x IF,BP SK (n) x IF,BP SK (n) = exp (jω c n) I(n) (3.1) = I(n) cos ω c n + ji(n) sin ω c n (3.2) IF 3.2 Re[x IF,BP SK (n)] = I(n) cos ω c n (3.3) (1, 0) NRZ (-1, 1) LPF I (n) cos (ωc n) xif (n) NRZ : NonReturn to Zero NCO 3.10: BPSK QPSK QPSK 3.11 QPSK S/P 2bit 2bit 1 3.2 Gray 3.4 BPSK 20 272bit 2720 22
3.2: QPSK 2bit Gray Gray 00 00 π/4 01 01 3π/4 10 11-3π/4 11 10 -π/4 QPSK I,Q I(n)+jQ(n) IF x IF,QP SK (n) x IF,QP SK (n) = exp (jω c n) (I(n)+jQ(n)) (3.4) = I(n) cos ω c n Q(n) sin ω c n + j(i(n) sin ω c n + Q(n) cos ω c n) (3.5) IF 3.5 Re[x IF,QP SK (n)] = I(n) cos ω c n Q(n) sin ω c n (3.6) Gray (-1, 1) LPF I (n) cos (ωc n) (1, 0) S / P (-1, 1) LPF Q (n) NCO -sin (ωc n) xif (n) 3.11: QPSK π/4dqpsk π/4dqpsk 3.12 QPSK S/P 2bit 10 π/4 23
20 2720 I,Q n θ n θ n = ± π 4, ±3 4 π (3.7) n θ n φ 0 10 m n =(0, 1, 2, 3) θ n θ n = θ n 1 + m n 2 π + φ 0 (3.8) = θ 0 + π n m i + n 2 i=1 4 π (3.9) = θ n + n 4 π (3.10) n 1 θ n = θ 0 + π m i + m n 2 i=1 2 π (3.11) = θ n 1 + π 2 m n (3.12) x(n) x(n) = exp (jθ n ) exp (j k π)=i(n)+jq(n) (3.13) 4 (3.14) I(n)+jQ(n) IF x IF,π/4 (n) 3.4 x IF,π/4 (n) = I(n) cos ω c n Q(n) sin ω c n + j(i(n) sin ω c n + Q(n) cos ω c n) (3.15) IF 3.6 Re[x IF,π/4 (n)] = I(n) cos ω c n Q(n) sin ω c n (3.16) 24
LPF I (n) cos (ωc n) (1, 0) S / P LPF NCO xif (n) Q (n) -sin (ωc n) 3.12: π/4dqpsk 16QAM 16QAM 3.13 3.11 QPSK 2bit S/P QPSK I Q 1bit 2bit 1 16QAM I Q 2bit 4bit 1 I,Q 4 16 I,Q 3.3 Gray 3.6 544bit 2720 I,Q 3.3: 16QAM 2bit Gray 2bit 2bit 00-3 00-3 01-1 01-1 11 1 11 1 10 3 10 3 16QAM I,Q QPSK IF IF IF 3.4, 3.6 x IF,QAM (n) = I(n) cos ω c n Q(n) sin ω c n + j(i(n) sin ω c n + Q(n) cos ω c n) (3.17) 25
Re[x IF,QAM (n)] = I(n) cos ω c n Q(n) sin ω c n (3.18) Gray LPF I (n) cos (ωc n) (1, 0) S / P -3, -1, 1, 3) LPF Q (n) NCO -sin (ωc n) xif (n) 3.13: 16QAM FPGA FPGA 3.1.5 IF Re[x IF (n)] MATLAB D/A 14bit Re[x IF (n)] Re[x IF (n)] = floor( Re[x IF(n)] (2 13 1) + 2 13 ) (3.19) M floor 0 MATLAB M Re[x IF (n)] Re[x IF (n)] M (2 13-1) +2 13 0 1 2 14 1 3.2 A/D FPGA ADC IF 2.7 DDC I,Q 26
FPGA CPU 3.2.1 D/A 16 3.14 x Ref 1 Sync cor i r x i x i x i r cor i = (3.20) (x i x i ) (r r ) 3.20 cor i 3.15 20 Ref x r x1 x2 Sync Data xi 27
3.14: Correlation Coefficient 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 10 20 30 40 50 60 70 80 90 100 Sample Index 3.15: 3.2.2 2720 136 I,Q 3.16 3.1.3 π/4dqpsk 1 16QAM I,Q 2bit 4bit 28
Q Q 01 00 1 0 I I 11 10 BPSK QPSK Q Q 01 00 11 10 I 10 11 I 01 π/4dqpsk 3.16: 00 01 11 10 16QAM 00 3.3 IF 3.17 D/A A/D IF 29
ADC:40MHz IF 10MHz A/D FPGA CPU BPSK DDC FIFO Frame QPSK Sync π/4dqpsk 16QAM 2720 samples 136 symbols Decoding Decoding Decoding Decoding D/A DAC:40MHz Modulation Data PC 3.17: IF Demodulation Data 1 BPSK QPSK π/4dqpsk 16QAM IF D/A A/D IF DDC D/A 14bit MATLAB 3.18 D/A D/A IF A/D IF ADC DDC I,Q 3.18 I,Q 30
I,Q I,Q A/D,D/A 3.18: A/D,D/A 14bit IF A/D 12bit ADC 10MHz (NCO) QPSK 3.19 3.20 LPF I,Q 3.21 3.22 3.4 3.22 3.16 2bit 31
Amplitude 2500 2000 1500 1000 500 0-500 -1000-1500 -2000-2500 0 50 100 150 200 250 300 Time [sample] 3.19: NCO I,Q In-phase Quadrature Amplitude 2500 2000 1500 1000 500 0-500 -1000-1500 -2000-2500 0 50 100 150 200 250 300 Time [sample] 3.20: LPF I,Q In-phase Quadrature 32
2000 1500 Amplitude (Quadrature) 1000 500 0-500 -1000-1500 -2000-2000 -1500-1000 -500 0 500 1000 1500 2000 Amplitude (In-phase) 3.21: I,Q Amplitude (Quadrature) 2000 1500 1000 500 0-500 -1000-1500 -2000-2000 -1500-1000 -500 0 500 1000 1500 2000 Amplitude (In-phase) 3.22: I,Q 33
3.3.1 D/A A/D 3.1.2 D/A 20 BPSK QPSK π/4dqpsk 16QAM 2720 3.3.2 BER IF 3.23 3.24 0 1 (AWGN:Additive White Gaussian Noise) DDC IF SNR per bit(e b /N 0 ) BER(Bit Error Rate) E b bit N 0 AWGN S T, bb IF D/A A/D DDC S R, bb 3.23: 34
12000 10000 8000 6000 4000 2000 0-5 -4-3 -2-1 0 1 2 3 4 5 Histogram 3.24: AWGN 3.3.3 3.3 3.6 2 BER 3.25 16QAM A A D/A A/D 3.19 M M M max A/D I,Q 3.26 3.25 35
Q Q A I A I BPSK QPSK Q Q A I A I π/4dqpsk 16QAM 3.25: 36
BPSK QPSK π/4dqpsk 16QAM 3.26: A/D I,Q 3.3.4 BER A E b /N 0 BER BPSK A/D BPSK I,Q x i,x q x i = u i + n i0, x q = 0 (3.21) 37
u i n i0 n i AWGN AD AWGN P s P N0 P N P s = E[u i 2 ]+E[n i0 2 ] (3.22) P N0 = E[n i0 2 ]=σ 0 2 P N = E[n i 2 ]=σ N 2 (3.23) (3.24) σ 0 σ N AWGN σ 2 = σ 2 0 + σ 2 N BPSK SNR SNR BPSK = P s P N0 P N0 + P N = A 2 σ 02 + σ N 2 = A2 σ 2 = 2E s N 0 (3.25) E s 1 E s = E b = A 2 (E b /N 0 ) BPSK (E b /N 0 ) BPSK = 1 2 SNR BPSK = 1 P s P N0 (3.26) 2 P N0 + P N 3.26 P s,p N 0 A/D I,Q E b /N 0 [db] P N 3.24 AWGN σ N A/D E b /N 0 [db] BER QPSK,π/4DQPSK BPSK x i = u i + n i0, x q = u q + n q0 (3.27) P s = E[u i 2 + u q 2 ]+E[n i0 2 + n q0 2 ] (3.28) P N0 = E[n i0 2 + n q0 2 ]=2σ 0 2 (3.29) P N = E[n i 2 + n 2 q ]=2σ N 2 (3.30) SNR QP SK = P s P N0 P N0 + P N = A 2 2σ 02 +2σ N 2 = A2 2σ 2 = E s N 0 (3.31) QPSK E s =2E b = A 2 (E b /N 0 ) QP SK (E b /N 0 ) QP SK = 1 2 SNR QP SK = 1 P s P N0 (3.32) 2 P N0 + P N 38
QPSK 3.32 BPSK P N 3.30 σ N E b /N 0 [db] BER π/4dqpsk QPSK 3.32 BER 16QAM 16QAM QPSK SNR SNR 16QAM = P s P N0 P N0 + P N = A 2 2σ 02 +2σ N 2 = A2 2σ 2 = E s N 0 (3.33) E s =4E b = A 2 3.32 16QAM SNR(E b /N 0 ) (E b /N 0 ) 16QAM = 1 4 SNR 16QAM = 1 P s P N0 (3.34) 4 P N0 + P N 16QAM 3.34 BPSK,QPSK P N P N = E[n 2 i ]=σ 2 N σ N E b /N 0 [db] BER BER 3.27 AWGN 3.27 BER P N,BPSK (γ) = 1 2 erfc( γ) (3.35) P N,QP SK (γ) = 1 2 erfc( γ) (3.36) P N,π/4DQP SK (γ) = erfc( γ) (3.37) P N,16QAM (γ) = 3 2 8 erfc( 5 γ) 9 2 64 erfc2 ( γ) (3.38) 5 γ = A 2 /2σ 2 1bit erfc erfc(x) = 2 e t2 dt (3.39) π 3.27 BPSK QPSK π/4dqpsk 16QAM BER x 39
AWGN BER 10 0 10-1 10-2 BER 10-3 10-4 10-5 Theory BPSK Measured BPSK Theory QPSK Measured QPSK Theory π/4 DQPSK Measured π/4 DQPSK Theory 16QAM Measured 16QAM -5-3 -1 1 3 5 7 9 11 13 15 SNR per bit (Eb/No) (db) BER 3.27: Bit Error Rate 40
4 SDR A/D,D/A BOX A/D D/A FPGA CPU Low-IF IF DDC I,Q A/D,D/A BOX IF D/A BER BER BPSK QPSK π/4dqpsk 16QAM BER AWGN BER 4 IF RF 41
D2 (Minseok Kim), 42
[1], Blind B Vol. J84-B No.7 pp.1151-1162 2001 7. [2],,. CS,, Vol. 98 Num. 650 pp.31-38 (1999.03) [3],,. SAT,, Vol. 101 Num. 540 pp.25-30 (2002.01) [4],,. DSP,, Vol. 97 Num. 582 pp.29-36 (1998.03) [5] S Mukthavaram, Design and FPGA Implementation of an Adaptive Demodulator,B.S.E.E Osmania University, Hyderabad, India, 1997 [6] S.S. JENG, S.M. CHANG, B.S. LAN, Multi-Mode Digital IF Downconverter for Software Radio Application,IEICI TRANS. COMMUN., VOL.E86-B, NO.12, pp.3498-3511, DEC. 2003. [7], A Study of Implementation of Digital Signal Processing for Adaptive Array Antenna, 14 2. [8], 15 2. [9], 15 2. [10],, 14 2. 43
[11], [12],,MWE 2003 Microwave Workshop Digest. [13], [14], [15], [16] Inter face, CQ, 2001 10. 44