/ / SeamlessCVE
From ASIC to SoC Original Hardware Content CPU Core Memory DSP Core Glue Logic PCI Controller Original Hardware Content USB Controller USART Slide 2
SoC SoC ASIC System Architecture ASIC Architecture HWR SWR RTL Model Test Vectors ASIC IP DRIVERS RTOS App RTL Verification SoC Verification Slide 3
/ Hardware Development Physical Implementation Software Development Software Development 1 3 System Integration Release to Manufacturing Slide 4
Seamless CVE SW Simulation HW Simulation Performance Optimizations SW Debug System Control HW Debug Slide 5
API: ISS - SeamlessCVE - Logic Simulator MPU Seamless ALLIANCE 2000 MPU C OK QuickSimII ModelSim(QuickHDL/V-System) SimExpress Cadence Verilog-XL Leapfrog ViewLogic/Synopsys IKOS Avant! Polaris QuickTurn SpeedSim Slide 6
CLK RW DC MREQ IOREQ ADDRESS DATA CLK RW DC MREQ IOREQ ADDRESS DATA CLK RW DC MREQ IOREQ ADDRESS DATA CLK RW DC MREQ IOREQ ADDRESS DATA 0055 0100 0101 0102 XXXX 5C7D 0055 5C7E 002A ZZZZ ZZZZ 6030 6031 0055 002A ZZZZ 0055 002A ZZZZ Fetch @ 0101 Memory Read @ 6031 Fetch @ 0102 Fetch @ 5C7D IO Write @ Port 55 Wait 4 clocks - Memory Read @ 6031 Wait 8 clocks - Wait 4 clocks - IO Write @ Port 55 Wait 4 clocks - Wait 2 clocks - Wait 4 clocks - Wait 4 clocks - IO Write @ Port 55 IO Write @ Port 55 IO Read @ Port 2A Slide 7
Slide 8 Bl oc k_ A Bloc k_b while (ctl == 0) { check_irq(); count++; check_others() j++; } Instruction Set Simulator Co-Simulation Manager ASIC MPU I/O RAM DMAC ROM FIFO
Slide 9 R/W I/O Instruction Set Simulator Co-Simulation Manager ASIC MPU I/O RAM DMAC ROM FIFO
/ HCE Mode CPU State Tracking HWR Debug Probe Memory Model I/F ModelSim Support V2.2 V2.3 V2.4 V2.5 JAN-98 PATCH Y2K Compliance GreenHills Support IKOS Voyager Support NC Verilog Support VCS Support AUG-98 V3.0 Q4-98 PATCH V3.0 Highlights Performance Multiple Processors DSP Support RTOS Support Openness Other Slide 10
FOE Load code Run diagnostics Data intensive algorithm Periodic interrupt service Collect ASICs output Feed into algorithm Session average SBE Setup ASIC#1 Setup ASIC#2 ASICs active CPU is slave == (FOE) == (SBE) Seamless V3.X: 2-3X V2.X FOE Slide 11
V2.X DUAL 940T ported Xray3.6 memory Glue CPU Logic V3.X Memory C54 USB Controller PCI Controller USART Slide 12
V3.0 DSP & (DSP ):... Slide 13
DSP TI C54 Core (C-Lead) -- @ TI-Dallas C54-10 (Lead-3) -- @ TI-Bangalore SPX-DSP--- DSP16000 -- 9 OAK --- Teak-Lite -- MGC-Wilsonville Motorola 56600/Onyx Core -- 9 (?) ADI SHARC 21020 -- 4Q97 Slide 14
RTOS HCE ISS - RTOS RTOS RTOS RTOS RTOS Slide 15
V3.0 RTOS RTOS RTOS RTOS RTOS RTOS- TCB ( ) XRAY : PSOS VRTX SPI TCB Slide 16
(, ) CVE --!! Slide 17
SPI: Seamless Plug-in Interface SYMBOL TABLES ADDRESS SPACES Request addresses of variables Receive addresses of variables Set values in memory Get values from memory Register callback(s) with one or more address Activate callbacks S P I SPI APP#1 (ex: memory usage monitor) SPI APP#2 (ex: virtual keypad) CVE Memory Image Server, read/write SPI X-Window Slide 18
Run/Stop/Step BIM BIM CVE CVE Kernel PSP CVE Platforms WinNT (3.1) Slide 19
Seamless Altia: SPI / SPI GHS: GHS Seamless WRS: RTOS VxSim I/O Seamless FORESIGHT: SPI CVE Slide 20
i960k, j, h, c, s, rp i8x5x, i80386sx, i80486dx 68000, 68020, 68030, 68040, 68ec040, 68302, 68340, 68360 PPC 603e, PPC 740, 750, MPC860SAR Coldfire2, 3, MCore sh7032, sh7050, sh7604, sh7708 ARM7tdmi ARM920T, 940T PPC403 V851, NA85E SPX-DSP Z180 OAK,Teak-Lite TX39 MiniRISC 4001,20 TinyRISC 4102 MN10300X M32R C165 ST20 ADSP21020 AVR90 C54 Core (C-Lead) C54-10 (Lead-3) Slide 21
Seamless Lite Denali Seamless Seamless CVE Seamless Lite New Seamless upgrade New Slide 22
Software Hardware SW Abstractions/RTOS & SDL Native Compiled Simulation Instruction Set Simulation Seamless Co-Designer Seamless CVE today Data Flow Simulation Transaction level Hardware Emulation Hardware acceleration Cycle Simulation Timing Simulation Slide 23
Slide 24
Slide 25 / C HDL / / &
Foresight procedural code Slide 26
Slide 27
Slide 28 Co-designer V1.0 & I/F CVE / H/S Foresight
Seamless Co-designer V1.0 CVE Foresight Foresight / CVE compiled software CPU Slide 29
Seamless Co-Designer Foresight Foresight HW SW Slide 30