Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 1
WG1: NEC STARC STARC Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 2
WG1 ITRS Design System Drivers SoC EDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 3
Design System Drivers Design WG1 Design process, System-level design, Logical/physical/circuit design, Design verification, Design for test System Drivers System Drivers ORTC ITRS ORTC =Overall Roadmap Technology Characteristic LSI SoC SoC Multi-Technology High-Performance, Cost-Driven Processor Mixed-Signal Memory SoC Low Power PDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 4
Canonical Design Flow ITRS US/EU Canonical Design Flow SoC WG1 2003 ITRS ITRS» Canonical Design Flow» RTL SW/HW Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 5
Full/Semi-Automated Handcraft Files, Documents System Requirement Analysis System Requirement Specification System Function Design System Architecture Design HW Specification SW Specification Micro Architecture Design(Block Partition) Block Level Specification RTL Design Software Development Modeling Verification RTL Models & Constraints Logic synthesis & Place-and-Route Mask Data Hardware Development Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 6
RTL System Requirement Analysis System Requirement Specification Full/Semi-Automated Handcraft Files, Documents System Function Design System Architecture Design HW Specification SW Specification Micro Architecture Design(Block Partition) Modeling Verification Changed Behavior Models & Constraints RTL Synthesis RTL Models & Constraints Software Development Logic synthesis & Place-and-Route Hardware Development Mask Data Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 7
HW/SW System Requirement Analysis Full/Semi-Automated Handcraft Files, Documents System Requirement Specification System Function Design Modeling Verification Changed System Behavior Model Design Constraint HW/SW Co-Synthesis Behavior Models & Constraints RTL Synthesis RTL Models & Constraints SW Source Code Software Development Logic synthesis & Place-and-Route Mask Data Hardware Development Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 8
WG1 WG1 SoC SoC 2003 ITRS SoC Time-To-Market Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 9
WG1 ITRS Design System Drivers SoC EDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 10
Time-To-Market SoC IP EDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 11
SoC SoC 82 45 SoC R. Collett, 01 11 Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 12
SoC Source: Aart de Geus, Chairman & CEO of Synopsys, Boston SNUG keynote address Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 13
WG1 SoC SoC 88 1 1 Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 14
85 EDA CAD Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 15
Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 16
WG1 ITRS Design System Drivers SoC EDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 17
IP Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 18
Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 19
LSI Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 20
IP Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 21
EDA CAD EDA EDA RTL Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 22
EDA 100% = Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 23
EDA LSI LSI EDA LSI Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 24
Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 25
: Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 26
WG1 ITRS Design System Drivers SoC EDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 27
SoC SoC SoC CMM 1 SoC CMM = The Capability Maturity Model SoC Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 28
EDA CAD EDA EDA 1985 1985 1995 1995 Next Next EDAEDA EDA EDA EDA EDA EDA ASIC EDA EDA EDA EDA ESD EDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 29
CMOS IR A B C A B SoC C Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 30 D
WG1 ITRS WG1 SoC EDA Work in Progress - Do not publish STRJ WS: March 4, 2004, WG1 31