0 7, LHC ATLAS CMS σ Higgs. 000,.,,..,.,. ATLAS,,.,,. FPGA TCP/IP,,. FPGA, 0Gbps.,., ATLAS.,,.

ATLAS 0

0 7, LHC ATLAS CMS σ Higgs. 000,.,,..,.,. ATLAS,,.,,. FPGA TCP/IP,,. FPGA, 0Gbps.,., ATLAS.,,.

LHC ATLAS. LHC............................................. LHC...................................... LHC............................ ATLAS................................................................................................................................................ 7........................... 8........................................................................................................... Level Trigger................................... High Level Trigger................................ ATLAS.................................... Standard Model Higgs............................. 6.. Higgs................................. 7.. Higgs................................. 8.............................. 9............................... LHC.................................. Long Shutdown (0-0)........................... Long Shutdown (08).............................. Long Shutdown (0).............................6 ATLAS...............................6. phase-0......................................6. phase-......................................6. phase-..................................... 7 9. TGC...................................... 9.. TGC................................. 9.. TGC................................... 0.. TGC..................................... TGC.....................................................................

.. p T.................................................................. Coincidence Window.............................................................. 6.................................... 6................................... 8.. HSC.................................. 0.. SL..................................... SL.................................6 TTC................................................................................................................................. phase-0................................ 6.. phase-................................ 6.. phase-................................ 8..6....................... 9 60. TCP/IP............................... 60.................................... 60.. TCP/IP..................................... 6.. UDP....................................... 6. SiTCP.......................................... 6......................................... 6.. TCP............................... 6. Gbps............................... 66..................................... 66.................................... 69.................................... 7.................................... 7. 00Mbps............................. 7..................................... 7.................................... 76................................... 76............................................ 77 GTX Transceiver 79............................. 79.. Xilinx Multi-Gigabit Transceiver....................... 79.. GTX Transceiver................................ 80................................... 8....................................... 8

.. KC70............................... 8.................................... 8. GTX Transceiver................................ 86..................................... 86................................... 89.............................. 9.................................. 9............................................ 97 Sector Logic 98. Sector Logic...................... 98............................... 98.. New Small Wheel.......................... 99.. Sector Logic............................. 00. PT7....................................... 0....................................... 0................................... 0.. PT7................................... 0................................. 06.. FPGA...................................... 06.. CPLD...................................... 07.. Ethernet PHY................................. 07.. DDR SDRAM................................. 08.. Flash memory................................. 08..6..................................... 09................................ 0.. VME.................................... 0............................................................................................. TTC.........................................6 I/O............................................................................................................................................... 6 6 A 7 A................................. 7 A................................... 7 A. 0/00/000BASE-T.................................. 8 A................................. 9

A............................... 0 B PT6 B........................................ B............................................ B........................................... C PT7 D List of abbreviations

. LHC []...................................... LHC []................................... ATLAS ( ), CMS ( )[]........................ ALICE ( ), LHCb ( )[]........................ ATLAS [6].................................6 ATLAS []...............................7 ID[6]...................................... 6.8 [6]..................................... 7.9 [6]............................ 8.0 r z (Large sector)[6]................... 0., [6]............................ []...................... TDAQ [6]...................................... L [6]................................. TTC [].............................6 0 7 [].............................7 Higgs []................................... 7.8 Higgs [].................................. 8.9 Higgs [].................................. 8.0 []................................ 0. [].................................. D []................................... []................................. IBL []............................... [].............................6 MicroMegas []................................7 High Granularity Calorimeter Trigger[]...................... 6.8 FTK [].............................. 7.9 ID [6]............................... 8. TGC [6]................................... 9., [6].......................... 0. Big Wheel[6]....................................... TGC [6]..................................... TGC [][9]...................6 p T []..................................

.7 []...............................8 CW [9].......................................9 []................................... 7.0 BW PS HSC [].......................... 7. USA [].................................. 7. PS [].................................. 8. ASD []..................................... 9. HpT []..................................... 0. SL []...................................... 0.6 SL []...................................7 [].................................8 SSW []......................................9 ROD [].....................................0 L MU0 η [7].................................. dθ, dl................................. 7. dθ, dl [7]................................ 7. phase- []............................. 8. phase- [8]........................ 9. SiTCP [6]................................ 6. TCP..................................... 6. Wireshark..................................... 6. Gbps................................... 67. G RTT.................................. 67.6 PT6................................. 68.7 PC................................... 68.8 G ( : Nagle on, : Nagle off)...... 7.9 MSS....................... 7.0 Nagle off........................... 7. G ( : Nagle on, : Nagle off)...... 7........................................ 7. flood................................... 7. LAN.................................. 7. 00Mbps.................................. 76.6 00M.................. 77. GTX TX [9].............................. 80. GTX RX [9].............................. 8. DFE [9]................................. 8. KC70...................................... 8. [6]................................ 8.6 [6]............................... 8.7 Fusion Digital Power Designer GUI....................... 86 6

.8.................................. 88.9 VCCINT................................. 88.0 MGTAVCC............................... 89. MGTAVTT............................... 89. XADC.................................. 90. FPGA.................................. 9. IBERT....................................... 9. PRBS-7................................... 9.6 [9]................................. 9.7 [9].......................... 9.8 m............................... 9.9 m............................... 9.0 7m............................... 9. 9m............................... 9. m.............................. 9. m.............................. 9. CTLE [9]................................. 96. CTLE +.......................... 97. SL............................. 99. NSW [].................................... 99. BW NSW sector []........................... 0.................................. 0. PT7................................... 06.6 DDR SDRAM [6]............................ 08.7 Infiniband........................8..................................9 TTCrq.......................................0 PT7................................... PT7..................................... 6. ATLAS [].................................... 6 B. PT6 [8]..................................... B. PT6 [8].................................. B. raw data monitor................................ C. PT7 ().................................... C. PT7 ().................................... 6 C. PT7 ().................................... 7 C. PT7 ().................................... 8 C. PT7 ().................................... 9 C.6 PT7 (6).................................... 0 C.7 PT7 (7).................................... 7

C.8 PT7 (8).................................... C.9 PT7 (9).................................... C.0 PT7 (0)................................... C. PT7 ()................................... C. PT7 ()................................... 6 C. PT7 ()................................... 7 C. PT7 ()................................... 8 C. PT7 ()................................... 9 C.6 PT7 (6)................................... 0 8

. LHC []................................... LHC................................. ID [7]....................................... 7. [8]........................ 9. (Large sector)[8]........................ 0.6,............................. 0.7 HL-LHC................................ L p T............................ [].............................. 7. SLB ASIC [].................... OSI..................................... 60. RBCP [7]................................ 6............................... 69. SiTCP and TCP control register........................... 69. G (Mbps).................. 70.6 G (, Mbps)........... 7.7 G (, Mbps)........... 7.8 00M (Mbps)................. 76.9 00M (Mbps)............... 77. Xilinx MGT............................... 79. GTX [9]......................... 8. KC70 GTX [].............................. 8. KC70 []................................ 87........................... 88. SL............................... 0. SL................................ 0. Kintex-7 []............................ 07. PT7.................................. 09. PT7.................................. 0.6 VME................................ A................................. 8 A. [66]............................... 8 9

A........................... 0 A............................ 0 B. Spartan-6 []............................ C. PT7.......................... C. PT7................................ D. List of abbreviations.................................. 0

LHC ATLAS ATLAS,. LHC ATLAS,.. LHC ATLAS, ATLAS, LHC... LHC LHC Large Hadron Collider 00m,.. LHC. LEP 7km CERN. - LEP, -. 0 TeV,..: LHC [] Large Electron-Positron collider: CERN 989 000 -. 00GeV Counseil Européen pour la Recherche Nucléaire:

. LHC ( )., LHC. 0 TeV, 7.7 0 cm s..: LHC [] 6.7 km 8. T 7 TeV 0 cm s.9 ns. 0 ID 6 808 LHC,. Linac. PS (Proton Synchrotron), PS Booster.GeV. PS, SPS (Super Proton Synchrotron) 0GeV, LHC... Length Energy Linac 0 m 0 MeV Booster 60 m. GeV PS 60 m GeV SPS 6.9 km 0 GeV LHC 7 km 7 TeV.: LHC [].. LHC LHC, ATLAS (A Toroidal LHC ApparatuS ) CMS (Compact Muon Solenoid). LHC,. 0 7-6GeV σ Higgs [][](ATLAS: 6GeV, CMS: GeV). ALICE (A Large Ion Collider Experiment) ( 08 Pb 8+ ), Quark Gluon Plasma (QGP)

る. LHCb (Large Hadron Collider beauty) では b クオークの物理に焦点を当て, B メソンにおけ る CP 対称性の破れの測定を行っている. ATLAS, CMS, LHCb, ALICE 実験についての概要を表. にまとめた. また, 各実験で用いら れている検出器の概略図を図.,. に示す. 表.: LHC で行われている実験 実験名 サイト ATLAS ALICE CMS LHCb point point point point 8 実験概要 大型汎用検出器による実験 重イオン検出器による QGP の物理 大型汎用検出器による実験 B メソンにおける対称性の破れの検証 図.: ATLAS 検出器 (左), CMS 検出器 (右)[] 図.: ALICE 検出器 (左), LHCb 検出器 (右)[] LHC を上空から見て 8 等分する点に point point 8 と時計回りに番号がついている. 各 point には検出器や ビームダンプが配置されている

. ATLAS ATLAS Higgs. 000,. m, m, LHC. ATLAS...,,,,.,...,. ATLAS, ( / ),.,,... ATLAS..: ATLAS [6]

ATLAS xyz rϕz. xyz, z, LHC x, y., ATLAS z A-side, C-side. rϕz, ATLAS. z, r, ϕ., η. θ. η = ln (tan (θ/)) η, ϕ,., ( ) ( ), η..6..6: ATLAS [].. (ID: Inner Detecor). ATLAS ID..7 ID., ID.. ATLAS,

.7: ID[6] ID,. Pixel, Semi-Conductor Tracker (SCT). Pixel., B layer, SCT. (p T ) ID. ID 6 Transition Radiation Tracker (TRT).,, B 6 6

X. X,..: ID [7] ( η ) (m ) (0 6 ) (µm) Pixel - B layer. 0. 6 rϕ :, z : 66 Pixel - Barrel.7. 8 rϕ :, z : 66 Pixel - Endcap.7. 0.7 rϕ :, z : 77 SCT - Barrel... rϕ : 6, z : 800 SCT - Endcap.. 6.7.0 rϕ : 6, z : 800 TRT - Barrel 0.7 0. 70/straw TRT - Endcap 0.7. 0. 70/straw.. ID.,..8..8: [6] (LAr).,. 7

η <.8,.8 < η <.. ( η <.7) Tile. (. < η <.) LAr Hadronic End-cap Calorimeter (HEC). (. < η <.9), Forward Calorimeter (FCal). LAr,, LAr... ATLAS,..9. ATLAS Precision Chamber Trigger Chamber. Precision Chamber (r z) 0µm. Trigger Chamber ns, p T, mm cm (ϕ)....9: [6] 8

Precision Chamber, Monitored Drift Tube (MDT). (. < η <.7), Cathod Strip Chamber (CSC). MDT 0mm, 0µm, 80µm., CSC.mm,.08mm MWPC 7, 60µm. 0Hz/cm MDT, 000Hz/cm CSC Trigger Chamber Resistive Plate Chamber (RPC), Thin Gap Chamber (TGC). RPC. ATLAS z ϕ, TGC (.8mm) (.mm) MWPC. ns r ϕ,.: [8] ( η ) (m ) (0 ) MDT.7 00 7 80 µm CSC.0.7 7 6.7 60 µm RPC. 60. mm TGC.0. 900 cm 7 Multi-Wire Proportional Chamber:. 9

,. (Inner, Middle, Outer), (I, M, O, Extra). B, E EM., EM Big Wheel (BW), EI Small Wheel (SW).,...: (Large sector)[8] ( η ) BI.0 MDT BM.0 MDT RPC RPC BO.0 MDT RPC RPC EI.0.0 MDT TGC.0.7 CSC CSC EM.0. MDT TGC TGC..7 MDT TGC EO..7 MDT EE.0. MDT.0: r z (Large sector)[6], 8 ϕ 6. 8 Large sector, 8 0

Small sector. Large, Small η,. Large sector..0 Large sector..., ATLAS. ATLAS....:, [6] ID z T. ϕ, ID p T. m. 8 ϕ 0.T. η, RPC p T. m... ϕ T, TGC p T.

., ATLAS (DAQ: Data Acquisition)..., TeV Higgs 0. ATLAS. ATLAS (TDAQ: Trigger and DAQ). 0 9 proton - (anti)proton cross sections 0 9 0 8 σ tot 0 8 0 7 Tevatron LHC 0 7 0 6 0 6 σ (nb) 0 0 0 0 0 0 0 0-0 - 0-0 - 0-0 -6 0-7 σ jet (E T jet > s/0) σ W σ Z σ jet (E jet T > 00 GeV) M H = GeV WJS0 { σ b σ WW σ σ t ZZ σ ggh σ WH σ VBF 0. 0 s (TeV) 0 0 0 0 0 0 0 0-0 - 0-0 - 0-0 -6 0-7 events / sec for L = 0 cm - s -.: [].. LHC 0MHz, 0.. σ tot minimum bias., QCD (Quantum Chromodynamics). GHz,. ATLAS 00Hz. Level (L) 7Hz, Level (L).kHz, Event Filter (EF) 00Hz, (.). L

.µs, L, EF. L, EF High Level Trigger (HLT). Interaction rate ~ GHz Bunch crossing rate 0 MHz LEVEL TRIGGER LVL < 7 (00) khz LA RoIs RoI Builder RoIB LVL Supervisor LSV CALO MUON TRACKING ROD ROD ROD ROB ROB ROB Pipeline memories Derandomizers Readout drivers (RODs) Read Out Links (ROLs) Read Out Systems (ROSs) latency. s 0ms LEVEL TRIGGER ~ khz LPs LVL Processors LVL & Event Builder Networks SFIs DFM Data Flow Manager Sub Farm Input sec EVENT FILTER ~ 00 Hz SFOs Sub Farm Output Mass Strage Data recording.: TDAQ [6].. Level Trigger L p T,,. p T TGC, RPC, /., Central Trigger Processor (CTP), Timing Trigger and Control distribution system (TTC) [9] L.. L. L.µs, 00 (L Buffer). CTP MU (muon), EM (electromagnetic), J (jet), Level Accept (LA). LA TTC L Buffer,., Read Out Driver (ROD). ROD, ROD ATLAS, Read Out System (ROS). ROS Read Out Buffer (ROB), L.,, Region of Interest (RoI) L. RoI L η ϕ, L.

Calorimeter Trigger Muon Trigger Front-end Preprocessor Endcap Muon Trigger (TGC based) Barrel Muon Trigger (RPC based) Cluster Processor (electron/photon and hadron/tau triggers) Jet/Energy-sum Processor Muon Trigger / CTP Interface Central Trigger Processor RoI Builder TTC.: L [6] TTC TTC /,. /, LA, ECR 8, BCR 9.., TTC Local Trigger Processor (LTP), TTCvi, TTCvx, ROD busy. LTP,. CTP /, TTCvx, TTCvi., LA,,..: TTC [] TTCvi A-Channel, B-Channel TTCvx. TTCvx TDM 0, 8 Event Count Reset: 9 Bunch Count Reset: 0 Time Division Multiplexing:

. RODbusy ROD busy, LTP CTP. busy ROD, LA. TTC, TTCrx ASIC. TTCrx TTC /. TGC, TTCrx TTCrq, L Buffer... High Level Trigger L L, L MDT, CSC, ID. 0ms, RoI ROS. L L, L Accept (LA). LA, ROS Sub Farm Input (SFI) buffer,. EF RoI. EF Sub Farm EF Farm,. EF Sub Farm SFI, sec. EF, Sub Farm Output (SFO) buffer,.. ATLAS ATLAS Higgs. Higgs 0. 0 LEP GeV, Tevatron 6-77GeV, LHC -76GeV 9%, 0. 9% CL Limit on µ 0-0 ATLAS 0-0 - s = 7 TeV: Ldt =.6-.8 fb - s = 8 TeV: Ldt =.8-.9 fb 0 0 ± σ ± σ Observed Bkg. Expected CL s Limits 00 00 00 00 m H [GeV] Local p 0 0 0 0 - - -6 0 0 0-0 0 - - -7-8 -9 ATLAS 0-0 0-0 0 0 0 - s = 7 TeV: Ldt =.6-.8 fb - s = 8 TeV: Ldt =.8-.9 fb Sig. Expected Observed σ σ σ σ 6 σ 00 00 00 00 m H [GeV].6: 0 7 [] Application Specific Integrated Circuit:, IC -. 6.km, TeV

0 7, ATLAS 6GeV (.6). Standard Model (SM) Higgs,. LHC Higgs, ATLAS... Standard Model Higgs SM Higgs. L = W µν W µν B µν B µν + Lγ (i µ µ g τ W µ g Y ) B µ L + Rγ (i µ µ g Y ) B µ R. 0, W ± Z 0, γ 0, ϕ SU() U(). ( L = i µ g τ W µ g Y ) B µ ϕ V (ϕ) V (ϕ) = µ ϕ ϕ + λ(ϕ ϕ) where µ < 0 and λ > 0. L = ( G LϕR + G Lϕ c R + Hermitian Conjugate ) ( ) ϕ = 0, ϕ c = iτ ϕ ν + h,. ν Higgs (6GeV). W, Z SM,. g ffh = m f ν g VVH = m V ν Higgs ( ), Higgs., Higgs m H = λν SM,. J P C = 0 ++,. 6

.. Higgs Higgs. gg H (gluon fusion), qq qqh (vector boson fusion), q q (W/Z)H (W/Z associate production), gg tth (top associate production)..7., Higgs.8..7: Higgs [] gluon fusion (GF): 0pb @m H = GeV Higgs, Higgs. LHC, p T. vector boson fusion (VBF): pb @m H = GeV (W, Z),. GF /6, p T. η ϕ. W/Z associated production (WH/ZH): pb @m H = GeV Higgs. W/Z. LHC, LEP Tevatron. 7

top associated production (tth): 0.pb @m H = GeV t Higgs. t b W (qq or lν). 0 0 0-0 - 0-0 - gg H qq _ HW σ(pp H+X) [pb] s = TeV M t = 7 GeV CTEQM qq Hqq gg,qq _ Hbb _ gg,qq _ Htt _ qq _ HZ 0 00 00 600 800 000 M H [GeV] 0-0 - 0 - bb _ BR(H) τ + τ cc _ gg γγ Zγ WW 0 00 00 00 000 M H [GeV] ZZ tt -.8: Higgs [].9: Higgs [].. Higgs Higgs,..9. H γγ: 0.% @m H = GeV Higgs.,.,, Higgs... m = E T E T (cosh( η) cos( ϕ)) H W W % @m H = GeV Higgs W, lν (l µ e),. νν met (missing E T ) ll (m T ). (E m T = ll T + E ) ( T + p ll T + p ) T Higgs 0, S/N. 8

H ZZ % @m H = GeV Higgs Z, ll, Higgs (golden channel). on-shell Z 9GeV,., CP. H ττ 6% @m H = GeV Higgs τ. τ lν l ν τ hν τ,. Drell Yan τ. g ττh. H bb 8% @m H = GeV Higgs b. QCD, q q (W/Z)H,. g bbh,... Higgs. H γγ H ZZ. 00fb 0.%. SM Higgs,., ATLAS GeV. H ZZ,. ϕ, Z θ, θ ϕ. F (ϕ) = + α cos(ϕ) + β cos(ϕ) G(θ) = T ( + cos (θ)) + L sin (θ) α, β, R = (L T )/(L + T ), CP. 00fb σ. 9

, (σ) (BR: Branching Ratio), N. σ BR = N B L ϵ B, L, ϵ..6,. α, β SM..6:, σ BR GF α GF gtth H γγ (β γw g WWH β γt g tth ) /Γ H VBF α WF gwwh + α ZF gzzh H W W β Z gzzh /Γ H WH α WH gwwh H ZZ β W gwwh /Γ H ZH As anα example, ZH gzzh for the channel WH(HH ττ WW) the product (σ β τ BR) gττh /Γ j ( x) inh tth equation α(8) can tth gbe tth written as: H bb β b gbbh /Γ H (σ BR) WH(H WW) ( x) = σ WH BR(H WW) = α WH gw gw β W. () ΓH ΓH SM Higgs For the case of GF H ZZ it is:. g tth, g bbh, g ττh. GF, tth g tth. g bbh, g ττh (σ BR) ggh(h ZZ) ( x) H= σ ggh bb, HBR(H ττ ZZ). Γ H,. = α ggh g t gw β W g Z gw. g WWH (6) ΓH ΓH.0. 00fb 0 0% In Figure the relative error on the measurement of relative couplings is shown.. for low and high luminosity. Due to the high rates of the GF and t th production processes the top-coupling ratio gt /gw can be measured quite accurately already at low luminosity. g W g W g (H,X) / g (H,W) g (H,X) / g (H,W) 0.8 0.6 g g g g (H,Z) / g (H,W) (H,τ) / g (H,W) (H,b) / g (H,W) (H,t) / g (H,W) without syst. uncertainty ATLAS L dt=0 fb - g (H,X) / g (H,W) g (H,X) / g (H,W) 0.8 0.6 g g g g (H,Z) / g (H,W) (H,τ) / g (H,W) (H,b) / g (H,W) (H,t) / g (H,W) without syst. uncertainty ATLAS L dt=00 fb - 0. 0. 0. 0. 0 0 0 0 0 0 60 70 80 90 m H [GeV] 0 0 0 0 0 0 60 70 80 90 m H [GeV] Figure : Relative error for the measurement of relative couplings. The dashed lines give the expected relative.0: error without systematic uncertainties. [] The reason for the small bump in gt /gw at m H = 70 GeV is, that the top coupling is mainly measured from the production ratios of GF and t th to WBF. 0

, Higgs,. λ HHH = m H ν λ HHHH = m H ν Higgs,. 000fb,... 0 Higgs, LHC. LHC TeV, LHC. Higgs, (SUSY ) Beyond Standard Model (BSM)., LHC ATLAS. LHC 7TeV, 0 cm s. High-Luminosity LHC (HL-LHC), 00 000fb. ATLAS. HL-LHC,. Higgs, TeV SM SUSY squark ( TeV), gluino (.TeV) W, Z. SuperSynmetry:

. LHC LHC 009 900GeV 00, 0 7TeV, 0 8TeV. 00 0pb, 0 fb, 0... cm - s - ] ] Peak Luminosity [0 0 s = 7 TeV s = 7 TeV s = 8 TeV ATLAS Online Luminosity 8 6 0 Jan Apr Jul Oct Jan Apr Jul Oct Jan Apr Month in 00 Month in 0 Month in 0 Jul Oct - Delivered Luminosity [fb 0 0 0 0 Jan ATLAS Online Luminosity 00 pp s = 7 TeV 0 pp s = 7 TeV 0 pp s = 8 TeV Apr Jul Oct Month in Year.: [] 0, Long Shutdown (LS). LS LHC,. LS 0, LHC. 0-0 LS, 08 LS, 0 LS, LS 0 cm s HL-LHC..7..7: HL-LHC (TeV) (cm s ) 0 6 0 0- (LS) 0-7 6. 7 0 08 (LS) 09-7 0 0 (LS) 0-7 0, HL-LHC. 0 0 cm s, 0 cm s.,., LS, LS LHC.

LS,... Long Shutdown (0-0) TeV 6. 7TeV.,,,... Long Shutdown (08). LIU (LHC Injectors Upgrade), Linac Linac, PS Booster, SPS. Linac 0MeV, Linac 60MeV, PS Booster.GeV GeV. PS Booster, J-PARC,... Long Shutdown (0) 0 cm s. Interaction Region (IR),. IR (Q, Q, Q) (D, D). KEK D, 6T R&D...,,. KEKB 6,....: D [].: [] Japan Proton Accelerator Research Complex: KEK :, 6 KEK km. 8GeV.GeV

.6 ATLAS,. cavern background 7, ATLAS LS. LS phase-0 upgrade, LS phase- upgrade, LS phase- upgrade...6. phase-0 phase-0. Insertable B Layer. Insertable B Layer Pixel, B Layer, b., B Layer B Layer (IBL: Insertable B Layer). IBL IP 8 (.7cm), b., D. D,.,,.. Pixel IBL..: IBL [] 7 8 Interaction Point:

Endcap Extra (EE) Chamber, (.0 < η <.).., (z 7m),...6. phase- phase- L L,. New Small Wheel, High Granularity Calorimeter Trigger, Fast TracKer, Forward Physics System. New Small Wheel Small Wheel (SW) MDT CSC. < η <.7. SW, New Small Wheel (NSW)... SW MDT. MDT 0 cm s, phase-. L 98%., p T., NSW,.: [].6: MicroMegas []

ATLAS Phase- Upgrade Letter of Intent[], NSW SW small tube MDT (smdt)+ small wheel TGC (stgc), smdt + RPC, MicroMegas (MM), MM + stgc. MM mm,. 00µm (0kV/cm ), 0. ( 00ns)..6 MM. stgc, 0 khz/cm TGC. MM, stgc 00µm. High Granularity Calorimeter Trigger,, L. 0kHz 0 0GeV, W, Z.., L η ϕ = 0. 0. RoI, 0.0 0. Super-cell, 0.07 0. 0.7 0. : R η = E E 7 R (/ ). L L, L..7..7: High Granularity Calorimeter Trigger[] 6

Fast TracKer Fast TracKer (FTK) L L L.. L 00ms, 00µs L. L Pixel SCT. FTK,. µs. FTK b, τ-id,..8 FTK. ATLAS FTK Calo Muon Pixel/SCT LVL Trigger ROD ROD ROD ROB ROB ROB LVL CPU Farm Lv pixel,sct Full Pixel/SCT Hits received @ 0KHz~00KHz FTK P T > ~ GeV FTK Lv Lv.8: FTK [] Lv / Forward Physics System IP 0m ATLAS Forward Proton detector (AFP),. BSM γ W/Z, QCD., AFP. 06m AFP D, m AFP D. PMT 9, 0ps..6. phase- phase-,. 9 Photomultiplier Tube:, 7

ID. Pixel SCT, TRT 0 cm s,. TRT., Pixel η <.7, SCT 7. η <...9 ID..9: ID [6], phase-.,. Tile. HEC, FCal., FCal,., FCal (sfcal), FCal (Mini-FCal). sfcal FCal.,. HLT. L0/L,. 8

L W Z p T, Higgs. TGC,, L.. TGC TGC,... TGC TGC MWPC,..8mm.mm, ns. R, ϕ.. TGC. Graphite layer Pick-up strip +HV 0 µm wire.8 mm. mm.6 mm G-0.: TGC [6].8mm 0µm 0µm -.mm 0g.kV MΩ/cm CO /n-pentane (:) CO n-pentane :.,., 9

.,. n-pentane,... TGC,.,.,....:, [6], T T9. T T ϕ π/ = 0.6rad, T T9 ϕ. T, T, T6, T7, T8 R ϕ TGC (M). T, 8. T, T, T6, T7, T8, T9 TGC (M), T, T, T6, T7, T8, T9 TGC (M). M, M, M MDT BW.. BW. 0

.: Big Wheel[6].. TGC BW (z m) M, (z m) M, (z.m) M. IP 7, 6. M M m, MDT.. TGC. 000 M M S L =.0 M 0000 R(mm) 8000 6000 I Low-p T Pivot plane End-cap 000 High-p T =.9 Forward =.0 000 S L =.70 6000 8000 0000 000 000 6000 z (mm).: TGC [6]

TGC.0 < η <.9,.9 < η <.70. T, T. DAQ..0 < η <.70 M,... TGC TGC, ϕ /.,, R (M) (M, M). (ϕ0, ϕ), (ϕ0 ϕ)... 8, 7 (R) (ϕ) = 8, 6 (R) (ϕ) = 6., TGC RoI....: TGC [][9]

. TGC.... p T TGC p T.. IP, W Z. BW., BW M, M, M. (R, ϕ). M IP. (dr, dϕ) p T.6. p T dr, dϕ. ϕ dϕ = 0, ϕ. muon path magnetic field Inf PT line beam line triplet Z=~m pivot middle Z=~.m Z=~m R Interaction Point.6: p T []... TGC, p T.,..7..

. SLB ASIC, SLB (Slave Board)ASIC. SLB ASIC / (WD/SD), / (WT/ST). WD, SD /, WT /, ST /. WD, SD Low-p T. HpT, VME HpT (High-p VME6x T ). HpT, PP SLB. High-p HPT SL T, Low-pMUCTPI T, High-p T ASD Trigger SL. SL,.:TGC Sector Logic (SL). Coincidence Window p T ASD PS LVDS PS HPT CAT6 0m m HPT SL HPT SL SLB ASIC M middle Doublet M pivot Doublet Str ip( ) / HPT SL M T r iplet Wire(R ) / R - T r igger Wire(R ) / Str ip( ) /.:TGC.7: [] SLBASIC HPT R φ SL R φ M M. p T Low-p T M M. p T... PPASIC SLBASIC LA SSW SSW SLBASIC G-Link ROD

É º½ Ó Ò Ò Ï Ò ÓÛÚ ÈÓ Ó Ò Ò Ï Ò ÓÛ ËÄÚ ÖÚÐ ÀÈÌ ËÙ ÚÐÓÒÎÖË Ò Ê Ö Ð ÌÙ Í È Ê µòéèóôìòìí ÎÏÚÚÉÈËÐÎ.. Coincidence ÄÎĽÖÍ Ë ÓØÔ ÖÍ ËÌÍÒÉÉÐ Ô ÐÐÛÚÊÈ ÙÕÐ ÙË Window ÙÈ ÔÌ ÒØ ÔÏÒÖØÐÈ ÌÐ ÍÉÐ Ì Ù ÌÈÑ Ó Ò L p T pt pt6 6 (.). Coincidence Window (CW) SL (dr, dϕ) 6 p T ÙÕÐ ÙËÈ ÎÚÙÍÄÎĽ ÊÈÉÐÚÈÕËÙÈ ÌØÔ ÔÌÌÍÚ ÄÓÓ ¹ÙÔ Ì Ð ÄÍ̵ÈÓ ÉÈËÐÓÈÎ ÄÍÌÖ É ÊÍËÎÙÓ ÉÏËÔÚ ÈÓÌÚ. ÌÐÍÐ ÒÚÛÍÚÙË É ÒÈÔÔ Ò Ö ÓÚÛÍÛÓÒÖÖ ÎØ CW SL LUT, SL ÖÚÊ ÓÎ ÒÐÎÈÓÔ Î ÕÏ ØÖ ÚÉ ÏÉ Ú É ÉÔ ÎÊËÚ dr, dϕ Î ÌÙ ÉÔÏÚÊ Ó ÖÚÐÓÈÎ p T. setc_0.9_mod0_roi8 pt pt pt pt pt6.: L p T η =. 0 φ = 0. L menu pt 6 condition Sub-sector dr 0 L MU0 pt p T 6GeV 0 L MU6 pt p T 6GeV 8 sub-sectors L MU0 pt Õ º½ Ì ÇØ ÒØ - L MU pt p T GeV -0 6 sub-sectors L MU pt p T GeV m L MU0 pt6 p T 0GeV Ó Ò Ò Ï Ò ÓÛ ÓÊÓÁÊÚÉÎÚÐÎ ÊÓÁ Õ ÖÍ ËÉÒÏ˽ ØÏÍ Ò Ô - -6 - - 0 6 8 dphi Õ º¾ Ó Ò Ò Ï Ò ÓÛ.8: CW [9].8 CW. dϕ, dr, ¾ dr p T. ÊÔ ½ ÓÖÛ Ö ÊÔ Î ÌÄ Ë ÖÑÈ ÌÐ ØÈÎÚ, η Ê Ó ËÐÓÈÎÏÚ ÌÐ ÇØ ÒØ ÚÙ ÓÈÎ ½ ÇØ ÒØ Ò Ô ÊÔ Ö dr = 0. Í ËÉÒÏË ÓÖÛ Ö ÊÔ ÚÍØ Î Õ º½µ ÕÍѽ¼ ¼ ÊÓÁÚ CW RoI. 8 /8, RoI 6 8 + 6 = 080 CW. CW,. sector Trigger..0. Look Up Table:.

., p T. FPGA, ASIC FPGA (Field Programmable Gate Array), LSI., LUT, FF (Flip Flop). LUT RAM, ( ). RAM,. FPGA,., IC CPLD (Complex Programmable Logic Device). FF AND/OR,., FPGA. FPGA, LSI,. ASIC (Application Specific Integrated Circuit) LSI,,. LSI. FPGA,., FPGA CPLD ASIC. ASIC., FPGA RAM anti-fuse FPGA,., FPGA. FPGA Block RAM DSP,, FPGA. FPGA..., ASD, PP, SLB, HpT, SL (.9).,... PS, PP SLB. MUCTPI (Muon trigger to CTP Interface) TGC CTP. Digital Signal Processor: 6

VME PP SLB VME6x SL HPT MUCTPI ASD ASD ASD ASD Trigger 図.9: トリガーフロー [] 表.: レイテンシテーブルの例 [] クロック消費 総クロック ASD cable PS Board cable HpT fibre SL cable MUCTPI 0.. 7. 6. 6. 6. 8 9. 0.. 6. それぞれのエレクトロニクスの詳細は次小節以降に譲るが, どの位置に配置されているかを簡 単に記す. ASD は増幅器であるため TGC の読み出し口に直取り付けられる. そこから LVDS 信号をフラットケーブルで PS ボードに送る. PS ボードは複数でまとめられて BW の側面に取り 付けられている. PS ボード内の PP と SLB での処理が終わると, LVDS 信号をツイストペアケー ブルで HpT ボードに送る. HpT ボードの入った HSC クレートは BW の外縁に取り付けられてい る (図.0). 図.0: BW 上の PS ボード及び HSC クレート [] 図.: USA のラック [] これまでは実験ホール (UX) であるが, これ以降のエレクトロニクスは 00m ほど離れたカ ウンティングルーム (USA) にある. 遠いのでデータを運ぶのに光ファイバーを用いなければな らず, ATLAS では G-Link 6 と呼ばれる規格で光通信を行っている. HpT から SL も G-Link でつ ながれており, 0 クロック程度かけて SL に到達する. 図. に USA の様子を載せる. Low Voltage Differential Signaling: 高速差動信号の規格. ANSI/TIA/EIA-6 において最大 6Mbps (理想的 な伝送路で.9Gbps) と記されている 6 Agilent Technologies 社のトランシーバチップ HDMP-0/0 で用いられている通信規格. TGC では 0bit 0MHz = 800Mbps で使用する 7

.. TGC ASD, PS. PS (Patch panel and Slave board ASIC Board) PP, SLB ASIC,. PP ASIC SLB ASIC. /, 0, 7 PS.. PS. Service Patch Panel PS Board LA CAN elmb ASD ASD Patch Panel Variable Delay Variable Delay Variable Delay BCID BCID Patch Panel BCID OR JTAG Route Controller Slave Board SSW HPT Variable Delay BCID LVL Buffer Derandomizer.: PS [] ASD ASD (Amplifier Shaper Discriminator) ASIC TGC,, ASIC. ASD ASD ASIC, 6., 7 6 ASD. LVDS PS.. ASD. PP ASIC PP (Patch Panel) ASIC PP. PP TOF 7, / = 0.78ns 0.ns,. PP,. PP. TTC LHC. 7 Time Of Flight: 8

i SW A B Cf = pf R f = 6 k INV NON-INV Cf Rf Cb i G 7 Vth offset setting comparator preamplifier SW-position C b NON-INV > INV B discharged byi NON-INV < INV A charged-up byi.: ASD []., PP ASIC, ASIC. SLB ASIC SLB ASIC ASIC,., PP, 60bit. WD SD / bit. WT bit. ST., WD, SD, WT, ST. ASIC,. WD, SD Low-p T. WT, ST. HpT. L Buffer. SLB L Buffer bit 8,.µs. bit 60bit. bit 0bit, (BCID: Bunch Crossing ID) bit. LA TTC, ± L Buffer,. bit (LID: Level ID), 6bit.,, bit LVDS. TTC ECR, BCR SLB,. 9

.. HSC HSC HpT SSW Crate HpT SSW VME 8 9U. HSC,. BW,, HSC (HpT SSW Controller board) VME. HSC G-Link USA CCI (Control Configuration Interface board). HpT HpT -. HpT ASIC,., 6 High-p T., p T., SLB ASIC Low-p T. HpT (EW), (ES), (FW). EW-HpT SLB ASIC, HpT ASIC. 7 9, G-Link SL. ES-HpT, HpT ASIC., SL.. FW-HpT EW-HpT..: HpT [].: SL [] 8 VERSAmodule Eurocard bus:. 9 ASIC TGC, 0

.. SL SL USA VME9U+6U, SL TTC, VME SBC 0. USA HpT G-Link. SL SL R ϕ p T. SL (EC) (FW),. EC-SL FW-SL. SL, FPGA SLB ASIC., FPGA SLB ASIC. EC-SL EW-HpT ES-HpT. FW-SL FW-HpT. FPGA CW Sub Sector Cluster (SSC) 6 pt. SSC R ϕ, SL. pt. pt, MUCTPI. RoI, pt, BCID, bit. SL PS SLB ASIC BCID, SL. from Hi-Pt board (strip) 9bit x decoder BCR ECR FE_BCID counter FE_LID counter L buffer Derandomizer LS-Link from Hi-Pt board (wire) from EI/FI 0bit x7 bit decoder Clock R-phi coincidence Clock EI/FI coincidence Pre-Selector Clock Track Selector LA highst Pt Track BCR FE_BCID counter Encoder Clock to MUCTPI Clock Clock Clock Clock.6: SL [] 0 Single Board Computer: CPU HDD, VME

.: SLB ASIC [] PS Board SLB ASIC HpT ASIC SL EWD0 EWD0-0 EW0 EC EWD0- EW EWD EWD-0 EWD- EWD EWD-0 EW EWD- EWD EWD-0 EWD- EW EWD EWD-0 EWD- ESD0 ESD0-0 ES0/ ESD0- ESD ESD-0 ES/ ESD- ESD- FWD0 FWD0-0 FW0 FW FWD0- FWD FWD-0 FWD- FW FSD FSD0-0 FW PS Board SLB ASIC HpT ASIC SL EWT0 EWT0-0 EW0 EC EWT0- EW EWT0- EWT EWT-0 EW EWT- EWT EWT-0 EW EWT- EST EST0-0 ES0/ EST0- ES/ FT0 FWT0-0 FW0 FW FWT0- FT FWT-0 FW FWT- FST0-0 FW SL SLB ASIC PS, SL. bit SL.. EC-SL,.6.,. SLB ASIC... SL SL PS SLB ASIC, SSW, ROD. SSW HSC USA SSW..7. SSW SSW (Star Switch) SLB ASIC,. SSW, anti-fuse FPGA 6,. FPGA SLB ASIC.. 8bit, 0,

M M M On TGC Big Wheel edge Counting Room TGC ASD PS-Board PP SLB ASIC / Coin. Readout VME crate HPT wire Sector Logic ASD Doublet PP PP DCS-PS SLB ASIC / Coin. Readout HPT strip SSW SSW ROD Readout ROB Triplet PP DCS-PS TTC CTP DCS LCS CLK, LA etc.7: []. TGC 0,. anti-fuse FPGA, G-Link ROD. /, /.,, 8 SSW HSC. SL SSW EC-SL FW-SL,. SSW USA..8 SSW..9: ROD [].8: SSW []

ROD ROD (Read Out Driver) TGC, ROB. TTC. SSW, S-Link[0] ROB., busy CTP..9 ROD...6 TTC TGC TTC PS SL SLB ASIC, ROD., BW PS SPP (Service Patch Panel board). TTCrq TTC, PS TTC. 7 PS, 8. USA, SL VME, SPP VME SL-SPP. SL TTC. ROD TTCrms. ROD,. TTCoc.. LHC HL-LHC, L. 0,, 98% IP.,... L, L MU0. p T 0GeV, 0.kHz. L MU0, khz phase-. L MU0 η.0. L MU0,, p T 0GeV., L MU0 %. 98%,. η >.0

(TGC ),, khz..0: L MU0 η [7]...,, IP..0 ( - ).,., IP, p T 0GeV..0 0GeV ( - ). p T BW,. TGC mrad,.. : 0.mrad. : mrad. nominal IP : mrad /,.

.. phase-0 phase-0, SW TGC. TGC (EI/FI),., 0, [0]. EI/FI BW TGC. SL R ϕ. EI/FI 6bit, BW-SW. [9], BW SW... phase- phase- NSW. NSW, NSW, NSW. NSW,. IP NSW dθ, IP. mrad. IP, BW R ϕ,. SW ( ), L MU0... L MU0, (InnerSeg)., dθ (dθ )., dl (dl ) dθ. IP. dθ 0 IP. dl BW-TGC RoI (η, ϕ). dl = (η RoI η Seg ) + (ϕ RoI ϕ Seg ) p T dl 0,.. L MU0. p T,.%. 96.6%,. 6

BW-TGC fake C SW RoI (η RoI, φ RoI ) Segment (η Seg, φ Seg ) dθ fake B Nominal IP Magnetic field z axis.: dθ, dl.: dθ, dl [7], NSW dθ 0. BW SL, p T. IP RoI, dl. SL R ϕ NSW-BW, NSW. phase- SL. 7

.. phase- phase-, L0. Long L Buffer (.)., L0/L Buffer L Buffer. LA(<00kHz) TGC BCID L- Buffer Readout L0 Trg Processor L0A info LA(<00kHz) MDT TDC L- Buffer Readout BCID L Trigger Processor LA info L0A(BCID/RoI).: phase- [] MDT L Buffer (LB) L Trigger Processor (LTP). LB ( k depth). TGC/RPC LB L0 Trigger Processor (L0TP), L0TP L0 Accept (L0A). L0TP L0A BCID RoI, MDT LP L0A, LA CTP.,,., PS L Buffer USA,.,.,.., phase-. MDT, L p T. EI, EM MDT [8]. EI z θ I, EM θ M β, p T. β = θ M θ I p T = Aβ + B p T β, p T. 8

Present system ASD PS-Boardon TGC HSC VME on BW VMEat USA Trigger LB BCID H-pT SL TRG Read out SSW ROD JRC HSC CCI SBC Control Phase- upgrade ASD PS-Board on TGC BCID ASIC Rx / Tx Controller Tx / Rx XXX crateat USA TRG SL LB SSW ROD Controller FPGAs SBC Trigger Read out Control.: phase- [8]..6, HL-LHC. phase- SL, R&D. phase- BW,, R&D., FPGA. FPGA 0, LSI FPGA. FPGA CPU., FPGA. FPGA, TCP/IP (SiTCP) Multi- Gigabit Transceiver (MGT)., TCP/IP FPGA. DAQ., 0Gbps FPGA. MGT,. TGC,. SiTCP SL, phase- DAQ. MGT SL, phase- USA.,. SiTCP, MGT., phase- SL. FPGA,. 9

PC, PC. (GbE: Gigabit Ethernet),, DAQ. FPGA TCP/IP. SiTCP (Silicon TCP), GbE. SiTCP, DAQ,.. TCP/IP TCP/IP. OSI (Open Systems Interconnection), ISO....: OSI 7 6,.. OSI ( ) ( ). MAC International Organization for Standardization: Media Access Control: 60

,.,. LAN 0BASE-T, 00BASE-TX, 000BASE-T RJ- UTP. UTP (Cat.x ),. 0BASE-T 00BASE-TX Cat. UTP /. 000BASE-T Cat.e (enhanced Category ) UTP... TCP/IP TCP/IP OSI ( ) IP ( ) TCP. IP Internet Protocol, TCP Transmission Control Protocol. IP TCP UDP, TCP. IP[] IP., IP IP. IP IP. TCP[] IP.,,. HTTP 6 SMTP 7. ARP IP MAC. IP MAC ARP[7] (Address Resolution Protocol). IP ARP request, MAC ARP reply. ICMP IP,. ICMP[8] (Internet Control Message Protocol)., ping, ICMP. Local Area Network: Registered Jack-: 8P8C Unshielded Twisted Pair: 6 HyperText Transfer Protocol: Web 7 Simple Mail Transfer Protocol: 6

.. UDP UDP[6] User Datagram Protocol, TCP ( )., TCP.,,... SiTCP TCP,.., SiTCP[]... SiTCP FPGA [6]. FPGA, GbE.,,. FPGA, FPGA, BeeBeansTechnologies. SiTCP...: SiTCP [6] 6

TCP, UDP, ICMP/ARP 8bit MAC,. TCP, UDP. TCP TCP TCP. TCP, PC. 8bit FIFO 8, FIFO. UDP UDP, UDP FPGA. RBCP (Remote Bus Control Protocol). RBCP FPGA,. Ethernet PHY 9, EEPROM 0, SiTCP., FPGA. (ver.0)...: RBCP [7] RBCP 0xFFFF0000-0xFFFFFBFF 0xFFFFFC00-0xFFFFFCFF 0xFFFFFD00-0xFFFFFDFF 0xFFFFFE00-0xFFFFFEFF 0xFFFFFF00-0xFFFFFFFF Reserved EEPROM Reserved Ethernet PHY I/F, SiTCP ARP/ICMP ARP request ICMP echo request. ARP MAC, IP. ICMP echo ( ping ), IP. 8 First In First Out:, 9 Physical layer: 0 Electrically Erasable and Programmable ROM: ROM ROM 6

MAC MAC., MAC... TCP TCP. ProtoType6 (PT6)[8] VME. PT6 FPGA Xilinx Spartan-6 FPGA XC6SLX0T, Ethernet PHY DP886, SiTCP GbE. B PT6.. FPGA 8bit 0MHz, SiTCP. SiTCP TCP. Windows PC Cat.6, SiTCP Utility[].. SiTCP Utility...: TCP SiTCP Gbps 6

, 70kbps, PT6. Wireshark[9].. Wireshark..: Wireshark µs, 9 [TCP zerowindow] 0 [TCP window update] sec. window update,., 0 update 60byte/.sec = 7kbps, Utility. TCP Window, TCP.,. 00Mbps. 6

. Gbps SiTCP Ethernet PHY 0/00/000BASE-T. PT6 000BASE-T, Gbps.... PT6 PT6 SiTCP. FPGA 8bit 0MHz G Corega CO-BSW6GTX. : 0/00/000BASE-T 6 :.8Mpps : Gbps LAN PT6, PC m Cat.6 PC DELL PRECISN T00. CPU: Intel Xeon W6 @.GHz : DDR- GB OS: Scientific Linux CERN release.8 NIC : Broadcom BCM76 G NIC.., RTT. 00 ping.. 0.ms, 0.06ms. :., packet per second: Network Interface Card: PC Round-Trip Time:, 66

: G link PT6 PC G switch.: Gbps 0 entry 0 0 0 0.07 0.08 0.09 0. 0. 0. 0. 0. 0. RTT (ms).: G RTT ( ). RTT. T = W R T, W TCP, R RTT. RTT,. PC W = 87.kB, SiTCP 6, 6kB. 6 6kB. 67

T = 66 8 =. [Gbps] 0. 0.. PT6 PT6. SiTCP FIFO, TCP TX FULL 0 TCP TX WR. FIFO.6. FIFO 8bit 0MHz, FULL. TCP TX FULL FIFO rd en (read enable), TCP TX WR valid, SiTCP.,. 8bit 0MHz Connection Connection Connection n valid User FIFO rd_en select TCP_TX_WR SiTCP TCP_TX_FULL len=recv (60 byte).6: PT6 While loop lenをカウントし 00MB たまったらループを 抜 ける.7: PC PC,..7.. PC PT6 TCP. Select. MSS 60byte. PC 00MB. PT6, (clock gettime ) 68

,, TCP/IP.. Gbps ( ), (.) 000 8 = 987 Mbps 8 + 8 +. 8byte, 8byte 7, byte IFG 8. TCP/IP. 987 60 = 99 Mbps 8.: 8 6 6 0 0 60 IFG preamble src addr dst addr type Ether data FCS 9 header IP data header TCP data.... SiTCP SiTCP and TCP control register (RBCP : 0xFFFFFF0)....: SiTCP and TCP control register bit 7 0 SiTCP reset 6-0 Reserved 0 Keep alive packet Keep alive 0 Fast retrans Fast retransmit 0 Nagle buffering Nagle buffering 7 8 Inter Frame Gap: byte 9 Frame Check Sequence: CRC (Cyclic Redundancy Check) 69

Keep alive[9], TCP. Keep alive Fast retransmit[0] TCP, ACK 0. Fast Transmit, ACK Nagle buffering[] TCP/IP. ACK MSS Keep alive. Fast retransmit Nagle buffering... 0..: G (Mbps) Fast retransmit off Fast retransmit on Nagle buffering off 860± 86± Nagle buffering on 88± 89± Fast retransmit Nagle buffering. Fast retransmit. Nagle buffering 0Mbps. Nagle buffering. tcpdump, Wireshark GUI..8. Bits/Tick 000000 Gbps. Nagle buffering.. 0 Acknowledgement packet: Maximum Segment Size: 70

.8: G ( : Nagle on, : Nagle off),. MSS TCP, MTU. MTU 00byte, TCP/IP 0byte 60byte MSS. TCP MSS,. SiTCP MSS (RBCP : 0xFFFFFF0-), PC. MSS 00 08byte. Nagle buffering, MSS..9. 000 000 Throughput (Mbps) 800 600 00 00 0 0 00 000 00 000 MSS (byte) 0 0 00 000 00 000 Segment Size (byte) 00 000 00 000 00 000 00 entry.9: MSS.0: Nagle off MSS 9 byte 8byte. PC OS 8byte., MSS, 60byte. Nagle buffering,. Maximum Transmission Unit: 7

.8 ( ),.0. x.9. 60byte,.,., Nagle buffering 60byte,,......6., Nagle buffering., PC 89Mbps..6: G (, Mbps) Fast retransmit off Fast retransmit on Nagle buffering off 70±00 690±0 Nagle buffering on 89.0±0. 89.0±0. Wireshark... Nagle buffering PT6. IP = 9.68.0.7. IP = 9.68.0.6, PC ACK, 0.sec 9.68.0.6..: G ( : Nagle on, : Nagle off),., Fast retransmit 0.sec. 7

, Nagle buffering. Fast Retransmit,,.,, Nagle buffering,., 89Mbps., PC. PT6.7. Nagle buffering.,..7: G (, Mbps) Fast retransmit off Fast retransmit on Nagle buffering off 80±90 60±0 Nagle buffering on 89.±0. 89.±0... PC DAQ (.). PT6 PT6A, PT6B, PC PCa, PCb PT6A-PCa, PT6B-PCb...,. PT6A : G link PT6A : G link TCP connection TCP connection PCa PCa TCP connection PT6B PCb PT6B PCb.:.: flood 7

flood, SiTCP. PT6A-PCa, PCb flood. PCb PT6A DoS (.). DoS.,. ICMP flood UDP flood. TCP SYN flood, TCP. hping[0] TCP UDP,. PCb hping, TCP SYN flood PT6A, ICMP flood. TCP SYN flood, PCa PT6A SYN flood ( SYN ).. PCa flood, PCa. PT6A ICMP flood, 00 ICMP 60Mbps, 000 0Mbps., PT6A-PCa,. SiTCP flood,., SiTCP.. 00Mbps SiTCP Gbps, PC 89Mbps. 00Mbps, SiTCP... SiTCP 00M. 00Mbps.. PHY 00BASE-TX. 00M PT6 G. 000BASE-T Denial of Service: Synchronize packet: 7

, 00BASE-TX 000BASE-T., 00Mbps, 00Mbps, 0Mbps. 00BASE-TX 000BASE-T. 0.m Cat.e. LAN.. TIA/EIA-68-b. 00BASE-TX,. 00M 8, 00M. / / / 6 7 / 8.: LAN.. 00 ping RTT, 0.6ms, 0.006ms. T = 66 8 =. [Gbps] 0.6 0. 00Mbps. 00MB, 0MB. TIA/EIA-68-a, TIA/EIA-68-b. a b 7

: G link : 00M link PT6 PC G switch.: 00Mbps.. 00Mbps.8. 0. 9.8Mbps., G Nagle buffering. 00M 9.9Mbps 99.9%,., SiTCP..8: 00M (Mbps) Fast retransmit off Fast retransmit on Nagle buffering off 9.79±0.0 9.8±0 Nagle buffering on 9.8±0 9.8±0.. SiTCP 00Mbps 0 PT6.. PT6 PT6. PT6 8..9. Nagle buffering Fast retransmit SiTCP and TCP control register 0, reg[:0] = 0 (Fast retransmit off, Nagle buffering on)., 00M, PT6. 76

.9: 00M (Mbps) PT6 reg[:0] = 00 reg[:0] = 0 reg[:0] = 0 reg[:0] = 9.8 9.8 9.8 9.8 89.7 89.7 89.7 89.7 8.6 8. 8. 8. 79. 79. 79. 79. 7. 7.6 7.0 7. 6 68. 69.0 69. 69. 7 66.6 66.9 66.0 66.9 8 760.7 760.7 760.8 760.7.6 reg[:0] = 0 PT6.. T [Mbps] = 9.06n 0.706, SiTCP. 900 800 700 Throughput (Mbps) 600 00 00 00 00 00 0-00 0 6 7 8 9 # of PT6.6: 00M. FPGA TCP/IP SiTCP, VME PT6. SiTCP 000BASE-T, Nagle buffering 860Mbps. PT6,, Nagle buffering 89Mbps. 77

SiTCP 00BASE-TX, Nagle buffering 9.8Mbps. PT6,.. n SiTCP, DAQ PC,. n 890Mbps. n 9 890/n Mbps, SiTCP, PC 000BASE-T. Nagle buffering 9/n 9 Mbps SiTCP 00BASE-TX, PC 000BASE-T. 9/n Mbps 00BASE-TX. EC-SL SiTCP. 0bit 7kHz = Mbps. EC-SL A/C-side, DAQ PC. SL 00BASE-TX, DAQ PC 000BASE-T DAQ. 78

GTX Transceiver., 0G,. FPGA 0G. Xilinx Multi-Gigabit Transceiver (MGT), FPGA. MGT GTX Transceiver.. Xilinx MGT,... Xilinx Multi-Gigabit Transceiver. Xilinx MGT. 0 0Gbps, 8., FPGA 6.6Gbps, MGT..: Xilinx MGT MGT (Gbps) 00 Rocket Virtex- 6. 006 Rocket GTP Virtex-.7 006 Rocket GTX Virtex- 6. 009 GTP Transceiver Spartan-6. 009 GTX Transceiver Virtex-6 6.6 009 GTH Transceiver Virtex-6.8 0 GTP Transceiver Artix-7 6.6 0 GTX Transceiver Kintex-7. 0 GTH Transceiver Virtex-7. 0 GTZ Transceiver Virtex-7 8.0 79

X-Ref Target - Figure -8 MGT FPGA,.., IP... GTX Transceiver, MGT GTX Transceiver ( GTX).., TX BufferGTX FPGA Kintex-7.Gbps MGT. Functional Description Transmitter TX Buffer The GTX/GTH transceiver TX datapath has two internal parallel clock domains used in the PCS: the PMA parallel clock domain (XCLK) and the TXUSRCLK domain. To transmit data, the XCLK rate must match the TXUSRCLK rate, and all phase differences between the two domains must be resolved. Figure -8 shows the XCLK and TXUSRCLK domains. TX Serial Clock PMA Parallel Clock (XCLK) PCS Parallel Clock (TXUSRCLK) FPGA Parallel Clock (TXUSCLK) TX Driver TX OOB and PCIe TX Pre/ Post Emp PISO Polarity PCIe Beacon SATA OOB Pattern Generator TX Gearbox TX PIPE Control TX Clock Dividers Phase Adjust FIFO 8B/0B Encoder FPGA TX Interface TX Phase Interpolator TX Phase Interpolator Controller (GTH) TX PMA TX PCS From Channel Clocking Architecture To RX Parallel Data (Near-End PCS Loopback) From RX Parallel Data (Far-End PMA Loopback) From RX Parallel Data (Far-End PCS Loopback) Figure -8: TX Clock Domains.: GTX TX [9] UG76_c_0_ The GTX/GTH transceiver transmitter includes a TX buffer and a TX phase alignment circuit to resolve phase differences between the XCLK and TXUSRCLK domains. The TX phase alignment circuit is used when TX buffer is bypassed (see TX Buffer Bypass, page 0). All TX datapaths must use either the TX buffer or the TX phase alignment circuit. Table - shows trade-offs between buffering and phase alignment.. Transmitter (TX). TX PCS PMA. Table -: TX Buffering versus Phase Alignment PCS,. PMA, TX Buffer TX Phase Alignment.,. 8B/0B Encoder Ease of Use The TX buffer is the Phase alignment is an advanced feature that recommended requires extra logic and additional constraints default to use when on clock sources. TXOUTCLKSEL must select possible. It is robust the GTX/GTH transceiver reference clock as and easier to operate. the source of TXOUTCLK to drive TXUSRCLK. 8bit 0bit 8b0b. TX Gearbox 6b66b. 7 Series FPGAs GTX/GTH Transceivers User Guide www.xilinx.com 99 UG76 (v.) May 7, 0 Intellectual Property Core: Physical Coding Sublayer: Physical Medium Attachment: 80

X-Ref Target - Figure - Pattern Generator. PRBS -7, PRBS-, PRBS-, PRBS-, UI. Assert RXPHALIGN for all slave lane(s). Hold this signal High until the rising edge of, Phase Adjust FIFO PMA PCS FIFO PISO Parallel In Serial Out. TX Pre/Post Emp due to phase differences after conditions such as a GTX/GTH transceiver reset or rate pre-cursor / post-cursor. ISI 6 TX Driver RX Elastic Buffer Functional Description Receiver RXPHALIGNDONE of the respective slave lane is observed. RX Elastic Buffer. Deassert RXPHALIGN for the slave lane in which the RXPHALIGNDONE is asserted. 6. When RXPHALIGN for all slave lane(s) are deasserted, assert RXDLYEN for the master lane. This causes RXPHALIGNDONE of the master lane to be deasserted. 7. Wait until RXPHALIGNDONE of the master lane reasserts. Phase and delay alignment for the multilane interface is complete. Continue to hold RXDLYEN for the master lane High to adjust RXUSRCLK to compensate for temperature and voltage variations. In a multilane application, it is necessary to start the RX alignment procedure on the interface after RXELECIDLE is deasserted on any lane. The RX CDR of all lanes should be locked before starting the RX alignment procedure. This requirement is to ensure that the RX recovered clocks and RXUSRCLK are stable and ready before alignment. When the RX elastic buffer is bypassed, data received from the PMA might be distorted change. If the received data evaluated at the fabric interface is invalid on any lane, the RX alignment procedure should be repeated for the interface after the RX CDR is locked on all lanes. The GTX/GTH transceiver RX datapath has two internal parallel clock domains used in the PCS: The PMA parallel clock domain (XCLK) and the RXUSRCLK domain. To receive data, the PMA parallel rate must be sufficiently close to the RXUSRCLK rate, and all phase differences between the two domains must be resolved. Figure - shows the two parallel clock domains: XCLK and RXUSRCLK. From Channel Clocking Architecture From TX Parallel Data (Near-End PCS Loopback) To TX Parallel Data (Far-End PMA Loopback) To TX Parallel Data (Far-End PCS Loopback) RX Clock Dividers RX PIPE Control RX EQ DFE RX OOB RX CDR SIPO Polarity PRBS Checker Comma Detect and Align 8B/0B Decoder RX Status Control RX Elastic Buffer RX Gearbox FPGA RX Interface RX Serial Clock PMA Parallel Clock (XCLK) PCS Parallel Clock (RXUSRCLK) FPGA Parallel Clock (RXUSRCLK) UG76_c_0_0 Figure -: RX Clock Domains.: GTX RX [9] 7 Series FPGAs GTX/GTH Transceivers User Guide www.xilinx.com 99 UG76 (v.) May 7, 0. Receiver (RX). RX EQ, DFE. RX EQ CTLE (Continues Time Linear Equalizer). DFE Decision Feedback Equalizer, ISI. DFE Pseudo-Random Bit Sequence:. Unit Interval:. UI 6 Inter Symbol Interference:. 8

X-Ref Target - Figure -8 X-Ref Target - Figure -7 CDR Clock Data Recovery. PRBS Checker, SIPO Serial In Parallel Out. Comma Detect and Align.. 8B/0B Decoder 8b0b. RX Elastic Buffer PMA PCS EQ FIFO RX Gearbox p n RX Data Path: LPM Mode Termination Limiter AGC Linear 6b66b KL RX Equalizer (DFE and LPM) GTX, GTP Transceiver LPMDFE Adaptation., 0Gbps Controller 7.. DFE. KH RXLPM_LF_CFG[7:] RXLPM_HF_CFG[7:] SIPO CDR PH Data to PCS RXCDR_CFG[6:0] UG76_c_9_07 Figure -7: LPM Mode RX Data Path: GTX DFE Mode Data to PCS p n Termination Limiter AGC RX_DFE_GAIN_CFG[:8] Linear EQ KL RX_DFE_KL_CFG[0:] + UT RX_DFE_UT_CFG[0:] H SIPO CDR PH RXCDR_CFG[6:0] RX_DFE_H_CFG[6:] H + RX_DFE_H_CFG[6:] H VP RX_DFE_VP_CFG[:] RX_DFE_H_CFG[:] H RX_DFE_H_CFG[:] MMSE Adaptation Controller UG76_c_9_0 Figure -8: GTX DFE Mode.: DFE [9] 7 Line Rate:. bps 8 7 Series FPGAs GTX/GTH Transceivers User Guide www.xilinx.com UG76 (v.) May 7, 0

GTX... 0Gbps 8b0b 6b66b..: GTX [9] (Gbps) PCIe 8 Gen.0 8b0b PC I/O SR 9 Gen.0, 6. 8b0b I/O XAUI 0. 8b0b 0GbE PHY ( ) XLAUI 0. 6b66b 0GbE PHY ( ) 0GBASE-R 0. 6b66b 0GbE. GTX.... GTX, ATLAS. MGT.,, ( ). phase- BW USA,., FPGA, FPGA. VME,,.,.. 8 Peripheral Component Interconnect express 9 Serial Rapid 0 0Gb Attachment Unit Interface 0Gb Attachment Unit Interface 8

.. KC70 GTX Xilinx Kintex-7 KC70 [].. KC70. FPGA XC7KT-FFG900. FPGA 6 GTX,.. SMA..: KC70.: KC70 GTX [] GTX GTX 0 PCIe 6 PCIe PCIe PCIe PCIe 6 PCIe PCIe 7 PCIe 7 8 SMA 8 FMC HPC 9 SGMII FMC HPC 0 SFP+ FMC HPC FMC LPC FMC HPC SMA TX±, RX±. TX+ RX+, TX- RX-,.. Sub Miniature type A: Serial Gigabit Media Independent Interface: GMII Small Form factor Pluggable +: FPGA Mezzanine Card Low Pin Count: 60. HPC 00 8

.. SMA, HUBER+ SUHNER S 07 B... (mm).0.8.96.8.0.: [6].,., 0Ω..6. a [db/m] = 0.970 f [GHz] + 0.00 f [GHz].6: [6] SMA - HUBER+ SUHNER SMA-0-0-/ NE. 8GHz VWSR <.0+ 0.0f [GHz] [6]. VSWR Voltage Standing Wave Ratio,.. VSWR = + V /V + V /V = Z Z 0 Z+Z 0 Z Z 0 Z+Z 0 8

. GTX Transceiver GTX. GTX /, GTX BER (Bit Error Rate), BER... GTX. KC70 Texas Instruments (TI) UCD98. IC,, bit ADC 6 [6] ( ). UCD98 PMBus 7, USB (TI: EVM USB-TO-GP) (TI: Fusion Digital Power Designer GUI) /..7: Fusion Digital Power Designer GUI.7 GUI. FPGA (bit ), Pout ( ) Iout ( ). Vin, Iin, Vout, Iout, Pout, Temperature 6 Analog to Digital Converter: 7 Power Management Bus: I C 86

. IC.. KC70.. GTX MGTAVCC MGTAVTT, MGTVCCAUX, FPGA VCCINT FPGA VCCAUX..: KC70 [] PMBus (V) VCCINT FPGA.0 FPGA VCCAUX.8 FPGA VCCVD..V VADJ.8 -. VCCV FPGA. FPGA.V VCCV..V MGTAVCC.0 GTX MGTAVTT. GTX VCCAUX.0 FPGA VCC BRAM.0 BRAM 8 MGTVCCAUX.8 GTX.. (Gbps). GTX. lane 8 m (.8). Near-End PMA Loopback. TX PMA RX PMA. ChipScope Pro IBERT 9 Kintex7 GTX (.0a) IP [6]. bit KC70 FPGA 0, Fusion GUI. ChipScope Pro[60], IP FPGA. BER, Xilinx JTAG 0 FPGA. 8 Block RAM: Xilinx FPGA RAM 9 Integrated Bit Error Ratio Test: BER Xilinx IP 0 Joint Test Action Group: IC. IEEE9. [] 87

.:.G.0G 0G lane 8 only..0 0 lane 8 0 0 0 lane 8 0 0 80.8: VCCAUX 0.±0.0[A]. MGTVCCAUX 0.0±0.0[A]..9,.0,. VCCINT, MGTAVCC, MGTAVTT. MGTAVTT,. VCCINT, MGTAVCC.,. MGTAVTT,. FPGA (XC7KT) 0Gbps 6 = 60Gbps, MGTAVCC MGTAVTT A. IC, Kintex-7 FPGA. Vccint current (A). 0. before config.gbps.0gbps 0Gbps line rate current (A) R 0G I = 0.079n + 0.87 0.9989 G I = 0.0n + 0.908 0.999.G I = 0.086n + 0.89 0.9989 0 0 6 7 8 # of lanes.9: VCCINT 88

Vmgtavcc current (A). 0. before config.gbps.0gbps 0Gbps line rate current (A) R 0G I = 0.688n + 0.06 0.9999 G I = 0.070n + 0.076.0000.G I = 0.8n + 0.09 0.999 0 0 6 7 8 # of lanes.0: MGTAVCC Vmgtavtt before config.gbps.0gbps 0Gbps current (A). average current (A) I = 0.7n + 0. 0. 0 0 6 7 8 # of lanes.: MGTAVTT.. GTX FPGA. Fusion GUI, FPGA,. Kintex-7 FPGA XADC ADC, PCB ADC. VCCINT, VCCAUX, VCCBRAM FPGA. XADC.. ChipScope Pro XADC. Printed Circuit Board:. 89

.: XADC KC70 FPGA bit 0, XADC......,. T =.0n + 7.8, (XADC ± []).. /. FPGA (θ JA ) 0. /W [8], 8 ( W ) 0.., GTX KC70. 90

temperature (Celsius) 0 8 6 0 8 6 before config.gbps.0gbps 0Gbps Die Temperature 0 6 7 8 # of lanes.: FPGA.., Xilinx ChipScope Pro IBERT[60] BER. IBERT IBERT IP FPGA PC JTAG, GUI GTX BER.. IBERT..: IBERT 9

BER. TX Pattern Generator. RX PRBS Checker PRBS 0bit, +. BER. PRBS, Signal Integrity (SI). PRBS-7.. GTX PRBS-7,,,. PRBS-n n XOR, 0 n+. 8b0b PRBS-7. XOR D Q D Q D Q D Q D Q D Q D Q D CLK CLK CLK CLK CLK CLK CLK DFF DFF DFF DFF DFF DFF DFF CLK.: PRBS-7 0Gbps SMA TX±, SMA RX±. 0 bit, BER. BER., m m BER< 0...6 m 0GHz db, 8GHz db..,... BER,....6 ( ). SI. SI,. GTX 0%-80% 0ps[], 0GHz. 9

, IBERT.. IBERT RX, ( ) ( )..6 ( ) Data Sample Offset Sample. Data Sample, Offset Sample., Offset Sample.6 ( ).,..6: [9].7. DAC, PI., RX.., [9]. 0Gbps.,. m, m, 7m, 9m, m, m. Digital to Analog Converter: Phase Interpolator:. CDR 9

X-Ref Target - Figure - Eye Scan Architecture The blocks with shaded gray in Figure - describe the portion of the PMA architecture that supports eye scan. The horizontal offset (HORZ_OFFSET) advances or delays the sampling time of the offset samples relative to the data samples. The vertical offset (VERT_OFFSET) raises or lowers the differential voltage threshold to which the equalized waveform is compared. The data samples are deserialized into the Rdata bus, and the offset samples are deserialized into the Sdata bus. When in DFE mode (RXLPMEN=0), due to the unrolled first DFE tap, two separate eye scan measurements are needed, one at +UT and one at UT, to measure the TOTAL BER at a given vertical and horizontal offset. RX Input Equalization + Capture FF Rdata Unrolled Tap UT_SIGN (±) DAC - Capture FF Error-detection, Screening De-serialization Sdata PCS Interface + Capture FF DAC PI PI VERT_OFFSET Rec Clock HORZ_OFFSET UG76_c_9_060 Figure -: PMA Architecture to Support Eye Scan.7: [9]. ( : ), ( : UI). m, m. 6 www.xilinx.com 7 Series FPGAs GTX/GTH Transceivers User Guide UG76 (v.) May 7, 0 9

図.8: ケーブル m の統計的アイ 図.9: ケーブル m の統計的アイ 図.0: ケーブル 7m の統計的アイ 図.: ケーブル 9m の統計的アイ 図.: ケーブル m の統計的アイ 図.: ケーブル m の統計的アイ 9

GTX RX, CTLE DFE.,.., GHz 9dB. DFE., CTLE..: CTLE [9] CTLE DFE, ISI., CTLE 6dB, DFE BER. DFE,. CTLE., AGC (Automatic Gain Control),.... CTLE. 0Gbps GHz, CTLE m +., +.9, +., +0., -., -.0dB., m., m.,.,.. GHz 0dB, m -db,. Frequency Boost = 0. m 9.dB, Frequency Boost =., / ( ). 96

.: CTLE +. MGT GTX Transceiver, Kintex-7 KC70. 0Gbps, GTX, 0mA/. FPGA 80mA/., FPGA,. /. BER, m BER < 0.,.. ATLAS. 0MHz, 8b0b.. 00MHz 0/8 = 8Gbps NSW BW., 6bit,. 6bit ( 0MHz) 0/8 =.Gbps,. GTX bit ( 0MHz) 0/8 = 6.Gbps., 800Mbps G-Llink. 97

Sector Logic phase- upgrade NSW. NSW BW,., Sector Logic (SL). SL... Sector Logic SL,... phase-, NSW IP BW RoI. IP, NSW dθ 0. BW SL, BW. IP RoI, dl. BW R ϕ p T, SL R ϕ LUT. SL HpT NSW,. phase- HpT.,. PS SLB ASIC. SL,. SSW, ROD., ROD,., GbE,..., SSW., PC. 98

SL crate Glink from HpT SL crate Glink from HpT SBC SL SBC New SL GbE switch GbE HSC SSW DAQ PC Glink to ROD SSW crate.: SL.. New Small Wheel SL NSW,. NSW. NSW z 7m SW. < η <.7. MM + stgc, quadruplet. IP stgc let, MM let, MM let, stgc let, stgc MM 8. NSW 8. 8 (Small sector), 8 (Large sector)... Large sector Small sector.: NSW [] 99

NSW, USA SL., BW NSW. mrad 0MHz, BW dθ.. SL. BW. NSW dθ dθ, BW (dl ) η, ϕ. dθ, mrad mrad. bit bit. η, NSW RoI. BW η 0.0, ϕ 0.0,. BW. BW η.-., RoI (..)/0.0 =. ϕ Small sector Large sector, /, / Small RoI π//0.0 = 7.9, Large π//0.0 =.9. η ϕ RoI 8 =, 6 = 70, RoI 0bit. dθ, η, ϕ, 6bit.. BW p T, /8 9 8., Large ( ), Small 8 ( )... Sector Logic SL. SL,. EC-SL, FW-SL.,. HpT. EW-HpT 7 High/Low-p T. 0bit, 70bit G-Link. ES-HpT High/Low-p T. 9bit, 6bit G-Link., 7bit G-Link,. 7 + 6 = 0bit. 00

NSW. NSW BW, SL NSW sector RoI. BW RoI NSW RoI, NSW sector. NSW RoI, dl.. [7] dη 0.07, dϕ 0.06. η 0.07 BW RoI RoI, ϕ 0.06 RoI. NSW RoI η ±RoI, ϕ ±RoI. Large sector, BW Small sector. BW Large/Small sector.. Large/Small sector 8 /7..: BW NSW sector [] SL Large sector, Small sector. SL,., bit, dθ bit, RoI 0bit. HpT 0 + 6 = bit.,,. 0

,. R ϕ LUT NSW LUT....: SL EW-HpT ES-HpT NSW Delay/Decoder Delay/Decoder Delay/Decoder R ϕ coin. LUT BW-NSW coin. LUT Pre-selector Track selector Encoder for MUCTPI BW-NSW, R ϕ RoI NSW. η ±RoI, ϕ ±RoI NSW RoI. Pre-selector, Track selector, MUCTPI. SLB ASIC SL FPGA. SLB ASIC,, SiTCP....: SL LA BCR input data trig data Ev. count BC count Delay coin. part bit 0bit 6bit L Buffer (BCID) L Buffer (input) L Buffer (trig) bit Derandomizer Encoder for readout 0

NSW SL,. NSW SL, SL 8 (= 8bit)., SL bit, 6bit. BCID, L Buffer. BCID SLB bit, bit. 0 + 8 + 6 + = 06bit. phase- k. LA bit LID,. FIFO,.,. λ, µ ρ ρ = λ µ M/M//K K ( ) P K [67] P K = ( ρ)ρk ρ K+ 00kHz, λ = (06 + ) 00kHz =.Mbps. SiTCP 00Mbps, Gbps ( 89Mbps). 6 SL, µ = 89/6 = 8Mbps. ρ = 8 = 0.8 ρ = 0.8.. K = 9 σ, K = σ. σ σ 0. P K 0.0 0.00 0.000 0 0 0 0 K.: ( ),, K 0

SiTCP, PC. Mbps Gbps., 6 SL.. PT7 SL, ProtoType 7 (PT7). SL, GTX Transceiver (GTX), SiTCP,. PT7.,, [6][0]..... SL, TCP VME. NIM, FPGA, R&D.., SL., SL 9U VME, 6U. NIM,. TCP..., PT7. HpT 0bit NSW 0bit LHC 0MHz. (0 + 0) 0MHz = 0.88Gbps.. PT7 GTX. Nuclear Instrument Modules: 0

SL SLB ASIC FPGA. L Buffer bit 6bit BCID bit ( k). LID. Kintex-7 FPGA 6Kb BRAM [7]. 7bit 9., bit LID GbE. 00kHz (98 + ) 00kHz = 8Mbps. PT7 GbE, SiTCP... PT7... FPGA GTX Kintex-7. FPGA, PT7 VME, CPLD., CPLD FPGA GTX Infiniband x. Infiniband, PT6 SiTCP, Gigabit Ethernet PHY DP886. IC PT6, SL. DDR- SDRAM MTJ6M6 TTC, TTC TTCrq., SPP,, LEMO, LED,. FPGA CPU [7], PT7. OS Flash memory, RSC 6 Double Data Rate : 8 SDRAM. (MT/s) Synchronous Dynamic RAM: DRAM... LEMO. NIM 0Ω 6 Recommended Standard version C: PC 0

.., FPGA., VME,., PT7. VME con VME con ADDR DATA DDR Mezz Card con 6 CPLD test 6 CPLD 7 FPGA 7 90 FPGA test 6 GbE PHY 6 TTCrq con Flash RS LED LED LEMO RJ Infiniband x con.: PT7. PT7... FPGA FPGA Xilinx Kintex-7 FPGA XC7KT-FFG900. T,. I/O Kintex. T. FFG900, FFG676, FBG DDR SDRAM FFG900. DDR MT/s, GTX 0.Gbps []. T GTX 6, PT7 8, PT7, GTP Transceiver PT6 7. 7 Infiniband x-x cable 06

.: Kintex-7 [] 8 BRAM 9 (Kb) GTX I/O I/O XC7K60T,0,700 8 8 00 XC7KT 0,90 6,00 6 0 00 XC7K0T 6,0 8,60 6 0 00 XC7K0T 6,0 0,060 8 00 XC7K80T 7,60,80 8 00,. FPGA mm mm. 00LFM 0 6. /W Advanced Thermal Solutions ATS-0D-C-R0... CPLD CPLD Xilinx CoolRunner-II CPLD XCC6-7PQ08. CPLD, TGC,. VME FPGA. VME,. FPGA SelectMAP[6]. CPLD, FPGA,. PT7 CPLD, VME FPGA, CPLD... Ethernet PHY UTP GbE, PHY Texas Instruments DP886 Gig PHYTER. 0BASE-T (Full/Half duplex), 00BASE-TX (Full/Half duplex), 000BASE-T (Full/Half duplex) 6,. MHz, 000BASE-T MHz FPGA. PHY, LED. ACT ( / ), LINK ( ), 00M (00BASE-TX ) G (000BASE-T ). 8 LUT 8 FF 9 BRAM 6Kb 0 Linear Feet per Minute:. 00LFM = m/s 07

d WE# Co Mode registers 6 Refresh counter Rowaddress MUX Bank 0 rowaddress latch and decoder Bank Bank Bank Bank Bank 6,8 Bank Bank Bank Bank Bank 0 memory array (6,8 x 8 x 6) 6 READ FIFO and data MUX 8 DLL READ drivers DQ[7:0] DQS, DQS# DQ8 (... 8) TDQS# DQ[7:0] V DDQ / Sense amplifiers 8,9 6 BC OTF BC sw R TT,nom R TT(WR) sw A[:0] BA[:0] 7 I/O gating DM mask logic Bank Address control logic register.. DDR SDRAM (8 x6) Column (, ) DQS, DQS# V DDQ / WRITE 6 8 Data drivers R TT,nom R TT(WR) interface and Data input sw sw decoder logic PT7 SDRAM microncolumn- address 7 MTJ6M6JT-E. DDR- DM/TDQS 0 (shared pin) counter/ latch Columns 0,, and, 667MHz. 6bit (select upper or lower nibble for BC) MT/s 6 =.Gbps. DDR SDRAM.6. Figure : 6 Meg x 6 Functional Block Diagram CK, CK# Column ODT ODT control ZQ RZQ RESET# CKE V SSQ A Control logic ZQCL, ZQCS ZQ CAL To ODT/output drivers CK, CK# CS# RAS# CAS# WE# Command decode Mode registers 6 BC (burst chop) OTF Refresh counter Rowaddress MUX Bank 0 rowaddress latch and decoder Bank 7 Bank 6 Bank Bank Bank Bank Bank 8,9 Bank 0 memory array (89 x 8 x 8) Bank 7 Bank 6 Bank Bank Bank Bank Bank Column 0,, and READ 8 FIFO 6 and data MUX CK, CK# DLL READ drivers V DDQ / R TT,nom R TT(WR) sw sw (... 6) DQ[:0] LDQS, LDQS#, UDQS, UDQS# DQ[:0] Sense amplifiers V DDQ / 6,8 8 BC R TT,nom R TT(WR) BC sw sw A[:0] BA[:0] 6 Address register Bank control logic I/O gating DM mask logic (8 x8) Column decoder OTF 8 Data interface 6 Data WRITE drivers and input logic V DDQ / R TT,nom sw (... ) R TT(WR) sw LDQS, LDQS# UDQS, UDQS# 0 Columnaddress counter/ latch 7 Columns 0,, and (, ) LDM/UDM CK, CK# Column (select upper or lower nibble for BC).6: DDR SDRAM [6] PDF: 0900aef86aa906 Micron Technology, Inc. reserves the right to change products or specifications without notice. Gb_DDR_SDRAM.pdf Rev. K 8/ EN 006 Micron Technology, Inc. All rights reserved. SDRAM,,.,. t RCD (Row to Column Delay). t CL (CAS Latency).,. t RP (Row Precharge Delay)..ns[6]., MHz 6MHz, 0Gbps. 0MHz 00bit, 00bit L Buffer. Gb, L Buffer M... Flash memory Flash memory EEPROM ROM, NAND NOR. NAND, byte NOR. PT7 Flash memory micron NOR Flash memory NQ08. FPGA SPI (Serial Peripheral Interface) 08

, 08MHz. FPGA CPU, OS...6 PT7.... JP, JP,. JP..: PT7 dst src frequency FPGA GTX CPLD NIM out X 0MHz JP X MHz LVDS X MHz LVDS VME sysclk 6MHz NIM in JP TTC cmos0 0MHz JP TTC lvds60 60MHz LVDS TTC another 0MHz JP JP JP JP FPGA nim JP dst GTX FPGA GTX bank. FPGA., NIM out LEMO, NIM in out. src X X. X LHC 0MHz,. X DDR. X X, GTX. TTC. cmos0 TGC, lvds60. GTX GTX. another JP,. 09

. PT7. FPGA,... VME PT7 VME, bit, bit VME. CPLD. VME., Low active *. : D[:0] VME bit CPLD FPGA. FPGA, VME. FPGA I/O., VME CPLD FPGA : A[:] A[:0]. bit, match* Low., A[9] CPLD FPGA, 0 CPLD, FPGA. PT7. Byte Access byte VME PT7..: PT7-0 9 8-6 -, 0 FPGA Access board address FPGA address[6:0] Byte Access CPLD Access board address 0 CPLD address[:0] Byte Access VME. VME.6. AS* Low, CPLD (match* ) (AM [:0] LWORD* ). A[9] WRITE*.. A[9] Low CPLD, A[:] (a) DS* [:0] Low, WRITE* High. DTACK* Low,. 0

(b) DS* [:0] Low, WRITE* Low. DTACK* Low,. A[9] High FPGA. FPGA A[8:] (a) DS* [:0] Low, WRITE* High rstr* (read strobe) Low. FPGA rstr* Low. CPLD DTACK* Low, (b) DS* [:0] Low, WRITE* Low wstr* (write strobe) Low. FPGA wstr*. CPLD DTACK* Low,.6: VME VME AS* AS*, A[:], AM [:0], LWORD*, WRITE* DS* [:0] DS* [:0], D[:0] (WRITE* = Low) PT7 DTACK* DTACK*, D[:0] (WRITE* = High).. GTX 8. Infiniband x, PT7. Infiniband 9 6,..7 Infiniband. Mellanox CTMC00 DGR0HS8E0..7: Infiniband

Infiniband DDR (double data rate: Gbps), = 0Gbps. 8b0b, 0 0.8 = 6Gbps, SL (0.88Gbps)... FPGA GMII/MII PHY. MII (Media Independent Interface) MAC PHY. GMII (Gigabit Media Independent Interface) MII 000BASE-T. PHY MDI HFJ-G0E (HALO Electronics),. MDI (Medium Dependent Interface) PHY..., CMC. PT6,. G-Link S-Link, LVDS..8 G-Link ( ) LVDS ( )..8:.. TTC ATLAS TTC. TTC, TTCrq. TGC TTCrq, LA, ECR, BCR..9 TTCrq. SL TTC, TTC, PT7 TTCrq.. SL TTCrq,. Common Mezzanine Card: VME CompactPCI. IEEE86 []

.9: TTCrq..6 I/O NIM NIM. LEMO,,. PT7,. RSC RSC 0. 8,. Linear Technology LTC80. FPGA CPU. JTAG FPGA, CPLD JTAG. Xilinx. Flash memory,. CPLD FPGA 6. TTC.

. PT7 0,. PT7... PT7 00MHz., 0.. Layer.,.0...0: PT7.. PT7, PT7.,.,.. PT7, PT7. PT7 (txpt7) HpT NSW 00bit, GTX. 00 0MHz. = Gbps (. 8b0b ). GTX Gbps,, Infiniband x. PT7 (rxpt7), BCID. 6bit,. TTC LA LID, SiTCP 8bit. rxpt7 PC, SiTCP GbE PC. PC,., txpt7., PT7. SL.

.: PT7

6, SiTCP GTX Transceiver. SiTCP, 00Mbps. GTX, 0m 0Gbps., DAQ,., ATLAS,., R&D.,,.. 6.: ATLAS [] 6