2. SIV53002-3.0 Stratix IV GX 2 3 2 7 2 9 2 10 2 11 2 13 2 1 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 2 2 2 1. Architecture Device Speciication Transceiver Coniguration Select Options in the Dynamic Reconiguration Controller (i required) Clocking Implementation Create Transceiver Instances Is Dynamic Reconiguration Required? No Yes Create a Dynamic Reconiguration Controller using the ALTGX_Reconig MegaWizard Create Reset and Control Logic Create Data Processing Logic Integrate the Design Yes Is Simulation Required? Functional Simulation Include Stratix IV GX ALTGX MegaWizard Plug-In Manager generated wrapper ile (.v or.vhd) and ALTGX_Reconig MegaWizard generated wrapper ile (i used in the design) No Compilation Synthesize the Design Add Altera Simulation Library Files Require SignalTap or Veriication? Yes No Simulate the Design Create Pin and OCT Assignments Create Timing Constraints Veriication Add signals to SignalTap II Logic Analyzer Create Clock Grouping Constraints i Required Include SignalTap ile (.stp) in the Compilation Compile the Design Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation
2 2 3 Stratix IV GX Stratix IV GX V OD FPGA DSP Stratix IV Volume 4 Stratix IV DC FPGA V CCHT x V CCA_L/R 2 Stratix IV Pin Connection Guidelines PCS PMA PCS FIFO PPM parts per million Stratix IV Volume 4 Stratix IV DC Stratix IV GX PCS PMA 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 4 2 FPGA PMA PCS 8B/10B Quartus II PCS PMA ALTGX MegaWizard Plug-In Manager ALTGX MegaWizard Plug-In Manager 1 ALTGX MegaWizard Plug-In Manager Stratix IV Volume 3 ALTGX FPGA FPGA 2 8 FPGA PMA Stratix IV GX Stratix IV Volume 2 Stratix IV Stratix IV GX - Quartus II Stratix IV Volume 2 Stratix IV GX PMA V OD DC FPGA PMA Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation
2 2 5 1 Quartus II.mi Quartus II ALTGX_RECONFIG MegaWizard Stratix IV Volume 3 ALTGX_RECONFIG MegaWizard Plug-In Manager 1 Stratix IV GX PVT Stratix IV GX Receiver only Transmitter and Receiver PMA Stratix IV Volume 2 Stratix IV Stratix IV GX reclk reclk reclk FPGA PLL I/O PLL PLL ATX advanced technology extended PLL phase-locked loop ATX PLL Stratix IV GX PCS PMA I/O PLL Stratix IV Volume 2 Stratix IV FPGA : 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 6 2 FPGA Stratix IV Volume 4 Stratix IV DC FPGA 1 FPGA PMA FPGA FPGA GPLL GPLL Stratix IV Volume 2 Stratix IV Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation
2 2 7 3 FPGA Quartus II ALTGX MegaWizard Plug-In Manager ALTGX MegaWizard Plug-In Manager ALTGX MegaWizard Plug-In Manager Stratix IV Volume 3 ALTGX ALTGX MegaWizard Plug-In Manager 2 MegaWizard Plug-In Manager 2 8 10 16 20 32 40 General Single-width Double-width ALTGX MegaWizard Plug-In Manager : tx_digitalreset rx_analogreset rx_digitalreset PCS PMA pll_powerdown CMU PLL 8B/10B V OD V CM rx_enapatternalign pll_locked rx_reqlocked rx_syncstatus rx_patterndetect pll_locked rx_reqlocked ALTGX MegaWizard Reconig FPGA tx_coreclk rx_coreclk 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 8 2 FPGA Stratix IV Volume 2 Stratix IV Reconig channel interace Use alternate PLL Reconig logical channel addressing logical PLL index type o reconiguration to select Stratix IV Volume 2 Stratix IV CMU PLL Finish ALTGX ALTGX_RECONFIG MegaWizard CMU PLL ALTGX_RECONFIG MegaWizard Plug-In Manager ALTGX_RECONFIG Stratix IV Volume 2 Stratix IV ALTGX MegaWizard Plug-In Manager tx_digitalreset rx_analogreset rx_digitalreset pll_powerdown CMU PLL pll_powerdown CMU PLL pll_powerdown Stratix IV Volume 2 FPGA CDR CDR CDR rx_locktoreclk rx_locktodata CDR Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation
2 2 9 2 PPM FPGA PPM PPM CDR FPGA PCS 8B/10B FPGA PCS FPGA FPGA Synplicity Quartus II PMA FPGA PCS Quartus II SRAM Object File.so.po Stratix IV GX I/O Quatus II Assignment Editor 1 Quartus II Quartus II Help Tutorial : Stratix IV GX I/O 1.5-V PCML LVDS tx_coreclk rx_coreclk FPGA 0ppm Quatus II Stratix IV Volume 2 Stratix IV Common Clock Driver Selection Rules reclk On-Chip Termination : OCT OCT Stratix IV Volume 2 Stratix IV TimeQuest TimeQuest Quartus II FPGA.so 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 10 2 Quartus II Quartus II Quartus II Fitter Processing Compilation Report Fitter Fitter Fitter FPGA Quartus II GXB Receiver GXB Transmitter Fitter Pin-Out File Fitter Pin-Out ile Quartus II I/O Quartus II PIN.pin.pin Stratix IV GX Fitter Resource Section GXB Transmitter channel GXB Transmitter PLL PLL GXB Receiver channel Global and other ast signals ALTGX MegaWizard Plug-In Manager Quartus II SignalTap SignalTap SignalTap Quartus II STP.stp.stp Quartus II SignalTap.so Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation
2 2 11 Quartus II.stp JTAG SignalTap Quartus II Volume 3 In-System Design Debugging Stratix IV GX PCS PMA Stratix IV Volume 2 Stratix IV Transceiver Architecture Loop-Back Stratix IV GX ALTGX MegaWizard ModelSim 2 1 VHDL Verilog 220pack 220model altera_m_components altera_m sgate_pack sgate stratixiv_hssi_component stratixiv_hssi_atoms Quartus II <Quartus II >/eda/sim_lib ModelSim VHDL ModelSim lpm sgate altera_m stratixiv_hssi <Quartus II \quartus\eda\sim_lib> 2 1 2 1. ( / ) 220pack 220model sgate pack lpm lpm sgate 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 12 2 2 1. ( / ) sgate altera_m_components altera_m stratixiv_hssi_component stratixiv_hssi_atoms user design iles sgate altera_m altera_m stratixiv_hssi stratixiv_hssi work ModelSim Properties General Compile to library 2 2 Stratix II GX ModelSim 2 2. ModelSim ALTGX ALTGX_RECONFIG MegaWizard Plug-In Manager.v.vhd Verilog ALTGX ALTGX_RECONFIG MegaWizard Plug-In Manager Verilog.v Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation
2 2 13 1 3 : 3 PCS PMA 2 2 1 2 2. 1 Stratix IV GX? 0 Receiver and Transmitter FC4G 4.25 Gbps 106.25 MHz 1 Receiver and Transmitter FC1G 1.0625 Gbps 53.125 MHz 2 Transmitter Only FC4G 4.25 Gbps 106.25 MHz Stratix IV Volume 4 Stratix IV DC 3? 4.25 Gpbs 1.0625 Gpbs? 2 CMU PLL 2 4.25 Gbps 1.0625 Gbps CDR Stratix IV Volume 4 Stratix IV DC 8B/10B 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 14 2 PCB 8B/10B? 2 EOFt End-o-Frame EOFt EOFt Stratix IV GX EOFt? FPGA 8B/10B PCS 8B/10B? FPGA 2 Transmitter and Receiver 1 Transmitter Only Stratix IV GX 2 2? FPGA 20 40 4.25 Gbps 1.0625 Gbps FPGA 10 FPGA 8B/10B PMA ALTGX ALTGX_RECONFIG Stratix IV Volume 2 Stratix IV ALTGX_RECONFIG ALTGX Stratix IV Volume 2 Stratix IV PMA ALTGX Reconig ALTGX_RECONFIG.mi Stratix IV Volume 2 Stratix IV CMU PLL 2? Stratix IV GX 2 reclk reclk? reclk 50 MHz 622.08 MHz Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation
2 2 15 FPGA? FPGA tx_clkout rx_clkout FPGA Stratix IV GX? Stratix IV Volume 2 Stratix IV Non-Bonded Transceiver Clocking 2 3 1 CMU clock multipler unit PLL CDR PMA PCS 2 3 2 3. Transceiver Block Channel 0 (4.25 Gbps) TX RX reclk0 (106.25 MHz) One CMU PLL Conigured or 4.25 Gbps Data Rate Channel 1 (1.0625 Gbps) reclk1 (53.125 MHz) Second CMU PLL Conigured or 1.0625 Gbps Data Rate TX RX Channel 2 (4.25 Gbps) TX 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 16 2 2 ALTGX MegaWizard Plug-In Manager Stratix IV Volume 3 ALTGX FC4G 0 2 4 2 14 FC4G ALTGX MegaWizard Plug-In Manager 0 General Stratix IV GX Basic 2 4 2 4. FC4G General Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation
2 2 17 2 5. FC4G Instance PLL/Ports PLL/Ports 2 5 Train Receiver CDR rom PLL inclk CMU PLL CDR pll_powerdown CMU PLL pll_locked CMU PLL pll_locked High rx_reqlocked CDR CDR rx_reqlocked Low PCS rx_digitalreset CDR Stratix IV Volume 2 Stratix IV 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 18 2 Ports /Cal Blk 2 6 2 6. FC4G Instance Ports/Cal Blk Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation
2 2 19 2 7. FC4G Instance Rx Analog RX Analog 2 7 Stratix IV Volume 3 ALTGX 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 20 2 2 8. FC4G Instance TX Analog TX Analog 2 8 Stratix IV Volume 4 Stratix IV DC Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation
2 2 21 2 9. FC4G Instance Reconig Reconig Reconig 2 9 0 Oset Cancellation or Receiver Channels reconig_romgxb reconig_togxb 1 Stratix IV Volume 2 Stratix IV 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 22 2 2 10. FC4G Instance Lpbk Lpbk 2 10 Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation
2 2 23 2 11. FC4G Instance Basic /8B10B Basic/8B10B Basic/8B10B 2 11 2 11 : (1) 8B/10B 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 24 2 Word Aligner K28.5 What is the word alignment pattern? 10 K28.5 2 12. FC4G Instance Word Aligner rx_patterndetect rx_syncstatus rx_patterndetect Finish MegaWizard Plug-In Manager Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation
2 2 25 FC1G 1 FC1G FC4G General 2 13 Reconig 4 2 13. FC4G Instance Channel 1 General 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 26 2 FC4G Transmitter Only 2 0 2 14 Transmitter Only Transmitter Only ALTGX MegaWizard Plug-In Manager 2 14. FC4G_TXONLY Instance Channel 1 General Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation
2 2 27 Reconig 8 2 15 PMA Analog controls Transmitter Only reconig_romgxb reconig_togxb 2 reconig_romgxb/reconig_togxb Quartus II Transmitter Only Analog options... 2 15. FC4G_TXONLY Instance Reconig Stratix IV Volume 2 ALTGX_Reconig 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 28 2 Stratix IV Volume 2 Stratix IV 2 16 PMA Number o Channels Stratix IV Volume 2 Stratix IV ALTGX_Reconig ALTGX_Reconig reconig_romgxb[16:0] FC4G 0 reconig_romgxb[33:17] FC1G 1 reconig_romgxb[50:34] FC4G Transmitter Only 2 ALTGX_RECONFIG reconig_togxb[3:0] 3 2 16. ALTGX_Reconig Reconiguration Settings FPGA 0 2 CMU PLL 1 2 CMU PLL Transmitter Only Receiver and Transmitter ALTGX MegaWizard Plug-In Manager pll_powerdown CMU PLL 0 2 CMU PLL ALTGX 0 2 pll_powerdown Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation
2 2 29 0 1 2 rx_digitalreset rx_analogreset tx_digitalreset 2 17 3 FPGA 2 17. FPGA User Logic rx_reqlocked reset control logic tx_digitalreset rx_digitalreset rx_analogreset ALTGX Instance Channel0 Starting channel number = 0 data processing logic transmitter side logic receiver side logic 8B/10B encoder tx_datain rx_patterndetect reconig_romgxb[16:0] reconig_togxb[3:0] ALTGX_RECONFIG Instance data processing logic 8B/10B decoder rx_syncstatus rx_dataout reconig_romgxb[16:0] reset control or CMU PLL pll_locked pll_powerdown reconig_romgxb[50:34] reconig_romgxb[33:17] reset control logic tx_digitalreset ALTGX Instance Channel 2 reconig_romgxb[16:0] reconig_togxb[3:0} data processing logic transmitter side logic 8B/10B encoder tx_datain Starting channel number = 8 reset control logic pll_powerdown pll_locked rx_reqlocked tx_digitalreset rx_digitalreset rx_analogreset ALTGX Instance Channel 1 reconig_togxb[3:0] reconig_romgxb[16:0] data processing logic transmitter side logic 8B/10B encoder tx_datain receiver side logic rx_patterndetect Starting channel number = 4 data processing logic 8B/10B decoder rx_syncstatus rx_dataout FPGA 8B/10B 2 29 2 17 FPGA 2009 3 Altera Corporation Stratix IV Device Handbook Volume 3
2 30 2 SignalTap SignalTap -FPGA.so 3 Quartus II v.8.1 Stratix IV GX OCT 4 2 11 2 3 2 3. 2009 3 v3.0 2 3 2 4 2008 11 v2.0 2 3 2 8 2 14 2 26 FC4G Transmitter Only 2 2 27 ALTGX_Reconig 2 1 2 4 2 5 2 6 2 7 2 8 2 10 2 11 2 12 2 13 2 14 2 9 2 15 2 16 2008 5 v1.0 Stratix IV Device Handbook Volume 3 2009 3 Altera Corporation