1 -- 7 7 2008 12 7-1 7-2 c 2011 1/(12)
1 -- 7 -- 7 7--1 2008 12 1960 1970 1972 U.C. Berkeley SPICE Simulation Program with Integrated Circuit Emphasis 1) SPICE SPICE 7--1--1 7 1 7 1 1 netlist SPICE 2) 7 2 7 2(b) R1 C1 V1 Rxxxxxxx 1 2 (Ω) Rxxxxxxx R C V 7 1 xxxxxxx c 2011 2/(12)
(a) (b) 7 2 R1 R2 ROUT RIN R3A2 Node SPICE 2 GND 0.MODEL GUI Graphical User Interface c 2011 3/(12)
7 1 R Resistor N+ N Ω C L D Capacitor N+ N F Inductor N+ N H K L1 L2 Q J M Mutual Inductor Diode N+ N NC NB BJT NE NS ND NG JFET NS MOS ND NG MOSFET NS NB T N1 N2 Lossless Transmission Line N3 N4 U N1 N2 LossyTransmission Line N3 N4 V N+ N Independent Voltage Source I N+ N Independent Current Source E N+ N V oltage Controlled V-Source NC+ NC G N+ N V oltage Controlled C-Source NC+ NC H N+ N Current Controlled V-Source VNAM F N+ N Current Controlled C-Source VNAM 2 SPICE..PZ.DISTO.SENS (a).dc.op.op.dc c 2011 4/(12)
(b).ac (c).tran 7--1--2 7 3(a) µa741 3) R L C 7 3 µa741 7 3(a) 7 3(b) SPICE c 2011 5/(12)
7 3(b) 0 V SPICE.SUBCKT X 7--1--3 VHDL Verilog HDL 1990 VHDL-AMS Verilog-AMS Verilog-AMS 7 4 4) C Pascal 7 4 Verilog-AMS MEMS 3) PSP HiSIM 5) 1) D. O. Pederson, A Historical Review of Circuit Simulation, IEEE Trans. Circuits and Systems, vol.cas-31, no.1, pp.103-111, Jan, 1984. c 2011 6/(12)
2),, Spice, pp.151-171,, 2002. 3) D. Jansen, The Electronic Design Automation Handbook, pp.238-325, Kluwer Academic Pub., 2003. 4),,, pp.264-291,, 2003. 5), HiSIM PSP, 19, pp.63-68, 2006. c 2011 7/(12)
1 -- 7 -- 7 7--2 2008 12 7--2--1 NA STA SPICE MNA v 1 i 1 G 1 G 2 G3 v 2 v in i in i 2 i 3 v 3 i 4 G 4 0 7 5 7 5 ν 1 ν 3 = ν in G 1 G 1 0 1 G 1 G 1 + G 2 + G 3 G 2 0 0 G 2 G 2 + G 4 1 1 0 1 0 v 1 v 2 v 3 i in 0 0 = 0 1) 7 2 G i j i i j j G i j j i G v in (7 1) c 2011 8/(12)
7 5 G 1 v 1 1 v 2 2 (7 1) G 1 7 3 k 7 2 i j RHS i G G j G G 7 3 i j k RHS i 1 j 1 k 1 1 v 7--2--2 1 LU N O(N 3 ) 90 2) SPICE LU L U LU re-ordering 2 x f (x) = 0 (7 2) SPICE Newton-Raphson (7 2) c 2011 9/(12)
x n = x n 1 ( f ) 1 f (x n 1 ) x (7 3) n f / x f x Jacobian N N N x 0 A (7 3) AX = f (x n 1 ) (7 4) x n = x n 1 + X 3 Cẋ(t) + f (x(t)) = 0 (7 5) C t (x t x t 1 )/ t t x C x t x t 1 + f (x t ) = 0 (7 6) t SPICE (x t x t 1 )/ t t + 1/2 x f (x t+1/2 ) t + 1 t C x t x t 1 t + f (x t) + f (x t 1 ) 2 (7 6) (7 7) = 0 (7 7) F(x t ) = 0 (7 8) x t x t x t 1 x t 1 c 2011 10/(12)
7--2--3 R i 12 = (v 1 v 2 )/R 2 3 1 BJT SPICE Ebers-Moll Gummel-Poon VBIC MEXTRAM 3) 2 MOSFET SPICE MOSFET.MODEL LEVEL V GS V T I D MOSFET LEVEL = 1 MOS1 Shichman-Hodges MOS1 NMOS 2) a) V GS < V T I D = 0 b) V T < V GS 0 < V DS < V GS V T W [ I D = K p (V GS V T )V DS V DS 2 ] (1 + λv DS ) L e f f 2 c) V T < V GS V GS V T < V DS W I D = K p (V GS V T ) 2 (1 + λv DS ) 2L e f f c 2011 11/(12)
V T = V T0 + γ[(φ V BS ) 1/2 Φ 1/2 ], L e f f = L 2L D K P λ Φ V T0 L D 1 + λv DS MOS1 SPICE MOS1 MOS2 MOS3 BSIM1 BSIM2 0.25 µm BSIM3 BSIM4 4) BSIM RF 5) PSP HiSIM 1),,, pp.264-291,, 2003. 2) D. Jansen, The Electronic Design Automation Handbook, pp.238-325, Kluwer Academic Pub., 2003. 3), SPICE, pp.177-192, CQ, 2005. 4) Y. Cheng and C. Hu,, MOSFET BSIM3,, 2002. 5) M. Miura-Mattausch, et.al, Circuit Simulation Models for Coming MOSFET Generations, IEICE Trans. Fundamentals, vol.e85-a, no.4, pp.740-748, April, 2002. c 2011 12/(12)