スライド 1

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1 Front End Processes FEP WG - - NEC 1 ITRS2006 update 2 ITRS vs. 2-1 FET 2-2 Source Drain Extension 2-3 Si-Silicide

2 , FEP Front End Processes Starting Materials: FEP Si,, SOI SOI: Si on Insulator, SON: Si on Nothing, Si on X: Si FDSOI: Fully Depleted SOI Surface Preparation: High-k: High Dielectric Constant Material, SiO 2 High SD: Source Drain SDE Deep SD SDE, SDExt.: Source Drain Extension Xj: SD well. 1e18cm -3, 5e18cm -3 Silicide: Si, NiSi: Nickel mono-silicide, CoSi 2 : Cobalt di-silicide, TiSi 2 : Titanium di-silicide, ErSix: Erbium silicide RTA: Rapid Thermal Anneal, Schottky-SD: SDE Si Silicide N D : Donor Concentration, N A : Acceptor Concentration Si/Silicide ITRS -cm 2 -µm 2 2

3 Front End Processes WG NEC * * * Selete Selete * SEAJ SEAJ * Start. Mat. WG SUMCO TECHXIV 3

4 - Starting Materials Silicidation Memory - Surface Preparation STRJ Stacked Cap. DRAM FeRAM Etch Memory DRAM Flash FeRAM PCRAM Thermal/Thin Films High-k Poly-SiGe Metal Gate Doping Starting Materials Anneal SOI Elevated S/D (SiGe) SON Contact (Silicide) Strained-Si/SiGe Si on X 4

5 1 Thermal Thin Film 2006 Updates High-k Metal FDSOI 2010 First Year of Volume Production SiON poly-si LSTP LOP HP High-k poly-si LSTP High-k Metal LOP HP LOP HP LSTP Fully Depleted SOI (FDSOI) HP HP LOP HP = High Performance Applications LOP = Low Operating Power Applications LSTP = Low Standby Power Applications 5

6 1 Stacked DRAM 2006 Updates WAS IS Year of Production DRAM M1 ½ pitch (nm) Dielectric constant Capacitor Dielectric Capacitor Dielectric Al 2 O 3, HfO 2, Ta 2 O 5 Ta 2 O 5, TiO 2 Ultrahigh k, new materials Al 2 O 3, Al 2 O 3, HfO 2, Ta 2 O 5, Ultrahigh k, Ta 2 O 5 TiO 2, ZrO 2 new materials 2007 Stacked DRAM 6

7 US FEP Raj Jamm 2005 vs. ITRS2006 update Note Alternative device designs, employing offset spacers and deeper extension junctions which preserve or even extend the effective channel length, may allow deeper extension junctions. A more comprehensive analysis will be performed in

8 2-1 Lg FET ITRS Table High Performance 0.6*SD_Xj 0.6*SDE_Xj SDE_Xj Lg SD_Xj 2*Design Rule (2*Half Pitch) 1.1*Lg 1um ( ) 1.1*Lg ~0.35*Lg SD=Source Drain SDE=Source Drain Extension 8

9 2-1 = = /10 W W 500 (500 sq) 50 9

10 2-1 45nm n HP n-fet nm 20nm W=1um 20nm (SD_Xj) 12nm 6.5nm (SDE_Xj) 45nm 5 11 Si/Silicide +SD SDE 1 <<SD 2 WG 10

11 2-1 ITRS Table HP LSTP HP LSTP 1/2 (nm) Lg (nm) SDE (nm) SD (nm) n-ch SDE (Ω/ ) Si-Silicide (Ω-um2) p-ch SDE (Ω/ ) Si-Silicide (Ω-um2) (na/um) Si-Silicide MPU(HP) 20%( ) SDE 15%( 3%) 11

12 2-2 SDE ITRS SDE SDE nm ITRS'99(150~35nm) ITRS'01(130~32nm) ITRS'05( 80~32nm) 130nm node 100nm node HP nm 0 ITRS 99 ITRS 01 ITRS 01 ITRS 03 ITRS 03 ITRS 05 msec : Si SD well =1e18cm -3, 5e18cm -3 12

13 2-2 SDE msec Lamp or Laser 1msec 100µm Diffusion-less P. Timans, MRS2006 spring, C1.1 RTA mm 1cm 13

14 2-2 SDE msec - - Flash Lamp Cap Laser( =10.6µm) (Brewster ) Cap Cap Cap Flash Lamp Laser( =0.81µm) 14

15 2-2 SDE ITRS nm n SDE HP Xj=6.5nm, LOP Xj=8.1nm, LSTP Xj=9.8nm ( 1 3) B(11) 100eV BF 2 (49) As(75) 500eV ( ) =? B 18 H 22 Cluster Ion Beam Plasma Dope 15

16 2-2 SDE SDE Ge+C+B, P+C Si.Electromagnetic Anneal Schottky-SD SDE Si Silicide 16

17 2-3 Silicide Si/Silicide +SD 45nm HP n-fet 90nm 20nm W=1um 20nm (SD_Xj) R C R SD 100 x 55nm/1µm SD 50nm 90nm 5 ITRS2006 Si-Silicide 4.8 -µm 2 R C =4.8/0.09=53 R SD NiSi 17

18 2-3 Silicide NiSi Si P (cm -3 ) NiSi P n + -Si Ni Si (nm) Si, Ni (cps) µm n+ -type N D : 2x10 20 cm Si Schottky (ev) NiSi NiSi 2 CoSi 2 TiSi 2 p + -type N A : 1x10 20 cm -3 NiSi NiSi 2 CoSi 2 TiSi NiSi/n+Si NiSi/p+Si Schottky SiGe, 18

19 2-3 Silicide SD 45nm HP n-fet 90nm 20nm R C SiO 2 R SD SOI Si R SD Si/Silicide SOI Ultra Thin Body SOI Si 19

20 2-4 Ioff Si LSTP 4( ) 6 ( ) HP 8( ) 10 ( ) Silicide Silicide Si 50nm Id(A/um) 1e-03 1e-06 1e-09 HP LSTP 1e Vg(V) 20

21 2-5 45nm 32nm HP LSTP HP LSTP 1/2 (nm) Lg (nm) SDE (nm) SD (nm) n-ch SDE (Ω/ ) Si-Silicide (Ω-um2) p-ch SDE (Ω/ ) Si-Silicide (Ω-um2) Dual Silicide n-ch ErSi 2 (na/um) SDE. SDE 10 15nm Lg 10nm FET. 21

22 2-5 Breakthrough - Schottky_SD, SDE Si Silicide - SDE SDE Si Silicide Si-Silicide SIlicide,, (+ ) Si Deep-SD, SOI A. Kinoshita et al., VL2005, p.158 Q.T.Zhao et al., IWJT2006, p

23 ITRS2006 update High-k/Metal Gate, FDSOI Stacked DRAM STRJ SDE. msec Integration Si-Silicide 45nm NiSi Schottky-SD SDE,Si-Silicide, 23

スライド 1

スライド 1 High-k & Selete 1 2 * * NEC * # * # # 3 4 10 Si/Diamond, Si/SiC, Si/AlOx, Si Si,,, CN SoC, 2007 2010 2013 2016 2019 Materials Selection CZ Defectengineered SOI: Bonded, SIMOX, SOI Emerging Materials Various