NAND FF,,
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- ともなり たかひ
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1
2 NAND FF,,
3 3. アドレス ( 番地 ) bit(0255) 7(3+4) 16 8 命令表 (0~255) コード内容 ( 機械語 ) ( 次の番地の内容 )+( 次の次の番地の内 99 容 ) の結果を次の次の次に書いてある番地に格納 2STOP A0A7, A8A15 D0D7 2
4 4.2. A B D H F 16bit 8bit C E L SP PC 1 2 F 3 4 PC 3 (8bit) (16bit)
5 PC=0 PC (PC) (PC) (PC)(PC)+ 5 SP 0 (a) (b) SP (500) (a) [(SP1)],[(SP2)]21 (SP)(SP)2 (PC)100 (b) (PC)[(SP+1)],[(SP)] (SP)(SP) SP (498) 2 4
6 (a) (b) (d) (c) SP (500) SP (498) 2 SP (496) (a) 1 [(SP1)],[(SP2)]21 (SP)(SP)2 (PC)100 (b) 2 [(SP1)],[(SP2)]130 (SP)(SP)2 (PC)200 (c) 1 (PC)[(SP+1)],[(SP)] (SP)(SP)+2 (d) (PC)[(SP+1)],[(SP)] (SP)(SP)+2 5
7 B D H A T C E L F 8bit 6 ALU AND OR NOT EX-OR F S Z AC P CY MSB LSB
8 2 7
9 4.5. 8
10 CPU 1 CPU8085A 64k 8bit CPU 8085A A8-A15 ALE AD0-AD7 RD WR IO / M 8 I0 I1 E 2-4 O0 O1 O2 O3 E I1 I k8bit A8-A15 A0-A7 O3 O2 O1 O D0-D7 WE CS
11 3 CPU8085A 1k 8bit CPU A A A8 A15 A0-A7 A14 I0 O0 D0-D7 A13 I1 O1 WE A12 E O2 A11 O3 A10 A9 A8 A8-A9 A0-A7 D0-D7 ALE WE AD0-AD7 A9 A8 RD A0-A7 D0-D7 WR WE IO / M A9 A8 A0-A7 D0-D7 WE 4 CPU8085A 1k 4bit CPU 8085A A15 A14 A13 A12 A11 A10 A8-A9 ALE AD4-AD7 AD0-AD3 RD WR IO / M 10 0 A8-A9 1k A0-A7 4bit D4-D7 WE CS 1 A8-A9 1k A0-A7 4bit D0-D3 WE CS 1k8bit CS 1k8bit CS 1k8bit CS 1k8bit CS 2 A8-A9 1k A0-A7 4bit D4-D7 WE CS 3 A8-A9 1k A0-A7 4bit D0-D3 WE CS
12 H (56H) CPU A 11
13 IO / M A8-A15 ALE AD0-AD7 RD MR T1 T2 T3 (1) (1) (12H) (1) (1) (5) (56H) (23H) (6)A (3) CPU 8085A A8-A15 (6) A ALE AD0-AD7 RD WR IO / M (1) 12H 8 (1) (1) (3) 0 RD+WR 1 (1) (2) 34H (5) 56H 64k8bit A8-A15 A0-A7 1234H 56H D0-D7 WE CS (4) 0 12
14 4.8. IC 1 SRAM S NMOS-SRAM NMOS FET Vg D G +VCC SRAM RAM RWM DRAM RAM ROM Q Q D D G D Vd S D S Q Vd G=1 ON G=0 OFF Vg Q S 1 SW ON SW OFF D 13 PROM ROM 0 D D S EPROM EEPROM S=0 Q=1, Q=0 Q=0,Q=1 Write S=1 D=1, D=0 Q=1 D=0, D=1 Q=0 Read S=1 D D 1 D D 0
15 2 SRAM bit I/O0I/O7 CSWE A0 A1 A D D S A5 0 A6 D D S 1 A12 D D S 255 CSWE IO CSWE CSWE D D D D S D S D S 5-32 D D D D S D S D S A0 A1 A4
16 5. 1 A B D H F C E L 2 A B C 3 D H E L A B D H F 16bit 8bit C E L SP PC (8bit) (16bit) H F 12H 15
17 (CPU Z80 1 r A B C D E H L (HL) LD A, r 7F A 7B 7C 7D 7E A r LD B, r B r LD C, r 4F A 4B 4C 4D 4E C r LD D, r D r LD E, r 5F A 5B 5C 5D 5E E r LD H, r H r LD L, r 6F A 6B 6C 6D 6E L r LD (HL), r HL r LD r, B 2 3E 06 0E 16 1E 26 2E 36 r B 2 1 LD B,C ; B C 41H 2 ; C D 3 LD H,A ; 4 ; 68H 5 LD B,12 ; B 12 06H 0CH 6 LD B,0CH ; B 0CH 06H 0CH 7 LD D,32H ; 8 LD H,12H ; H 12H 26H 12H LD L,34H ; L 34H 2EH 34H LD (HL),A ; (HL) A 77H ; (1234H) A 8bit (8bit) A F B C D E H (12H) L (34H) SP PC (16bit) H 16
18 9 LD H,12H ; H 12H 26H 12H LD L,34H ; L 34H 2EH 34H LD C,(HL) ; C (HL) 4EH ; C (1234H)1234H C H C ; ; ; B 8200H ; ; ; 2 r A B C D E H L (HL) ADD A, r ADC A, r 87 8F A 83 8B 84 8C 85 8D 86 8E A A + r A A + r + CY SUB r SBC A, r 97 9F A 93 9B 94 9C 95 9D 96 9E A A r A A r CY AND r XOR r OR r A7 AF B7 A0 A8 B0 A1 A9 B1 A2 AA B2 A3 AB B3 A4 AC B4 A5 AD B5 A6 AE B6 A A AND r A A Ex-OR r A A OR r CP r BF B8 B9 BA BB BC BD BE A r INC r DEC r 3C 3D C 0D C 1D C 2D r r + 1 r r 1 1 ADD A,B ; A A + B 80H B D H A T C E L 8bit 17 ALU AND OR NOT EX-OR F
19 2 ADC A,C ; A A + C + CY() 89H F S MSB Z AC P CY LSB 3+1+1(CY)= (CY)=6 3 SUB D ; A A D H 4 SBC A,E ; A A E CY H 311(CY)=1 321(CY)=0 5 AND H ; A A AND H H 6 OR L ; A A OR L H 7 XOR B ; A A B H (EX-OR) AND OR 8 CP D ; A D H if( ){ } 9 INC E ; E E + 1 H 10 DEC H ; H H 1 H 18
20 11 12 ADD A, 23H ; A A + 23H C6 23 SBC A, 0F0H ; A A F0H CY 13 CP 12 ; A 1210 Z80 ADD A, B 2 ADC A, B 2 C6 CE A A + B 2 A A + B 2 + CY SUB B 2 SBC A, B 2 D6 DE A A B 2 A A B 2 CY AND B 2 XOR B 2 OR B 2 E6 EE F6 A A AND B 2 A A Ex-OR B 2 A A OR B 2 CP B 2 FE A B LD HL, 1234 ; HL r 1 r 2 BC DE HL SP LD r 1 r 2, B 3 B r 1 r 2 B 3 B 2 2 LD BC, 8000H ; BC 8000H ADD HL, r 1 r HL HL + r 1 r 2 INC r 1 r r 1 r 2 r 1 r DEC r 1 r 2 0B 1B 2B 3B r 1 r 2 r 1 r ADD HL, BC ; HL HL + BC 4 ; HL HL + DE 5 INC BC ; BC BC ; HL HL 1 7 (1234H ) A () LD BC, 1234H ; BC 1234H LD (BC), A ; (BC) A () LD DE, 1234H ; DE 1234H LD (BC), A ; (DE) A () LD HL, 1234H ; HL 1234H LD (HL), A ; (HL) A Z80 LD (BC), A 02 (BC) A LD A, (BC) 0A A (BC) LD (DE), A 12 (DE) A LD A, (DE) 1A A (DE) LD (B 3 B 2 ), A 32 (B 3 B 2 ) A LD A, (B 3 B 2 ) 3A A (B 3 B 2 ) () LD (1234H), A ; (1234H) A 19
21 8 A (1234H ) () () () () LD (1234H), HL ; (1234H) L ; (1235H) H LD HL, (1234H) ; L (1234H) ; H (1235H) EX (SP), HL ; (SP) L ; (SP+1) H Z80 LD (B 3 B 2 ), HL 22 (B 3 B 2 ) L (B 3 B 2 +1) H LD HL, (B 3 B 2 ) 2A L (B 3 B 2 ) H (B 3 B 2 +1) EX (SP), HL E3 (SP) L (SP+1) EX DE, HL EB DE HL JP (HL) E9 PC HL LD SP,HL F9 SP HL H 12 JP (HL) ; PC HL HL 4 1 JP 1234H ; 1234H C JP, 1234H ; 1234H Z Z =1 NZ Z =0 C CY =1 20 Z80 JP B 3 B 2 JP Z, B 3 B 2 JP NZ, B 3 B 2 JP C, B 3 B 2 JP NC, B 3 B 2 JP PE, B 3 B 2 JP PO, B 3 B 2 JP M, B 3 B 2 JP P, B 3 B 2 C3 CA C2 DA D2 EA E2 FA F2 NC CY =0 0 M S =1 P S =0 0 PE =1 PO =0
22 H (a) (b) 150H (a) CALL 100H CD (b) RET C9 2 CALL, 1234H ; 1234H 21 Z80 CALL B 3 B 2 CALL Z, B 3 B 2 CALL NZ, B 3 B 2 CALL C, B 3 B 2 CALL NC, B 3 B 2 CALL PE, B 3 B 2 CALL PO, B 3 B 2 CALL M, B 3 B 2 CALL P, B 3 B 2 CD CC C4 DC D4 EC E4 FC F4 Z80 RET C9 RET Z C8 RET NZ C0 RET C D8 RET NC D0 RET PE E8 RET PO E0 RET M F8 RET P F0 S Z 0 AC 0 P 1 CY MSB LSB Z Z =1 NZ C NC M P Z =0 CY =1 CY =0 S =1 S =0 0 0 PE PO =1 =0 2 RET ;
23 1 #include <stdio.h> void main(void) { } int A, B; A = 0; for(b = 20; B > 0; B){ A = A + B; } 2 1. A 2. B 3. A A+B 4. B 5. B 3, 4 6. SUM A 3 start A0 B20 L1 AA+B BB1 Y B0 (SUM)A STOP 22
24 4 ; ; A 0 ; B 20 L1: ; A A + B ; B B1 ; if(b0) goto L1 ; if(z =0) goto L1 ; (SUM) A ; stop SUM: ; SUM 9000H ; 5 ; ORG 8000H ; 8000H LD A, 0 ; A 0 LD B, 20 ; B 20 L1: ADD A, B ; A A + B DEC B ; B B1 JP NZ, L1 ; if(b0) goto L1 ; if(z =0) goto L1 LD (SUM), A ; (SUM) A HALT ; stop ORG 9000H SUM: DB 0 END ; SUM 9000H ; 6 ; ORG 8000H ; 8000H 3E LD A, 0 LD B, 20 ; A 0 ; B C2 L1: ADD A, B DEC B JP NZ, L1 ; A A + B ; B B ; if(b0) goto L1 ; if(z =0) goto L1 LD (SUM), A ; (SUM) A HALT ; stop 00 ORG 9000H SUM: DB 0 END ; SUM 9000H ; 23
25 7 ; ORG 8000H ; 8000H 8000H 8002H 8004H 8005H 8006H 3E C2 L1: LD A, 0 LD B, 20 ADD A, B DEC B JP NZ, L1 ; A 0 ; B 20 ; A A + B ; B B1 8009H 800CH ; if(b0) goto L1 ; if(z =0) goto L1 LD (SUM), A ; (SUM) A HALT ; stop 9000H 00 ORG 9000H SUM: DB 0 END ; SUM 9000H ; 8 ; ORG 8000H ; 8000H 8000H 8002H 8004H 8005H 8006H 3E C L1: LD A, 0 LD B, 20 ADD A, B DEC B JP NZ, L1 ; A 0 ; B 20 ; A A + B ; B B1 8009H 800CH ; if(b0) goto L1 ; if(z =0) goto L1 LD (SUM), A ; (SUM) A HALT ; stop 9000H 00 ORG 9000H SUM: DB 0 END ; SUM 9000H ; H 24
26 11 A B Z 9000H PC E 00 LD A, 0 ; A LD B, 3 ; B L1: ADD A, B ; A A + B DEC B ; B B1 JP NZ, L1 ; if(b0) goto L1 L1: ADD A, B ; A A + B DEC B ; B B1 JP NZ, L1 ; if(b0) goto L1 L1: ADD A, B ; A A + B DEC B ; B B1 JP NZ, L1 ; if(b0) goto L1 LD (SUM), A ; (SUM) A HALT ; stop 25
27 5.5. if 1 Yes No if () { } else { } 2 A 3 if if (A = = B) { CP B ; AB JP Z, PROC1 } else { JP ENDIF ; } PROC1: ; else { } ENDIF: ; } ; if(a!= B) {Z PROC1 ; ; 4 if 2 if (A = = B) { CP B ; AB JP NZ, PROC2 ; if(a = = B) {Z 0 PROC2 ; } else { JP ENDIF ; } PROC2: ; else { ; } ENDIF: ; } 26
28 5 D1 D3 D1,D D100 L1 DD1 Y D0 N 2 XX(8100H )100 YY(8200H ) start HLXX() BCYY() D100 XX(8100H) 8101H L1 8163H Y A (HL) (BC) A HLHL+1 BCBC+1 DD1 D0 N STOP YY(8200H) 8201H 8263H 27
29 for 2 1 C for (; ; ) { } No Yes 2 for F: ENDF: JP F H 28
30 while 1 while () { No } Yes 2 while W: ENDW JP W 5.9. DATA(8200H) POS(8100H) NEG(8101H)80H 29
31 DATA(8200H) POS(8100H) NEG(8101H)80H start BC0 BC HLDATA POS(8100H) NEG(8101H) 3 2 W A (HL) A 80H Z1 N HLHL+1 Y DATA(8200H) (POS)B (NEG)C STOP 03H 0FEH 0FFH 23H 34H 80H N A A AND A A < 0 Y B ++ C ++ return 30
32 5.10. bit 1 bit bit bit AND x 1 = x x 0 = 0 2 bit bit bit bit x + 1 = 1 x + 0 = x OR 3 bit bit AND 4 bit bit x 0 = 0 x 1 = x EX-OR x 0 = x x 1 = x a b a b H 4bit 8101H 4bit
33 RLCA CY A CY RLCA 2 RRCA CY A CY RRCA 3 RLA CY A 4 RRA CY A H AP 8101H AQ 8102H, 8103H AR,AR+1 32
34 (AP )(AQ ) (AR )(AR+1 ) 8 bit 8 bit 16 bit (7) DE (AP ) (11) A (AQ ) HL 0, HL HL + DE DE 1bit, HL HL + DE DE 1bit DE 1bit, HL HL + DE (AR )(AR+1 ) HL (1) start D 0 E (AP ) A (AQ ) HL 0 CY 0 A0? Y LOOP (AR )(AR+1 ) HL N (2) CYA CY1? Y HL HL + DE (3) A LSB CY SKIP DE 1bit (4) N DE 1bit HL DE HL HL+HL HL DE return stop CY A DE HL 33
35 5.12. (a) CALL 800BH 8000H 800BH PCPC+3 (a) (SP1),(SP2)PC 8007H SPSP2 800AH PC800BH (b) (b) RET PC(SP+1),(SP) SPSP+2 834EH 834FH 0AH 80H 8350H SP 8350H 8350H SP 834EH 2 34
36 8350H 834CH 834DH 834EH 834FH 8350H (F) (A) 0DH 80H SP 8350H SP 834CH 834EH 834FH 8350H 834AH 834BH 834CH 834DH 834EH 834FH 8350H 0DH 80H (E) (D) (F) (A) 0DH 80H SP 834EH SP 834AH 35
37 6. 1 CPU8085A 64k 8bit CPU 8085A 8 A8-A15 ALE AD0-AD7 RD WR IO / M 2 CPU8085A (I/O) CPU 8085A A8-A15 ALE AD0-AD7 RD WR IO / M k8bit A8-A15 A0-A7 D0-D7 A M A RDIO WRIO 2 WE IC 8255A (1) CS A0-1 D0-7 RD WR A B C CWR CS IC 8255A (2) CS A0-1 D0-7 RD WR A B C CWR I/O SW LED I/O DA1 DA2 36
38 3 CPU 8255A A0 A0 A1 A1 74LS139 A2 Y0 8255A(1)CS A3 Y1 8255A(2)CS Y2 Y3 CS A4 1 A5 1 A6 1 A4 A5 A6 A4 A5 A6 A7 A7 1 A7 8255A A (1) B C 8255A (2) CWR A B C CWR 4 IC 8255A 8 IC 8255A A0 A1 CWR A B C 8255A(1) SW LED 8255A(2) DA DA CWR 8255A CWR 37
39 CWR MSB LSB 0 A C B C 8255A(1)CWR 90H8255A(2)CWR ORG 8000H LD A, 90H ; A90H OUT (0F3H), A ; 8255A(1) CWR 90H LD A, 80H ; A80H OUT (0F7H), A ; 8255A(2) CWR 80H LD A, B OUT (0F1H), A ; (LED)A HALT ; A LED wait 38
40 SW LED ORG 8000H CALL INIT ; LOOP: IN A,(SW) ; A <-- (SW) XOR 0FFH ; A bit AND 0FH ; A 4bit OUT (LED),A ; (LED) <-- A JP LOOP ; LOOP INIT: LD A,90H OUT (CWR1),A LD A,80H OUT (CWR2),A RET SW: EQU 0F0H LED: EQU 0F1H CWR1: EQU 0F3H CWR2: EQU 0F7H END SW 4bit LED sw0 LED sw1 LED 2 LED 8255A(1)A 4bit bit ORG 8000H CALL INIT ; LD C,0 ; C <-- 0 LOOP: IN A,(SW) ; A <-- (SW) XOR 0FFH ; A bit AND 0FH ; A 4bit JP Z,LOOP ; LOOP ADD A,C ; A <-- A + C LD C,A ; C <-- A OUT (LED),A ; (LED) <-- A CALL SWOFF ; SW JP LOOP ; LOOP SWOFF: ; SW CALL DELAY ; IN A,(SW) ; A <-- (SW) XOR 0FFH ; A bit AND 0FH ; A 4bit JP NZ,SWOFF ; SWOFF RET 39
41 INIT: LD A,90H OUT (CWR1),A LD A,80H OUT (CWR2),A RET start 8255A INIT DELAY: PUSH AF PUSH DE LD DE,0681H DELAY1: DEC DE LD A,D OR E JP NZ,DELAY1 POP DE POP AF RET SW: EQU 0F0H LED: EQU 0F1H CWR1: EQU 0F3H CWR2: EQU 0F7H END 8255A INIT (CWR1)90H (CWR2)80H return (C)0 LED LOOP (A) (SW) (A) bit 4bit (A)0? N (A)(A)+(C) (C)(A) (LED)(A) Y SW SWOFF SW SWOFF DELAY (A) (SW) (A) bit 4bit N (A)0? Y return 40
42 ; ; ; ; A(1) C MSB ; 0,1 ; -- 0,1 ; -- 0,1 ; 8255A(1) C MSB bit -- CWR ; ORG 8000H CALL INIT ; L0: LD B,9FH ; B <-- 9FH CALL SOUND ; JP L0 ; 8255A(1),(2) INIT: LD A,90H OUT (CWR1),A LD A,80H OUT (CWR2),A RET ; SOUND: CALL SPK_ON ; CALL SPK_OFF ; 0 DEC B ; B 1 RET Z ; B RETURN JP SOUND ; 1 SPK_ON: LD A,0FH OUT (CWR1),A CALL DELAY RET ; 0 SPK_OFF: LD A,0EH OUT (CWR1),A CALL DELAY RET ; 8255A(1)CWR 0FH ; C MSB ; B ; 8255A(1)CWR 0EH ; C MSB ; B ; B DELAY: LD A,B DD: DEC A JP NZ,DD RET CWR1: EQU 0F3H CWR2: EQU 0F7H END 41
43 7. AD DA ms = 1 H (a)1khz (b)~(e) f (t) (0Hz), 1kHz 3kHz sin t (a) (b) 2 1 0Hz (0Hz), 1kHz,3kHz,5kHz sin (c) 1kHz sin sin(2 πf 0 t ) 2 1 (e) 5kHz sin sin(2 5 ) 5 f 0 π π t 2 1 (d) 3kHz sin sin(2 3 ) 3 f 0 π π t π [khz] (0Hz), 1kHz, 3kHz,5kHz (e) 5kHz sin sin(2 5 ) 5 f 0 π π t [khz]
44 7.2. F [Hz] F [Hz] 1 [sec]2 F [Hz] 2F t (LPF) AD DA (LPF) () t 50,75,115,125,135, t 1 [sec] 2F t 8bit DA 4 bit (4 bit ) t 10 D3 D2 D1 D0 [V] () 0.05[V] 43
45 R2R DA R R R Vout 2R D3 E 2R D2 E 2R D1 E 2R D0 E 2R E 3 2 Vout (2 D3 + 2 D2 + 2 D1 + D0 ) 4 2 Z80 IO 0F4H 8255A(2) A 8bitDA 8bitDA 8bitDA 0H 0 [V], 0FFH 5 [V] 5 [v] 0 [v] IC 8255A (2) A B C CWR IO 0F4H IO 0F6H I/O DA1 DA2 (X ch) (Y ch) Y ch (150,250) (50,50) (250,50) X ch Z X Y AD 1 AD t t 44
46 2 AD () ( ) AD () ( ) C1 C0 1 [sec] 2F t 3 50,75,115,125,135, 8bit 256 Vi S ON R C Vo S S=1 ON Vi R C Vo t V = RC o V i 1 e Vo Vi t S=0 OFF C Ri Vo V o = V i e (OP ) t RiC Vo Vi t S t 45
47 4 (a) (b) 72g 80g 80g 40g 10 D3 D2 D1 D0 [V] (a) 0.8[V] D3 0.72[V] 40g (b) 0.4[V] D2 (c) 40g 20g (c) 0.6[V] D1 60g (d) 0.7[V] D0 (d) 40g 20g 10g (0.72[V]) 4 bit 70g 46
48 4bit AD Vi=0.72[V] (a) Q1 Q2 Q3 Q4 Q5 (Q1) FF3 Set DA DA d0.8[v] id c id c i AD c Q D CLK D d Q 3 DA Q 2 Q 1 A3 A2 A1 A0 Q1 Q2 Q3 Q4 Q5 Q 0 (b) (D3=0) Q1 Q2 Q3 Q4 Q5 (Q2) Q2, c A3 FF3 Reset FF3 Q2 FF2 Set FF2 DA DA d0.4[v] id c (c) (D2=1) Q1 Q2 Q3 Q4 Q5 (Q3) Q3, c A3 FF2 Reset FF2 Q3 FF1 Set FF1 DA 1 DA d0.6[v] id c (d) (D1=1) Q1 Q2 Q3 Q4 Q5 (Q4) Q4, c A3 FF1 Reset FF1 Q4 FF0 Set FF0 DA 1 DA d0.7[v] id c (e) (D0=1) AD 47
49 5 IO AD () 1k k A0 AD LSI DATA AD (1 bit ) A(1) AMSB(A7) (IO 0F0H) CLK C 3bit (C3) (IO 0F2H) A1 CS C 2bit (C2) (IO 0F2H) CS C0,C1 CLK AD DATA A2 A3 C1 C0 A0A3 AD C 2bit (C2) (IO 0F2H) A0A3 AD C, C1, C0) C 1bit (C1) C 0bit (C0) (IO 0F2H) (IO 0F2H) C 2bit (C2) (IO 0F2H) MSB 2SB 3SB 4SB 5SB 6SB 7SB LSB AMSB(A7) (IO 0F0H) 9 8bit MSB 6 AD 48
50 A C1 C0 C C1 C0 A A 0 0 C1 C0 0 1 C1 C0 0 0 C1 C0 C 1/0 3bit 1 CWR bit CWR A AD SW SW SW SW CY AD SW SW SW SW CY AD B7 B6 B5 B4 B3 B2 B1 B0 CY B7 B6 B5 B4 B3 B2 B1 B0 AD B B B7 B6 B5 B6 B5 B4 B5 B4 B3 B4 B3 B2 B3 B2 B1 B2 B1 B0 B1 B0 MSB B0 MSB 2SB MSB 49 2SB 3SB 4SB 5SB 6SB 7SB LSB
51 CPU CPU IN A, (0F0H) Yes CPU No 8085A RST7.5 CPU RST7.5 CALL 3CH 2 3 CPU 8085A 5 RST5.5 CALL 2CH RST6.5 CALL 34H RST7.5 CALL 3CH TRAP CALL 24H INTR INTR INTR (High) INTA () RST 1, RST2, RST3, RST4, RST 5, RST 6, RST7 50
52 RST7.5 CPU RST7.5 1 RST 7.5FF D Q CLK Reset CALL 3CH SIM SIM FF RST7.5 RST7.5 EI S R DI FF LD A,1BH DB 30H A ; SIM RST7.5 FF 1 RST 7.5FF Reset RST 5.5FF RST 6.5FF RST 7.5FF CPU RST7.5 R O M 3CH 3DH 3EH 04BDH 04BEH 04BFH 8000H 8200H FF1EH FF1FH FF20H C3 BD 04 C3 1E FF RET C CALL 3CH C3 BD 04 JP 04BDH C3 1E FF JP FF1EH C JP 8200H 51
53 4 RST7.5 RST7.5 52
54 53
55 8. 1 () 2 ADD A,B ; H () A A + B ADD B 000 C 001 D ADD B C B B + C LD B, C H LD,
56 4 D B + C 5 pop pop ADD 30 push LD A, (1234H) CPU 2 [3] p LD A, (HL) bit XX 100 YY p (2) () 55
57 3 [3] p bit 4 PC PC b+a a p+a b b+a CPU + PC + a a p a PC p+a + PC + 3 bit 5 a + bit + 2 a[2] b+a+i b i CPU + + a b+a+i 56
58 6 big endian little endian (windows PC ) 1234H H () 60112H () (Mac, Sun ) 1234H H () 60134H () 8.3. CPU 1 2 W W 3 W W W W W
59 CPU CPU (SRAM ) (DRAM ) [3] p ns 200 ns ns200 ns19.5 ns 200 ns 10 () bit direct mapping fully associative mapping set associative mapping 58
60 ([3] p.113~p.114) 1 byte 1 = 64 byte = 64 k byte = 2 16 byte = 10 G byte = 2 32 byte = byte = = 0 ~1023 direct mapping ([3] p.114) (,Tag) M M M O M (,Index) (,Index) 2 10 (,Tag) () (16bit) (10bit) (6bit) 1 hit (,16bit)
61 fully associative mapping ([3] p.113) (26bit) (26bit) 26bit1024 M M 1023 () 2 26 ( 2 26 ) M (26bit) CPU () 1024 hit () (,26bit) (6bit) set associative mapping = ( 4 2 ) M M O M (20bit) M M O M 1 63(,) M M O M hit () 26 (2 ) 6 (2 ) () = (6bit) ( 20bit) 0 ( 6bit)
62 128K 4G 32 set associative mapping IndexTag [3]p n first-in first-out usage bit 1bit usage bit 1 usage bit 0 usage bit usage bit CISC 1 CISC (Complex Instruction Set Computer, ) CPU 2 RISC (Reduced Instruction Set Computer, ) CPU 3 RISC CISC CISC RISC CISC RISC RISC CISC RISC RISC+CISC CISC 61 CISC
63 PC() IR () ON (2bit) 2 (2bit) (1bit)
64 1 R0 R1 Rn PC IR 10 MDR 3 8 MAR PCMARIR IR CPU F D E WB 63
65 3 RISC firmware; CISC 4 (state machine) IR D D D D E D WB 5 IR 20~100bit 64
66 IR (state) 65
67 66
68 67
69 68 1
1 8 Z80 Z GBA ASIC 2 WINDOWS C 1
1 8 Z80 Z80 20 8080 GBA ASIC 2 WINDOWS C 1 2.1 Z-80 A 0 - A 15 CPU Z80 D 0- D 7 I/O Z80 1: 1 (1) CPU CPU Z80 CPU Z80 AND,OR,NOT, (2) CPU (3) I/O () Z80 (4) 2 Z80 I/O 16 16 A 0, A 1,, A 15 (5) Z80I/O 8
取扱説明書 -詳細版- 液晶プロジェクター CP-AW3019WNJ
B A C D E F K I M L J H G N O Q P Y CB/PB CR/PR COMPONENT VIDEO OUT RS-232C LAN RS-232C LAN LAN BE EF 03 06 00 2A D3 01 00 00 60 00 00 BE EF 03 06 00 BA D2 01 00 00 60 01 00 BE EF 03 06 00 19 D3 02 00
HITACHI 液晶プロジェクター CP-AX3505J/CP-AW3005J 取扱説明書 -詳細版- 【技術情報編】
B A C E D 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 H G I F J M N L K Y CB/PB CR/PR COMPONENT VIDEO OUT RS-232C LAN RS-232C LAN LAN BE EF 03 06 00 2A D3 01 00 00 60 00 00 BE EF 03 06 00 BA D2 01
ディジタルシステム設計
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