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1 Verilog HDL Verilog HDL VerilogHDL veriloghdl / CPLD

2 , 1bit 2 MUX 5 D,E) always) module MUX(out, a, b, sel); output out; input a, b, sel; A) IF module MUX(out, a, b, sel); output out; input a, b, sel; wire out, a, b, sel; assign out = sel? a : b; B) module MUX(out, a, b, sel); output out; input a, b, sel; wire out, a, b, sel; assign out = (a & sel ) (b & sel) C) AND,OR,NOT module MUX(out, a, b, sel); output out; input a, b, sel; wire out, a, b, sel; wire a1, bl, sel_ ; not i1(sel_, sel); and i2(a1, a, sel); and i3(b1, b, sel_); or i4(out, a1, b1); reg out; wire a, b, sel; a or b or sel ) if(sel = = 1 b1) out = a; else if ( sel = = 1 b0 ) out = b; else out = 1 bx; module MUX(out, a, b, sel); output out; input a, b, sel; reg out; wire a, b, sel; a or b or sel ) case( sel ) 1 b1: out = a; 1 b0: out = b; default: out = 1 bx;

3 module half_adder ( s, co, a, b ); input a, b; output s, co; OR module full_adder ( s, co, a, b, ci ); input a, b, ci; output s, co; wire w0, w1, w2; assign w0 = a & b, w1 = w0, w2 = a b, s = w1 & w2, co = w0; wire w0, w1, w2; assign co = w1 w2; half_adder i0 (.co(w1),.s(w0),.a(a),.b(b)); half_adder i1 (.co(w2),.s(s),.a(w0),.b(ci)); w2 half_adder i0 w1 half_adder i1 assign c0=w1 w2; OR

4 4 module adder4 ( s, co, a, b, ci ); input [3:0] a, b; input ci; output [3:0] s; output co; 4 module adder4 ( s, co, a, b, ci ); input [3:0] a, b; input ci; output [3:0] s; output co; wire w0, w1, w2; full_adder i0 (.co(w0),.s( s[0]),.a(a[0]),. b(b[0]),.ci(ci) ); full_adder i1 (.co(w1),.s( s[1]),.a(a[1]),. b(b[1]),.ci(w0) ); full_adder i2 (.co(w2),.s( s[2]),.a(a[2]),. b(b[2]),.ci(w1) ); full_adder i3 (.co(co),.s( s[3]),.a(a[3]),. b(b[3]),.ci(w2) ); a or b or ci ) begin { co, s } = a + b + ci;

5 Verilog HDL reg: always <=, =) always wire: assign assign a = b; c = a; c <= a <= b; c <= a; c a x, o, 1, z supply, strong, pull, large, weak, medium, small, highz parameter: timescale / timescale 1 ns / 1ns assign #10 x = a & b; 10

6 AND, NAND, OP, NOR, not n1( out_not, in0); and an2( out_and2, in0, in1); or or2( out_or2, in0, in1); nor nr2( out_nor2, in0, in1); xor xr2( out_xor2, in0, in1); and an3( out_and3, in0, in1, in2); xnor xn3( out_xor3, in0, in1, in2);

7 assign out_not = ~in0; assign out_and2 = in0 & in1; assign out_or2 = in0 in1; assign out_nand2 = ~( in0 & in1); assign out4 = ~in1& ( in1 in2); assign out_xnor3 = ~( in0 ^ in1 ^ in2); assign and_or_not = ~( ( in0 & in1 ) ( in2 & in3) ); assign

8 module mux( out, a, b, sel); input [ 7 : 0 ] a, b; input sel; output [ 7 : 0 ] out; [MSB : LSB]

9 initial : always: initial begin a = 1 b0; 0 #10 a = 1 b1; 10 1 #20 a = 1 b0; #30 a = 1 b1; D FF module dff (d, clk, rst, q, xq); input d, clk, rst; output q, xq; module MUX(out, a, b, sel); output out; input a, b, sel; reg out; wire a, b, sel; a or b or sel ) if(sel = = 1 b1) out = a; else if ( sel = = 1 b0 ) out = b; else out = 1 bx; always always clk rst posedge clk or negedge rst) begin if ( rst = = 1 b0 ) begin q <= 1 b0; xq <= 1 b1; else begin q <= d; xq <= d ;

10 : assign assign assign out = sel? a : b; if assign out = ( a & sel ) ( b & sel); always moduke dff ( q, qb, d, clk ); output q, qb; input d, clk; reg q, qb; pesedge clk ) begin # 5 q = d; #1 qb = d; q, qb d,~d reg a, b; posedge clk) begin a <= b; b <= a; a b a=b; b=a; a b b

11 A) `resetall `timescale 1ns/10ps module Blocking1(a, b, d, ck); input d, ck; output b, a; B) `resetall `timescale 1ns/10ps module Blocking1(a, b, d, ck); input d, ck; output b, a; reg b, a; posedge ck) begin b = d; a = b; reg b, a; posedge ck) begin b <= d; a <= b; a b

12 FF wire a, b, sel; reg out; module MUX(out, a, b, sel); output out; input a, b, sel; reg out; wire a, b, sel; a or b or sel ) if(sel = = 1 b1) out = a; else if ( sel = = 1 b0 ) out = b; else out = 1 bx; out FF reg always FF sel )

13 module example1 (... );... MUX m1 ( out1, in1, in2, select );... module example2 (... );... MUX m2 (.out(out1),.b(in2),.a(in1),.sel(select) );... MUX Mmodule MUX( out, a, b, sel);

14 1 2 module adder4sim(); reg [ 3 : 0 ] in1, in2; wire [ 3 : 0 ] rslt; wire cy; adder4 add4 ( in1, in2, rslt, cy );. module adder4sim(); reg [ 3 : 0 ] in1, in2; wire [ 3 : 0 ] rslt; wire cy; adder4 add4 (.out_data1(rslt),.cy(cy),.in_data1( in1 ),. in_data2( in2) );. module adder4 ( in_data1, in_data2, out_data, cy); input [ 3 : 0 ] in_data1, in_data2; output [ 3 : 0 ] out_data; output cy;.. module adder4 ( in_data1, in_data2, out_data, cy); input [ 3 : 0 ] in_data1, in_data2; output [ 3 : 0 ] out_data; output cy;..

15 always timescale 1 ns / 1 ns module mux ( x, a, b, s ); input a, b, s; output x; reg w1, x; reg tmp; a or b or s ) begin if ( s = = 1 b1 ) tmp = a; else tmp = b; w1 <= tmp; always FF begin x <= w1;

16 always FF) module dff (d, clk, rst, q, xq); input d, clk, rst; output q, xq; reg q, xq; posedge clk or negedge rst) begin if ( rst = = 1 b0 ) begin q <= 1 b0; xq <= 1 b1; else begin q <= d; xq <= d ; A) FF q xq B) FF) module dff (d, clk, rst, q, xq); input d, clk, rst; output q, xq; reg q; posedge clk or negedge rst) begin if ( rst = = 1 b0 ) begin q <= 1 b0; else begin q <= d; assign xq = ~q; <= always q xq assign q

17 always `resetall `timescale 1ns/10ps module mux1( x, a, s); input a, s; output x; always FF `resetall `timescale 1ns/10ps module mux1( x, a, s); input a, s; output x; reg tmp; a or s) begin if( s == 1'b1 ) tmp <= a; assign x = ~tmp; s reg tmp; a or s) begin if( s == 1'b1 ) tmp <= a; else tmp <= 1'b0; assign x = ~tmp;

18 if.. else.. if ( cond1 = = 1 b1) x <= a; else if ( cond2 = = 1 b1 ) x <= b; else x <= c; case case ( sel ) 2 b00: x <= a; 2 b01: x <= b; 2 b10: x <= c; 2 b11: x <= d; default: x <= 1 bx; case C case for for ( i = 0; i<= 7; i = i + 1 ) x[i] <= y[7 i ]; x[0] <= y[7 ]; x[1] <= y[6 ]; x[2] <= y[5 ]; x[3] <= y[4 ]; x[4] <= y[3 ]; x[5] <= y[2 ]; x[6] <= y[1 ]; x[7] <= y[0 ]; while i = 1; while (i <= 7 ) begin x[ i ] <= y[ 7- i ]; i = i + 1; for i i=i+1 i integer

19 for `resetall `timescale 1ns/10ps module Latch8( y, x, ck, set); input [7:0] y; output [7:0] x; input ck, set; integer i; reg [7:0] x; posedge ck ) begin if ( set) begin for ( i=0; i<=7; i=i+1) x[i] <= y[7-i]; for while i for

20 forever i = 0; forever begin: forever_block x[ i ] <= y[ 7 i]; i = i + 1; if ( i = = 8 ) disable forever_block; $stop; $finish; #100; 100 wait ( c = = 1 b1 a or b or c ); a, b, c

21 function [ 7 : 0 ] sign_ext; input [ 3 : 0 ] a; if ( a[ 3 ] ) sing_ext = {4 b1111, a }; else sing_ext = {4 b0000, a }; function C input x <= sign_ext( a ); sign_ext x task sign_ext; input [ 3 : 0 ] a; output [ 7 : 0 ] x; if ( a[ 3 ] ) x= {4 b1111, a }; else x= {4 b0000, a }; task sign_ext( a, x ); x

22 module register( wr, we, data_in, data_out); parameter DATA_WIDTH = 8; input wr, we; input [DATA_WIDTH 1 : 0 ] data_in; output [DATA_WIDTH 1 : 0 ] data_out; reg [DATA_WIDTH 1 : 0 ] data_out; posedge wr ) begin if ( we ) begin data_out <= data_in; module paramtop( regsel, wr, we, data_in, data_out); input [ 2 : 0 ] regsel; input wr, we; input [ 31 : 0] data_in; output [ 31 : 0 ] data_out; wire [ 7 : 0 ] reg8out; wire [ 15 : 0 ] reg16out; wire [ 31 : 0 ] reg32out; assign data_out = ( regsel = = 1 )? { 24 h000000, reg8out} : 32 hzzzzzzzz; assign data_out = ( regsel = = 2 )? { 16 h0000, reg16out} : 32 hzzzzzzzz; assign data_out = ( regsel = = 4 )? { reg8out} : 32 hzzzzzzzz; register #( 8) reg8 ( wr, we, data_in[ 7 : 0 ], reg8out); register #( 16) reg16 ( wr, we, data_in[ 15 : 0 ], reg16out); register #( 32) reg32 ( wr, we, data_in[ 31 : 0 ], reg32out);

23 module add_const( a, q); input [3:0] a; output [3:0] q; parameter [3:0] const = 5; assign q = a + const;

24 tmescale 1 ns / i ns module dec ( a, x ); input [2:0] a; output [ 7 : 0 ] x; reg [ 7 : 0 ] x; begin case (a) 3 b000 : x <= 8 b ; 3 b001 : x <= 8 b ; 3 b010 : x <= 8 b ; 3 b011 : x <= 8 b ; 3 b100 : x <= 8 b ; 3 b101 : x <= 8 b ; 3 b110 : x <= 8 b ; 3 b111 : x <= 8 b ; default : x <= 8 bxxxxxxxx; case default FF

25 tmescale 1 ns / i ns module dec ( a, x ); input [2:0] a; output [ 7 : 0 ] x; reg [ 7 : 0 ] x; case begin case (a) 3 b000 : x <= 8 b ; 3 b001 : x <= 8 b ; 3 b010 : x <= 8 b ; 3 b011 : x <= 8 b ; 3 b100 : x <= 8 b ; 3 b101 : x <= 8 b ; 3 b110 : x <= 8 b ; // 3 b111 : x <= 8 b ; // default : x <= 8 bxxxxxxxx; case

timescale 1 ns / 1ns module enc ( a, x ); input [ 7: 0 ] a; output [ 3: 0 ] x; reg [ 3: 0 ] x; always @(a) begin casex (a) 8 b???????1: x <= 4 b1000; 8 b??????10: x <= 4 b1001; 8 b?

26 timescale 1 ns / 1ns module enc ( a, x ); input [ 7: 0 ] a; output [ 3: 0 ] x; reg [ 3: 0 ] x; begin casex (a) 8 b???????1: x <= 4 b1000; 8 b??????10: x <= 4 b1001; 8 b?????100: x <= 4 b1010; 8 b????1000: x <= 4 b1011; 8 b???10000: x <= 4 b1100; 8 b??100000: x <= 4 b1101; 8 b? : x <= 4 b1110; 8 b : x <= 4 b1111; defalut : x <= 4b 0000; case casex case?

27 timescale 1 ns / 1 ns module mux ( a, b, s, x ); input [ 7 : 0 ] a, b; input s; output [ 7 : 0 ] x; reg [ 7 : 0 ] x; a or b or s ) begin if ( s = = 1 b1) x <= a; else x<= b; always if

28 3in 8bit `resetall `timescale 1ns/10ps module mux8(a, b, c, s, x); input [7:0] a, b, c; input [1:0] s; output x; reg [7:0] x; or b or c or s) begin case (s) 2'b00: x <= a; 2'b01: x <= b; 2'b10: x <= c; default: x<= 8'hff; case always case

29 timescale 1 ns / 1 ns module comp ( a, b, gt, lt, eq ); input [ 7: 0 ] a, b; output gt, lt, eq; reg gt, lt, eq; a or b ) begin if( a > b ) begin gt <= 1 b1; lt <= 1 b0; eq <= 1 b0; else if ( a < b) begin gt <= 1 b0; lt <= 1 b1; eq <= 1 b0; else begin gt <= 1 b0; lt <= 1 b0; eq <= 1 b1;

30 8 timescale 1 ns / 1 ns module add ( a, b, ci, co, x ); input [7 : 0] a, b; input ci; output [ 7: 0 ] x; output co; reg [ 7 : 0 ] x; reg co; a or b or ci ) { co, x } <= a + b + ci; ; {co, x} 1 a,b,ci

31 ALU timescale 1 ns / 1 ns accum or data or opcode) begin define AND 3 b000 case ( opcode ) define OR 3 b001 AND : alu_out <= accum & data; define NOT 3 b010 OR : alu_out <= accum data; define XOR 3 b011 NOT : alu_out <= accum; define ADD 3 b100 XOR : alu_out <= accum ^ data; define SUB 3 b101 ADD : alu_out <= accum + data; define ACC 3 b110 SUB : alu_out <= accum - data; define DAT 3 b111 ACC : alu_out <= accum; DAT : alu_out <= data; module alu ( alu_out, accum, data, opcode); default : alu_out <= 8b xxxxxxxx; input [ 7 : 0 ] accum, data; case input [ 2 : 0 ] opcode; output [ 7 : 0 ] alu_out: reg [ 7 : 0 ] alu_out: accum data (`define) case opcode ALU alu_out

32 ALU

33 timescale 1 ns / 1ns module sync_reg8 ( d, clk, rst, q ); input [ 7 : 0 ] d; input clk, rst; output [ 7 : 0 ] q; reg [ 7 : 0 ] q; posedge clk ) begin if ( rst = = 1 b0) begin q <= 8 b ; else begin q <= d; posedge

34 timescale 1 ns / 1ns module async_reg8 ( d, clk, rst, q ); input [ 7 : 0 ] d; input clk, rst; output [ 7 : 0 ] q; reg [ 7 : 0 ] q; posedge clk or negedge rst ) begin if ( rst = = 1 b0) begin q <= 8 b ; else begin q <= d; always negedge

35 8 timescale 1 ns / 1ns module count8_ld ( d, ci, clk, rst, ld, co, q ); input [ 7 : 0 ] d; input ci, clk, rst, ld; output co; output [ 7 : 0 ] q; reg [ 7 : 0 ] q; posedge clk ) begin if ( rst = = 1 b0) begin q <= 8 b ; else if ( ld = = 1 b1 ) begin q <= d; else begin q <= q+ ci; assign co =&{ q, ci}; &{q,ci};

36 KHz

37 7 LED 16 BCD-7 a a,b,c,d,e,f b,c,f,g a,b,c,d,e,f,g f e g b c d b,c a,c,d,f,g a,b,c,d,f,g 2 a,b,d,e,g a,b,c,d,g a,c,d,e,f a,b,c

38 6 4 / 6 clk 6 2 veriloghdl CPLD 2 start stop reset 2 set( 0 5 FF

2.5. Verilog 19 Z= X + Y - Z A+B LD ADD SUB ST (X<<1)+(Y<<1) X 1 2 LD SL ST 2 10

2.5. Verilog 19 Z= X + Y - Z A+B LD 0 0001 0000 ADD 1 0110 0001 SUB 2 0111 0010 ST 2 1000 0010 (X