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1 99/10/7 ie.u-ryukyu.ac..ac.jp bw-

2 PC MPEG2 3 /

3 [1] PC LSI PC LSI LSI

4 PentiumPC Video L2 Cache Frame Memory Graphic Controller LAN Modem Core Chip Set Pentium HOST BUS 66MHz -> > 100MHz Main Memory PCI 33MHz -> > AGP 66MHz ISA Bridge HOST BUS MPU

5 PentiumII PC Video Frame Memory Graphic Controller AGP 66+MHz LAN Modem PCI 33MHz MHz L2 Pentium II Cache Core Chip Set 100MHz -> > 133MHz USB Main Memory 100MHz(SD) -> 800MHz(RD) L2 BUS MPU

6 PC MPU+L2 Video Core Chip Set Graphic Controller Rambus Memory Main + Frame PCI 33MHz USB IEEE1364 LAN Modem BUS

7 Direct RAMBUS 400MHz clock 18bit bit Byte x 800MHz = 1.6GB/s 100MHz SDRAM, 64bit 800MB/s MB/s Latency Controller RDRAM RDRAM Vtt RAC Data Cntl, Addr Vref 2 2 ClkFM ClkTM

8 PentiumII PentiumII PC PC ISA ISA DIMM DIMM Slot1 Slot1 PentiumII PentiumII PCI PCI AGP AGP PC PC LSI LSI

9 PC LSI USB, IEEE1394 Rambus DRAM

10 PentiumII PC LSI MPU (1) Cache SRAM (2) (1-3) INTEL / VIA DRAM (4-8) Samsung / Micron.. BIOS (1) AMI / Phenix I/O (1)??? CNTL(1) Matrox / ATI / S3 (2) Micron / NEC.. LAN/MODEM (1) 3Com etc. SOUND (1) INTEL / AMD NEC / Toshiba... Creative etc. Maxim etc. Intel

11 [2] MPEG2 DVD PC JPEG VHS MPEG H.26x DV

12 MPEG2

13 MPEG Red,Green,Blue MPEG Video Y(luminance),Cb Cb,Cr(color- difference) Y = 0.299R G B Cb= R G B Cr= 0.500R G B color Cb,Cr,CrY

14 Motion Estimation Motion Vector Motion Vector Error Motion Vector

15 Motion Estimation N-1 N-1 MAD(x,y) = Σ Σ S(m+x,n+y) S(m+x,n+y)-B(m,n) B(m,n) -p p <= x, y <= p m=0 n=0 (2p+1)x(2p+1) Search Window in previous picture Input NxN Block H/W

16 Transform Cording Discrete Cosine Transform DCT

17 DCT DC

18 DCT Scalar Quantization

19 1D-DCT 7 y(u)= 0.5 C(u) Σ {x(n){ cos[(2n+1)u [(2n+1)uπ/16]} n=0 cos ROM ROM Distributed Arithmetic

20 MPEG LSI DCT ROM MPU H/W KEY H/W

21 [3] Nintendo64 PlayStation PC TV

22 PC Frame Memory MHz L2 Pentium II Cache Video 3D D Graphics Core Rendering Chip Controller Set PCI 33MHz, PCI AGP 66+MHz /AGP Main Memory

23 Nintendo Nintendo 64 64bit bit MIPS MIPS MPU MPU Rendering Rendering Controller Controller RDRAM RDRAM RDRAM RDRAM 9bit, 500MHz bit, 500MHz Cassette Cassette ROM ROM Video Video D RambusDRAM RambusDRAM TV TV PC PC B/W B/W

24 D Depth (R,G,B) R,G,B) A(

25 OpenGL Machine( Lighting Vertex( Normal( Color( TexCord n Model / View Matrix TexGen ( n n Lighting Matrix Coloring ( Primitive Assembly Clipping Projection Matrix Rasterization

26 Vx,Vy Vy,Xz,Vw (Nx,Ny,Nz) SIMD (R,G,B,A) R,G,B,A) SIMD MPU MMX Pentium in PC, 64bit RISC in Nintendo64.

27 128bit MPU for PlayStation2?? ISSCC99, TP15.1, SCE & Toshiba 2way 64bit superscalar MPU 10 IEEE single precision FMAC 4 IEEE single FDIV MPEG support-- --VLD, DCT/IDCT, IQ, CSC, VQ

28 OpenGL Machine Rasterization (X,Y,Z) (Rf,Gf,Bf,Af) (Xt,Yt) Texel Generation Texture Memory (Rt,Gt,Bt,At) Texture Application Frame Buffer Test Depth Depth-Test Z-buffer (X,Y) (R,G,B,A) Blending Z-buffer Memory Pixel Memory

29 Rf,Gf Gf,Bf,,Bf,Af

30 (Rk,Gk,Bk) Uf Vf (Ri,Gi,Bi) (Rl,Gl,Bl) (Rj,Gj,Bj) RGB) (1 Rt = Rl Rt = (1-Vf){ Vf){Uf Rj + (1-Uf) Uf)Ri} } + Vf {Uf Rl + (1-Uf) Uf)Rk}

31 Depth Test TRUE FALSE Depth Test ) Z-buffer Zdest Zsource ZsourceZdest Zsource < Zdest Zdest Pixel Z-buffer Read Modify Write Z-buffer 32bit bit RGBA Z-bufferPixel I/O BW

32 SOURCE DESTINATION SOURCE DESTINATION 1) (RGBA) RGBA) 2) Rrst = As Rsrc + (1-As) Rdest Pixel Read Modify Write DRAM BW

33 PC 1000x1000x64bit= x1000x64bit=8mb Pixel Z-buffer Frame Memory MHz L2 Pentium II Cache Video 3D D Graphics Rendering Controller Core Chip Set PCI 33MHz, PCI AGP 66+MHz /AGP Main Memory MB

34 D LSI LSI Floating Floating SIMD SIMD BW BW PCI PCI AGP AGP

35 [4] PHS IMT CDMA

36 IC IC TDMA TDMA CDMA CDMA V V V / V / V V V V LSI LSI G/A G/A LSI LSI LSI LSI FDMA FDMA

37 LSI CDMA MPEG4 MPEG4 CODEC Rake Interleave, Convolution Code, Viterbi Decode USB(Universal Serial Bus) BlueTooth

38 CDMA( ) FDMA, TDMA Pseudo-Noise Random Sequence (Direct-Sequence Spread-Spectrum) Spectrum) Power Time User 3 User 2 User 1 frequency

39 Random Waveform x(t) Autocorrelation Rxx(τ)=E{x(t) x(t+τ)} x(t) x(t+τ)dt Rxx(τ) 0 Tc

40 Linear Feedback Shift Register f(x) = 1 + a1xa 1 +a2x a a 11X 11 + a12x X 13 Reg a12 a11 a1 Reg Reg Reg PN output a1 a2 a12 Reg Reg Reg Reg PN output

41 FEC)

42 non-interleaved interleaved read Interleaver write read Deinterleaver de-interleaved write

43 W-CDMA CDMA BB BB I Q A/D & Fil Chip (Finger) Symbol Rake CH Dec (Viterbi) Perch BCCH (Viterbi) Timing Control Delay Profile Searcher AFC AGC D/A (AFC) D/A (AGC) MPU CPU Peripheral RAM Flash ROM Modulation (HPSK) Formatter Spreader CH_Enc D/A & Fil Speech CODEC (GSM-AMR) D/A A/D Tone Data FEC (Turbo) &I/F MEM I/F PS_Cont. I Q UIM

44 LSI RF MPEG4 USB BlueTooth

橡夏の学校９９.PDF

橡夏の学校９９.PDF VLSI LSI 99/8/20 wada@ie.u-ryukyu.ac.jp http://bw-www.ie.u-ryukyu.ac.jp/~wada/ LSI PC MPEG2 3 LSI LSI LSI 1997 8 23... LSI [1] PC LSI PC LSI PentiumPC L2 Cache Pentium Frame Memory Core Chip Set HOST BUS

橡SysAbst.PDF

橡SysAbst.PDF