Curriculum Vitae ( ) kondo , Software Controlled On-Ch

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1 Curriculum Vitae ( ) kondo@hal.ipc.i.u-tokyo.ac.jp kondo , Software Controlled On-Chip Memory for High-Performance and Low-Power Processor, ( ), ( ), , HPC, ( ), ( ), , LSI,, ( ), , , , , , , , , , IEEE International Symposium on System-on-Chip, Best Paper Award ,, , IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), Best Poster Award , SACSIS2012, , SACSIS2011, , , SACSIS2008, , SACSIS2005, , 2003 (HPCS2003),. [1] Shaswot Shresthamali, Masaaki Kondo, and Hiroshi Nakamura, Adaptive Power Management in Solar Energy Harvesting Sensor Node using Reinforcement Learning, ACM Transactions on Embedded Computing Systems, Vol.16, No.5s, pp.181:1-181:21, Oct [2] Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, and Hiroshi Nakamura, A Runtime Multi-Optimization Framework to Realize Energy Efficient Networks-on-Chip, IEICE Transactions on Information and Systems, Vol.E99-D, No.12, pp , Dec [3] Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, and Mitaro Namiki, An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications, IEICE Transactions on Electronics, Vol.E99-C, No.8, pp , Aug [4] Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, and Mitaro Namiki, A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units, IEICE Transactions on Electronics, Vol.E98-C, No.7, pp , July

2 [5],,,, (ACS), Vol.8, No.1, pp.34-50, [6],,,,,,, FLAT: MPI GPU,, Vol.6, No.4, pp , [7] Son Truong Nguyen, Masaaki Kondo, Tomoya Hirao, and Koji Inoue, A Prototype System for Many-core Architecture SMYLEref with FPGA Evaluation Boards, IEICE Transactions on Information and Systems, Vol.E96-D, No.8, pp , Aug [8] Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki, Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design, IEICE Transactions on Electronics (INVITED PAPER), Vol.E96-C, No.4, pp , April [9],,,,, ACS, Vol.4, No.4, pp.36-50, [10] Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano, Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units, IPSJ Transactions on System LSI Design Methodology, Vol.4, No., pp , Aug [11],,,,, ACS, Vol.4, No.2, pp.40-58, [12],,,,,,,,,,,,,,,, MIPS R3000,, Vol.J93-D No.6, pp , [13],,, Pipeline Blocking, ACS, Vol.2, No.3, pp.83-95, [14] Hiroshi Sasaki, Masaaki Kondo, and Hiroshi Nakamura, Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping, IEEE Transactions on VLSI (Transactions Briefs), Vol.17 Issue 6, pp , June [15],,, CMP, ACS, Vol.1, No.2, pp , [16],,,, Web, ACS, Vol.1, No.1, pp , [17],,,,,,,, Vol.49, No.SIG2(ACS21), pp.20-36, [18],, CMP, Vol.48, No.SIG13(ACS19), pp , [19] Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya, Design Method of High Performance and Low Power Functional Units Considering Delay Variations, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E89-A, No. 12, pp , Dec [20],,,,,,, Vol.47, No.SIG18 (ACS 16), pp.80-91, [21],,,,, Vol.47, No.SIG12 (ACS 15), pp , [22],,,,,, Vol.J98-D No.8, pp , [23],,, Vol.46, No.SIG12(ACS11), pp.62-72, [24],,,,, Vol.45, No.SIG11(ACS7), pp , [25],,,, Vol. 45, No. SIG 6(ACS 6), pp.1-11,

3 [26],,,,, Vol.45, No. SIG(ACS4), pp.77-87, [27] Masaaki Kondo, Takuro Hayashida, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, and Atsushi Hori, Evaluation of Checkpointing Mechanism on SCore Cluster System, IEICE Transactions on Information and Systems, Vol.E86-D, No.12, Dec [28] Masaaki Kondo and Hiroshi Nakamura, Reducing Memory System Energy by Software-Controlled On-Chip Memory, IEICE Transactions on Electronics, Vol.E86-C, No. 4, pp , April [29],,,,,, HPC SCIMA SMP,, Vol.44, No.SIG6(ACS1), [30],,, SCIMA,, Vol.42, No.SIG 12(HPS 4), pp.37-48, [31],,,,,,, SMP-PC,, Vol. 41, No. SIG 5(HPS 1), pp.70-79, [32],,,, SCIMA,, Vol. 41, No. SIG 5(HPS 1), pp.15-27, (CONFERENCE) [1] Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani, OS-ELM-FPGA: An FPGA-Based Online Sequential Unsupervised Anomaly Detector, The 16th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar 18), Aug [2] Ryuichi Sakamoto, Tapasya Patki, Thang Cao, Masaaki Kondo, Koji Inoue, Masatsugu Ueda, Daniel Ellsworth, Barry Rountree, and Martin Schulz, Analyzing Resource Trade-offs in Hardware Overprovisioned Supercomputers, 32nd IEEE International Parallel & Distributed Processing Symposium (IPDPS2018), 10pages, May [3] Yasutaka Wada, Yuan He, Thang Cao, Masaaki Kondo, A Power Management Framework with Simple DSL for Automatic Power-Performance Optimization on Power-Constrained HPC Systems, SupercomputingAsia 2018 (SCA18), 20pages, Mar [4] Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima and Hideharu Amano, The Design and Implementation of Scalable Deep Neural Network Accelerator Cores, IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC- 17), 8pages, Sep [5] Ryuichi Sakamoto, Thang Cao, Masaaki Kondo, Koji Inoue, Masatsugu Ueda, Tapasya Patki, Daniel Ellsworth, Barry Rountree, and Martin Schulz, Production Hardware Overprovisioning: Real-world Performance Optimization using an Extensible Power-aware Resource Management Framework, 31st IEEE International Parallel & Distributed Processing Symposium (IPDPS2017). 10pages, May [6] Thang Cao, Wei Huang, Yuan He, and Masaaki Kondo, Cooling-Aware Job Scheduling and Node Allocation for Overprovisioned HPC Systems, 31st IEEE International Parallel & Distributed Processing Symposium (IPDPS2017), 10pages, May [7] Tetsui Ohkubo, Ryo Tanaka, Ryuichi Sakamoto, Masaaki Kondo, and Hideharu Amano, NAMACHA: A Software Development Environment for a Multi-Chip Convolutional Network Accelerator, 32nd International Conference on Computers and Their Applications (CATA 17), Mar [8] Yuan He and Masaaki Kondo, Opportunistic Circuit-Switching for Energy Efficient On-Chip Networks, The 24th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2016), 6pages, Sep [9] Thang Cao, Yuan He, and Masaaki Kondo, Demand-Aware Power Management for Power-Constrained HPC Systems, The 16th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid2016), pp.21-31, May [10] Yuichi Inadomi, Tapasya Patki, Koji Inoue, Mutsumi Aoyagi, Barry Rountree, Martin Schulz, David Lowenthal, Yasutaka Wada, Keiichiro Fukazawa, Masatsugu Ueda, Masaaki Kondo, and Ikuo Miyoshi, Analyzing and Mitigating the Impact of Manufacturing Variability in Power-Constrained Supercomputing, The International Conference for High Performance Computing, Networking, Storage and Analysis (SC15), 12pages, Nov

4 [11] Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, and Hiroshi Nakamura, Runtime Multi-Optimizations for Energy Efficient On-chip Interconnections, The 33rd IEEE International Conference on Computer Design (ICCD2015) (Accepted as poster presentation), pp , Oct [12] Takeshi Soga, Hiroshi Sasaki, Tomoya Hirao, Masaaki Kondo, and Koji Inoue, A Flexible Hardware Barrier Mechanism for Many-Core Processors, 20th Asia and South Pacific Design Automation Conference (ASP- DAC 2015), pp.61-68, Jan [13] Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Unbalanced Buffer Tree Synthesis to Suppress Ground Bounce for Finegrain Power Gating, International Symposium on System-on-Chip 2014, Oct [14] Masaaki Kondo, Hiroaki Kobyashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda and Hiroshi Nakamura, Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors, Design, Automation and Test in Europe Conference and Exhibition (DATE2014), 6pages, Mar [15] Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Design and Control Methodology for Fine Grain Power Gating based on Energy Characterization and Code Profiling of Microprocessors, 19th Asia and South Pacific Design Automation Conference (ASP-DAC 2014). pp , Jan [16] Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo and Hiroshi Nakamura, Demonstration of a Hetero- geneous Multi-Core Processor with 3-D Inductive Coupling Links, 23rd International Conference on Field Programmable Logic and Applications (FPL2013), Demo Presentations, Sep [17] Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namik, Kimiyoshi Usami, Masaaki Kondo, and Hiroshi Nakamura, Dynamic Power Control with a Heterogeneous Multi-Core System Using a 3-D Wireless Inductive Coupling Interconnect, 2012 International Conference on Field-Programmable Technology (FPT2012), Demo Session, pp , Dec [18] Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Cool Mega Array: a highly energy efficient reconfigurable accelerator, International Conference on Field-Programmable Technologies (FPT 2011), pp.1-8, Dec [19] Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, and Hiroshi Nakamura, Adaptive Power Gating for Function Units in a Microprocessor, 11th IEEE International Symposium on Quality Electronic Design (ISQED-2010), pp.29-37, March [20] Daisuke Ikebuchi, Naomi Seki, Yu Kojima, Masahiro Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Yusuke Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, and Masaaki Kondo, Geyser-1: A MIPS R3000 CPU core with Fine Grain Runtime Power Gating, IEEE Asian Solid-State Circuits Conference 2009 (A-SSCC 2009), pp , Nov [21] Noriko Takagi, Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura, Cooperative Shared Resource Access Control for Low-Power Chip Multiprocessors, 14th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED-2009), pp , Aug [22] Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hidehal Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo and Hiroshi Nakamura, Design and Implementation of Fine-grain Power Gating with Ground Bounce Suppression, The 22nd IEEE International Conference on VLSI Design, pp , Jan [23] Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitustaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo and Hiroshi Nakamura, A Fine Grain Dynamic Sleep Control Scheme in MIPS R3000, XXVI International Conference on Computer Design (ICCD-2008), pp , Oct [24] Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, and Takashi Nanya, Power Reduction of Chip Multi- Processors using Shared Resource Control Cooperating with DVFS, XXV International Conference on Computer Design (ICCD-2007), pp , Oct

5 [25] Hiroshi Sasaki, Masaaki Kondo, and Hiroshi. Nakamura, An Intra-Task DVFS Technique based on Statistical Analysis of Hardware Events, International Conference on Computing Frontiers 2007 (CF 2007), pp , May [26] Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, and Takashi Nanya, Task Scheduling under Performance Constrations for Reducing Energy Consumption of GALS Multi-Processor SoC, Design Automation and Test in Europe 2007 (DATE 2007), April [27] Hiroshi Sasaki, Masaaki Kondo, and Hiroshi. Nakamura, Energy-Efficient Dynamic Instruction Scheduling Logic through Instruction Grouping, International Symposium on Low Power Electronics and Design 2006 (ISLPED 2006), pp.43-48, Oct [28] Masaaki Kondo and Hiroshi Nakamura, Small, Fast and Low-Power Register File by Bit-Partitioning, 11th International Symposium on High-Performance Computer Architecture (HPCA 2005), pp.40-49, Feb [29] Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, and Takashi Nanya, Skewed Checkpointing for Tolerating Multi-Node Failures, 23rd Symposium on Reliable and Distributed Systems (SRDS 2004), pp , Oct [30] Taku Ohneda, Masaaki Kondo, Masashi Imai, and Hiroshi Nakamura, Design and Evaluation of High Performance Microprocessor with Reconfigurable On-Chip Memory, 2002 Asia-Pacific Conference on Circuits and Systems (APCCAS 2002), pp , Oct [31] Masaaki Kondo, Mitsugu Iwamoto, and Hiroshi Nakamura, Cache Line Impact on 3D PDP Solvers, 4th International Symposium on High Performance Computing (ISHPC 2002), LNCS 2327, pp , May [32] Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, and Taisuke Boku, SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing, 2000 International Conference on Computer Design (ICCD 2000), pp , Oct [33] Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku, and Shuichi Sakai, SCIMA: A Novel Processor Architecture for High Performance Computing, HPC-Asia 2000, pp , May (WORKSHOP) [1] Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura, A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface, IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), April [2] Takefumi Miyoshi Keigo Shima Masaaki. Kondo Hidetsugu Irie, Hiroki Honda and Tsutomu Yoshinaga, FLAT: A GPU Programming Framework to Provide Embedded MPI, 5th Workshop on General Purpose Processing on Graphics Processing Units (GPGPU 2012), pp March [3] Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, SLD-1(Silent Large Datapath) A Ultra Low Power Reconfigurable Accelerator, IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XIV), April [4] Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Yusuke Umahashi, Daiki Masuda, Kimiyoshi Usami, Tetsuya Sunata, Kazuki Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo, Geyser-1 and Geyser-2: MIPS R3000 CPU Chips with Fine-grain Runtime Power Gating, IEEE Symposium on Low-Power and High-Speed Chips, (COOL Chips XIII), April [5] Hiroshi Sasaki, Takatsugu Oya, Masaaki Kondo, and Hiroshi Nakamura, Power-Performance Modeling of Heterogeneous Cluster-Based Web Servers, Energy Efficient Grids, Clouds and Clusters Workshop (E2GC2), Oct [6] Toshiya. Komoda, Hiroshi Sasaki, Masaaki Kondo, and Hiroshi Nakamura, Compiler Directed Fine Grain Power Gating for Leakage Power Reduction in Microprocessor Functional Units, 7th Workshop on Optimizations for DSP and Embedded Systems (ODES-2009), Mar [7] Masaaki Kondo Yoshimichi Ikeda, and Hiroshi Nakamura, A High Performance Cluster System Design by Adaptive Power Control Workshop on High-Performance Power-Aware Computing (HPPAC 2007), Mar [8] Masaaki Kondo, Hiroshi Sasaki, and Hiroshi Nakamura, Improving Fairness, Throughput and Energy- Efficiency on a Chip Multiprocessor through DVFS, Workshop on Design, Architecture and Simulation of Chip Multi-Processors 2006 (dascmp 2006), Dec

6 [9] Hiroshi Sasaki, Masaaki Kondo, and Hiroshi. Nakamura, Dynamic Instruction Cascading on GALS Microprocessor, International Workshop on Power And Timing Modeling, Optimization and Simulation 2005 (PATMOS 2005), LNCS 3728, pp.30-39, Sep [10] Masaaki Kondo and Hiroshi Nakamura, Dynamic Processor Throttling for Power Efficient Computations, Workshop on Power-Aware Computer Systems 2004 (PACS 2004), LNCS 3471, pp , Dec [11] Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi, Hiroshi Nakamura, and Mitsuhisa Sato, SCIMA-SMP: On-chip Memory Processor Architecture for SMP, 3rd workshop on Memory performance issues, ACM Electronic Edition, pp , June [12] Motonobu Fujita, Masaaki Kondo, and Hiroshi Nakamura Data Movement Optimization for Software- Controlled On-Chip Memory, 8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT 2004), pp , Feb [13] Masaaki Kondo, Shinichi Tanaka, Motonobu Fujita, Hiroshi Nakamura, Reducing Memory System Energy in Data Intensive Computations by Software-Controlled On-Chip Memory, Workshop on Compilers and Operating Systems for Low Power, (COLP 2002), Sep [14] Hiroshi Nakamura, Masaaki Kondo, and Taisuke Boku, Software Controlled Reconfigurable On-Chip Memory for High Performance Computing, 2nd International Workshop on Intelligent Memory Systems, LNCS 2107, pp.15-32, [1] Masaaki Kondo, Reinforcement Learning-Based Adaptive Power Management for Energy Harvesting IoT Devices, International Forum on MPSoC for Software-defined Hardware (MPSoC), July [2] Masaaki Kondo, Energy Efficient Network-on-Chips with Opportunistic Circuit-Switching for MPSoCs, International Forum on MPSoC for Software-defined Hardware (MPSoC), July [3] Masaaki Kondo, Research and Development of Power Management Framework for Exascale Computing, The 35th JSST Annual Conference International Conference on Simulation Technology (Invited Talk), Oct [4] Masaaki Kondo, Demand-Aware Power Management for Power-Constrained HPC Systems, 16th International Forum on Embedded MPSoC and Multicore (MPSoC 16), July [5],,,,,,,, TCI SOTB ICD, [6],, STE ( ), [7] Masaaki Kondo, Assisting Cache Replacement by Helper-Threading for MPSoCs, 15th International Forum on Embedded MPSoC and Multicore (MPSoC 15), July [8] Masaaki Kondo, Power Management Framework for Extreme-Scale Computing, The workshop on Big Data and Extreme-scale Computing (BDEC), Jan [9] Masaaki Kondo, Evaluating Power-Efficientcy for an Embedded Microprocessor with Fine-Grained Power- Gating Demand-Aware Power Management for Power-Constrained HPC Systems, 14th International Forum on Embedded MPSoC and Multicore (MPSoC 14), July [10], Power Wall,, [11] Masaaki Kondo, SMYLEref: A Reference Architecture for Manycore-Processor SoCs, 13th International Forum on Embedded MPSoC and Multicore (MPSoC 13), July [12] Masaaki Kondo, Son Truong Nguyen, Tomoya Hirao, Takeshi Soga, Hiroshi Sasaki, and Koji Inoue, SMYLEref: A Reference Architecture for Manycore-Processor SoCs, Asia and South Pacific Design Automation Conference (ASP-DAC), pp , Jan [13],,,, 2012 ( ), [14],,, SMYLEref, 4, [15],,, Aug

7 [16] Koji Inoue and Masaaki Kondo, SMYLE: Scalable Many-core for Low-Energy computing, 12th International Forum on Embedded MPSoC and Multicore (MPSoC 12), July [17] Masaaki Kondo, Report on Exascale Architecture Roadmap in Japan, 8th The International Exascale Software Roadmap Meeting (IESP Meeting 8), April [18],,, (SWEST2011), [1], HPC,, Vol. 36, No. 2, pp.85-88, [2] Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, and Hiroshi Nakamura, A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface 3D NoC, IEEE Micro Magazine, Vol.33, Issue 6, pp.6-15, Nov/Dec [3] Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips, IEEE MICRO Magazine, Vol.31, No.6, Dec [4] Hiroshi Sasaki, Hideharu Amano, Kimiyoshi Usami, Masaaki Kondo, Mitaro Namiki, and Hiroshi Nakamura (Ishfag Ahmad and Sanjay Ranka ), Handbook of Energy-Aware and Green Computing, 1 : Geyser: Energy-Efficient MIPS CPU Core with Fine-Grained Run-Time Power Gating, Chapman Hall/CRC Computer Information Science Series, pp.49-65, [5] ( ), LSI, 2 : SimpleScalar Tool Set,, ( ) [1] 24th Asia and South Pacific Design Automation Conference (ASP-DAC 2019),, [2] The 51th Annual IEEE/ACM International Symposium on Microarchitecture (Micro 2018),, [3] The 51th Annual IEEE/ACM International Symposium on Microarchitecture (Micro 2018), Finance Co-Chair, [4] The IEEE Cluster 2018, TPC Area Chair (Architecture, Network/Communications, and Management Area), [5] International Symposium on Low Power Electronics and Design (ISLPED 18),, [6] 2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2018),, [7] 23rd Asia and South Pacific Design Automation Conference (ASP-DAC 2018),, [8] International Symposium on Low Power Electronics and Design (ISLPED 17),, [9] 46st International Conference on Parallel Processing (ICPP 2017),, [10] The IEEE Cluster 2017, Publicity Chair, [11] 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2017), Publicity Co-Chair, [12] 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2017),, [13] 22nd Asia and South Pacific Design Automation Conference (ASP-DAC 2017),, [14] IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2016),, [15] The IEEE Cluster 2016,, [16] International Symposium on Low Power Electronics and Design (ISLPED 16),, [17] 16th International Forum on MPSoC for Software-defined Hardware (MPSoC 16), Program Co-Chair, [18] The 25th International Symposium on High-Performance Parallel and Distributed Computing (HPDC 16), Publicity Co-Chair,

8 [19] IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2015),, [20] The IEEE Cluster 2015,, [21] International Symposium on Low Power Electronics and Design (ISLPED 15),, [22] 52nd Design Automation Conference (DAC 2015),, [23] The International Conference for High Performance Computing, Networking, Storage and Analysis (SC14),, [24] International Symposium on Low Power Electronics and Design (ISLPED 14),, [25] 2013 International Conference on High Performance Computing (HiPC 2013),, [26] International Symposium on Low Power Electronics and Design (ISLPED 13),, [27] 1st International Workshop on Strategic Development of High Performance Computers,, [28] International Symposium on Low Power Electronics and Design (ISLPED 12),, [29] IEEE 17th Pacific Rim International Symposium on Dependable Computing (PRDC),, [30] 41st International Conference on Parallel Processing (ICPP 2012),, [31] 18th IEEE International Conference on High Performance Computing (HiPC2011),, [32] 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA),, [33] International Symposium on Low Power Electronics and Design (ISLPED 11),, [34] International Symposium on Low Power Electronics and Design (ISLPED 11),, [35] IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips),, [36] International Symposium on Low Power Electronics and Design (ISLPED 10),, [37] IEEE 16th Pacific Rim International Symposium on Dependable Computing (PRDC),, [38] Sixteenth International Conference on Parallel and Distributed Systems (ICPADS),, [39] 2010 International Symposium on Embedded Multicore SoCs (MCSoC),, [40] 10th IEEE International Conference on Computer and Information Technology (CIT),, [41] IEEE Symposium on Low-Power and High-Speed Chips 2010 (COOL Chips),, [42] Tenth International Conference on Parallel and Distributed Computing, Applications and Technologies (PD- CAT),, [43] 2009 International Symposium on Embedded Multicore SoCs (MCSoC),, [44] IEEE Symposium on Low-Power and High-Speed Chips 2009 (COOL Chips),, [45] 10th IEEE International Conference on High Performance Computing and Communications (HPCC),, ( ) [1] FIT ,, [2] FIT ,, [3] 1st Cross-Disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xsig2017),, [4],, [5] 2015,, [6],, [7] 8,, [8],, [9],, [10] / / SWoPP2012,, [11] / / SWoPP2011,, [12] / / SWoPP2010,,

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10 [7],,,,,,,,,, CMA:, 2011, pp , ( ). [8],,,,, MPI GPU, SACSIS2011, pp , [9],,,,, SACSIS2009, pp.11-18, [10],,,,,,, Linux, 20, Vol.2008, No.12, pp.77-86, [11],,,,,, SACSIS2008, pp , [12],,, : CMP, SACSIS2008, pp , (SACSIS2008 ). [13],,,, SACSIS2008, pp.73-80, [14], Lei Zhao,,,,,,,,,,,,,,,, MIPS R3000, SACSIS2008, pp.65-72, [15],,,,,,,, 2007 (ComSys 2007), Vol.2007, No.14, pp , Nov [16],, CMP, SAC- SIS2007, pp , [17],,,, SACSIS2006, pp , [18],,,,,, SACSIS2006, pp.67-74, [19],,, SACSIS2005, pp , (SACSIS2005 ). [20],,,,, SACSIS2004, pp.3-10, [21],,,,,, HPC SCIMA SMP, HPCS2003, pp.47-54, ( ). [22],,,,, JSPP2002, pp , ( : ) [1],,, Cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xsig2017), [2] Atsushi Koshiba, Jun Tsukamoto, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, and Mitaro Namiki, A Fine-grained Power Gating Control using Leakage Monitor by Linux Process Scheduler, IEEE Symposium on Low-Power and High-Speed Chips (CoolChips XVII), Apr [3] Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda and Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usam, Masaaki Kondo, and Hiroshi Nakamura, A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface, HOTCHIPS 2013, Aug [4],,,,, SACSIS2013,

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