Vol. 47 No. 2 Feb TSVM TSVM ID ID TSVM TSVM TSVM % 74% % 17% Mechanisms Hiding Miss Penalty for Cache Memory to Shared
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1 Vol. 47 No. 2 Feb TSVM TSVM ID ID TSVM TSVM TSVM % 74% % 17% Mechanisms Hiding Miss Penalty for Cache Memory to Shared Variables with Synchronization on a Chip-multiprocessor Akira Yamawaki and Masahiko Iwane To hide cache miss penalty is important for improving a performance of processors. On a chip multiprocessor, the TSVM cache performs inter processor communication and synchronization simultaneously with coherence maintenance to make parallel processing more efficiently. To utilize entries more efficiently among tasks and threads, the TSVM cache specifies a shared variable with synchronization by the tag including the task ID and thread ID. To not use a structured physical memory with synchronization mechanism, the TSVM cache treats shared variables with synchronization as just structures on a conventional main memory. Thus, when a cache miss occurs, the TSVM cache translates a tag to the address and transfers the structured line to the memory. This paper attempts to improve the performance more by introducing the mechanisms to hide the miss penalty for the TSVM cache. The result shows that the introduced mechanisms improve a speedup up to 2.77 times (1.91 times on average) compared with a conventional data cache, and suppress a bus utilization up to 17% (11% on average). It is also confirmed that overheads of communication and synchronization make a capability of prefetching delay strong. 1. ILP 1) CMP 2) 4) 1 L1 Faculty of Engineering, Kyushu Institute of Technology CMP 5) 8) TSVM Tagged Shared Variable Memory TSVM 566
2 Vol. 47 No. 2 CMP ) 10) 12) ID ID TSVM 2 TSVM TSVM TSVM 2.1 TSVM CMP TSVM CMP ) 1 TSVM CMP Fig. 1 Concept of CMP with TSVM cache. DC TSVM TC GC TSVM 6) TSVM TSVM TSVM TSVM tag ID ID ID TSVM 13) TSVM sc 0 empty 0 full TSVM
3 568 Feb Fig. 2 Organization of data cache with TSVM cache. wf 1 wf 6) gr TSVM 5) TSVM false sharing 1 1 v 2 ns gc nw gc ns tc TSVM nw tc nb gcd nb gcc nb tcd nb tcc tnb org tnb org =(nb gcd +nb gcc ) ns org nw gc (1) ns org TSVM tnb pro tnb pro =(nb gcd +nb gcc ) ns gc nw gc +(nb tcd +nb tcc ) ns tc nw tc (2) gr tnb 3 Fig. 3 Tag to address translation mechanism. gr tnb = (tnb pro tnb org )/tnb org (3) tdt: Task Description Table thdt: THread Description Table TSVM tdtr tdt Register tdt tdt 1 thdt tdt 0 thdt 1 thdt 0 tdtr tdt tid thdt thdt thid thdt ID ssvid 2.4 TSVM 4 5) 7) 4 RXLT RXST wf gr / LW/SW 5)
4 Vol. 47 No. 2 CMP 569 RXLT 4 Fig. 4 Load/store instructions for TSVM. 5 TSVM Fig. 5 State transition diagram of TSVM cache line. RXLT RelaXed Load Tsvm RXST Relaxed Store Tsvm gr wf RXLT RXST TSVM 1 RXLT RXST 5 5(a) 5(b) I Invalid TSVM E Empty 0 FE Far-Empty NE Near-Empty full 2 1 I FE NE E RXLT E FE wf 1 RXST FE NE RXST 1 1 RXLT 1 RXST TSVM E FE NE I FE NE RXLT E RXST RXLT TSVM RXLT RXST TSVM TATB Tag to Address Translation Buffer SHT Snoop History Table TATB SHT 6 (a) (b) TATB CAM Content Addressable Memory tid thid tdt[tid] thdt[thid] CAM tid thid TSVM tid thid
5 570 Feb TSVM Fig. 7 Prefetch mechanism for TSVM cache. TATB SHT 6 TATB SHT Fig. 6 Organization of TATB and SHT. (1) tid thid ssv (2) tid thid CAM tid thid tdt[tid] thdt[thid] (3) tid CAM tid thid tdt[tid] thdt[thid] SHT CAM 0 CAM 1 CAM 0 TSVM CAM 1 TSVM TSVM CAM 0 CAM 0 TSVM TSVM CAM 1 TSVM / TSVM CAM 0 CAM 1 tid thid 3.2 PFT Register, tag_wordaddr PFT PFT PFT 7 PFT PFT TSVM PFT TSVM PFT PFT PFT PFT FIFO PFT TSVM
6 Vol. 47 No. 2 CMP 571 PFT TATB SHT PFT 1 PFT TSVM TSVM PFT PFT nb tcd nb tcc CMP 8 16 KB 16 KB L1 32 MIPS-II 5 MMU 14),15) G2 PowerPC 16) 8 15 KB 8 TSVM CMP Fig. 8 Model of CMP with TSVM cache. 1KB TSVM TSVM LRU Dragon tid thid 3 ssvid ) TSVM 1 TSVM 1 9 RXLT RXST 8) Dragon
7 572 Feb TAG Fig. 9 TAG format and structure of SSV on memory. 1 Table 1 Basic performance. TSVM /8 2/9 2/ TATB SHT 4 4 PFT 1 L2 1 TSVM SHT TATB tid thid tid gcc O3 4.2 TSVM 10 (a) (b) 10 Fig. 10 Detail of coherence maintenance TSVM RXLT RXST wf gr TSVM TSVM 4 RXLT RXST TSVM 11 (a) (b)
8 Vol. 47 No. 2 CMP Fig. 11 Evaluation programs. 14 doacross Fig. 14 Execution of doacross loop. doacross 2 PFT 12 doacross Fig. 12 Parallelization of loop programs on doacross fashion. 13 Fig. 13 PFT Insertion of PFT. NAS kernel Benchmark Program doacross RXLT 1 2 RXST nm mid ID tmp1 tmp2 PFT 13 PFT 1 2 nm mid 12 PFT PFT 512 2KB TSVM doacross 14 RXST RXLT PFT S3 1 t scov RXST TSVM RXLT RXLT RXLT RXST TSVM
9 574 Feb Table 2 2 doacross Characteristics of doacross loops (average). t cscov t scov t pd t pov loop loop t cscov RXST RXLT t cscov <t scov t cscov t scov doacross t scov TSVM t pd PFT PFT TSVM t pov PFT t pd <t pov TSVM t pd t scov t pov t pov 2 doacross b 3 t TATB s SHT p m1 m2 8 TSVM 0KB 16 KB 17 17) 15 loop1 Fig. 15 Speedup ratio of loop1. 16 loop2 Fig. 16 Speedup ratio of loop2. 17 doacross Fig. 17 Doacross loops on conventional cache memory. nm mid 12 m1 Dragon m2 software-controlled updating 10) loop1 loop2 2 loop2 m Dragon
10 Vol. 47 No. 2 CMP loop1 Fig. 19 Breakdown of loop1 execution. 20 loop2 Fig. 20 Breakdown of loop2 execution. 18 loop1 Fig. 18 Analysis of loop1 execution m TSVM (b) loop1 8 loop2 4 b btsp m1 m2 b btsp b m1 m2 loop (a) 1 1 TSVM (b) (d) b m1 m2 0 2 t scov b t scov m m TSVM b 1 E B T TSVM M 15 m1 m2 b TSVM
11 576 Feb TATB 5 Table 3 Effects of TATB. Table 5 Effects of prefetching. b bt loop1 loop SHT SHT TATB Table 4 Effects of SHT and SHT with TATB. bt bts loop1 loop b bts loop1 loop loop1 p b bp bt btp bts btsp loop2 p b bp bt btp bts btsp TATB SHT 3 b bt TSVM A B B A bt b TSVM 49% 67% TATB t scov bt bts b bts 4 bt bts bt 37% 94% SHT t scov b TATB SHT 18% 64% b bt bts loop1 9% loop2 2% 5 TSVM 8% 53% t pd t scov 6 Table 6 TATB SHT Total effect of TATB, SHT and prefetching. b btsp loop1 loop Table 7 Reduction ratio of stall time due to combinations of introduced mechanisms. b bts bp btp btsp loop loop b btsp 6 TATB SHT 7% 21% b bts bp btp btsp TSVM 7 TATB SHT bp btp bts TATB SHT 4.6 bp btp btsp t pd t pov TSVM 8 p
12 Vol. 47 No. 2 CMP loop1 loop2 t pd t pov Table 8 t pd, t pov and hit ratio of loop1 and loop2 execution. p loop1 loop2 bp btp btsp bp btp btsp 2 t pd ˆt pov t pov hit t pd ˆt pov t pov hit t pd ˆt pov t pov hit loop1 Fig. 21 Bus cycles and utilization on loop1 execution. t pd ˆt pov t pov t pd t pov ˆt pov hit 8 t scov t pd btsp loop1 loop2 b b bt bs bts bt b 57% 60% TATB bs b 22 loop2 Fig. 22 Bus cycles and utilization on loop1 execution. 9 Table 9 Reduction ratio of system bus cycles. p b bt b bs b bts loop loop % 50% SHT TATB SHT 8% 29% b 44% 74% btsp 11% 17% 8 bp loop1 4 8 loop2 8 t pov ˆt pov t pd btp loop1 8 t pov bp loop % 97% loop2 8 91% btp loop1 8 92% t pov btsp loop1 8 17% t pov m1
13 578 Feb Table 10 Estimation of hardware count. gr tnb tnb pro tnb org nb gcd nb gcc nb tcd nb tcc ns org ns gc ns tc nw gc nw tc , , m2 btsp m1 1/14 m2 1/7 5. (1) (3) 10 TATB 6(a) 7 tid + thid + v 64 4 TATB 284 SHT 6(b) CAM v CAM 0 1,388 CAM v 4 CAM SHT 1, v v 4 1,364 TATB 284 SHT 1,520 1,364 3,168 TSVM 3 10 ((tnb pro ) tnb org )/tnb org = KB 1KB TSVM 17 KB 1KB TSVM 7% tid thid TLB TLB TSVM TATB read snarfing software-controlled updating cache injection 10) 2 SHT cache injection cache injection injection table injection table 1 injection table injection table cache injection SHT SHT TSVM TSVM SHT injection table
14 Vol. 47 No. 2 CMP 579 SHT 9) 2 bundling 11) 1 12) 6.2 / 18),19) 6) 8) I-structure 17),20),21) I-structure TSVM I-structure 6),8) TSVM empty I-structure full/empty TSVM I-structure 6) I-structure full/empty TSVM TSVM CMP TSVM I-structure MISC 17) all-read all-write all-read-write doacross all-read-write TSVM TSVM all-read-write MISC TSVM SHT MISC TSVM gr 5) MISC TSVM 5)
15 580 Feb RXLT RXST JUMP-1 I-structure 20) 21) I-structure 7. TSVM CMP TSVM TATB TSVM / SHT 2 doacross TSVM % 74% % 17% CMP TSVM TSVM 16 KB 1KB 3% TSVM TSVM TSVM 1) Austin, T., Blaauw, D., Mahike, S. and Mudge, T.: Mobile Supercomputers, IEEE Computer, Vol.37, No.5, pp (2004). 2) Codrescu, L., Wills, D.S. and Meindln, J.: Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications, IEEE Trans. Comput., Vol.50, No.1, pp (2001). 3) Kimura, K., Kodaka, T., Obata, M. and Kasahara, H.: Multigrain Parallel Processing on Compiler Cooperative OSCAR Chip Multiprocessor Architecture, IEICE Trans. Electronics, Vol.E86-C, No.4, pp (2003). 4) Hammond, L., Hubbert, B., Siu, M., Prabhu, M., Chen, M. and Olukotun, K.: The Stanford Hydra CMP, IEEE MICRO Magazine, Vol.20, No.2, pp (2000). 5) Yamawaki, A. and Iwane, M.: Organization of Shared Memory with Synchronization on Multiprocessor-on-a-chip, Proc. 9th Int. Conf. on Parallel and Distributed Systems, pp (2002). 6) Vol.J87-D-I, No.12, pp (2004). 7) Yamawaki, A. and Iwane, M.: Evaluation of Mechanisms Introduced to Improve Performance of TSVM Cache, Proc.Int.Conf.on Parallel and Distributed Computing and Networks, pp (2004). 8) Yamawaki, A. and Iwane, M.: Implementation and Evaluation of Novel Cache Architecture for Communicating Shared Variable with Synchronization on a SOC-multiprocessor, The 1st Workshop on Embedded Parallel Architectures, pp.1 6 (2004). 9) Vanderwiel, S.P.: Data Prefetch Mechanisms, ACM Computing Surveys, Vol.32, No.2, pp (2000). 10) Milenkovic, A.: Achieving High Performance
16 Vol. 47 No. 2 CMP 581 in Bus-Based Shared-Memory Multiprocessors, IEEE Concurrency, Vol.8, No.3, pp (2000). 11) Wallin, D. and Hagersten, E.: Bundling: Reducing the Overhead of Multiprocessor Prefetchers, Proc. 18th Int. Symp. on Parallel and Distributed Processing, pp (2004). 12) Tullsen, D.M. and Eggers, S.J.: Effective Cache Prefetching on Bus-Based Multiprocessors, ACM Trans. Comput. Syst., Vol.13, No.1, pp (1995). 13) Nuth, P.R. and Dally, W.: The named state register file: Implementation and performance, Proc. 1st Int. Symp. in High-Performance Computer Architecture, pp.4 13 (1995). 14) Hennesy, J.L. and Patterson, D.A.: Computer Architecture: A Quantitative Approach, 3rd Edition, Morgan Kaufmann (2003). 15) Yamawaki, A., Chayamichi, H. and Iwane, M.: Easily Customizable Open Soft Processor Cores, The st IEEE Technical Exhibition Based Conference on Robotics and Automation, pp (2004). 16) Motorola: G2 PowerPC Core Reference Manual Rev.1, Motorola. Inc (2003). 17) DO- ACROSS Vol.34, No.4, pp (1993). 18) Tarui, T., Nakagawa, T., Ido, N., Asaie, M. and Sugie, M.: Evaluation of the Lock Mechanism in a Snooping Cache, Proc. 6th Int. Conf. on Supercomputing, pp (1992). 19) Ramachandran, U. and Lee, J.: Cache-Based Synchronization in Shared Memory Multiprocessors, Journal of Parallel and Distributed Computing, Vol.32, No.2, pp (1996). 20) Goshima, M., Mori, S., Nakashima, H. and Tomita, S.: The Intelligent Cache Controller of a Massively Parallel Processor JUMP-1, Proc. Intl. Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, pp (1997). 21) Kavi, K.M. and Hurson, A.: Design of cache memories for dataflow architecture, Journal of Systems Architecture, Vol.44, pp (1998). ( ) ( ) LSI IEEE Computer Society
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