2. HTM 2.1 TM Tx Tx TM Tx 2 Serializability Tx Tx Atomicity Tx Tx Tx Tx Tx Tx Conflict TM Tx Abort Tx Tx Tx HTM [4] Cache 1 Tag 0x100 Data
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1 TM TM TM 27.4% 99.9% 17.7% 36.5% 1. Transactional Memory: TM [1] TM Transaction: Tx TM Tx 1 Nagoya Institute of Technology 2 Nagoya University 3 National Institute of Informatics Tx TM Tx Hardware Transactional Memory: HTM [2], [3] Tx HTM Tx HTM c 2018 Information Processing Society of Japan 1
2 2. HTM 2.1 TM Tx Tx TM Tx 2 Serializability Tx Tx Atomicity Tx Tx Tx Tx Tx Tx Conflict TM Tx Abort Tx Tx Tx HTM [4] Cache 1 Tag 0x100 Data (t2-i) Fill and Write 1 R W 0 1 (t2-ii) Set Write bit (t3-ii) NACK (t3-i) Sharing Req. Shared Memory Address a[0-3] 0x100-0x10C Data Core 2 Cache Tag Data Thread1 Thread2 t1 BEGIN TRANSACTION; BEGIN TRANSACTION; t2 t3. a[0]=26;. COMMIT TRANSACTION; 2 tmp=a[2];. COMMIT TRANSACTION; 2.2 HTM R W HTM Read/Write Tx 1 Core Cache Shared Memory 2 Core1 Core2 Thread1 Thread2 2 2 BEGIN TRANSACTION COMMIT TRANSACTION Tx 2 Tx t1 Thread1 a[0] t2 Cache1 a[0] 0x100 a[0] 1 t2-i 0x100 Tx Write 0x100 Write 1 t2-ii Thread2 a[0] a[2] t3 Cache2 c 2018 Information Processing Society of Japan 2
3 a[2] Cache1 0x100 1 t3-i Thread1 0x100 Read/Write Write Thread1 Thread2 NACK 1 t3-ii HTM Read/Write 3. Tx HTM 3.1 HTM LogTM[5] Simics [6] GEMS [7] Simics GEMS 32 SPARC V9 OS Solaris 10 1 LogTM [8] Illinois [9] GEMS microbench[7] SPLASH-2[10] STAMP[11] (B) (S) LogTM (B) Read/Write (B) 1 (S) Processor #cores clock issue width issue order 1 non-memory IPC 1 D1 cache ways latency D2 cache ways latency Memory latency Interconnect network latency 2 GEMS microbench Btree SPARC V9 32 cores 4 GHz single in-order 32 KBytes 4 ways 3 cycles 8 MBytes 8 ways 20 cycles 4 GBytes 450 cycles Contention config 1 Deque Prioqueue Slist SPLASH2 Cholesky priv-alloc-20pct 4096ops 128bkoff 8192ops 1024ops 64len tk14.0 Radiosity -p 31 STAMP Kmeans -m40 -n40 -t cycles -i random-n2048-d16-c16.txt Vacation -q10 -u80 -r t4096 Read/Write Non trans Tx Good trans Tx Bad trans Tx Aborting Backoff Stall 3 (B) NACK 99.9% 27.4% (S) (B) 87.9% 24.7% c 2018 Information Processing Society of Japan 3
4 Ratio of cycles (B) 既存のLogTM (S) 既存のLogTMに変数分のRead/Writeビットを追加したモデル GEMS microbench SPLASH-2 STAMP 3 3 Btree Contention Prioqueue SortedList 0.6% 0.0% 45.8% 99.9% Cholesky Radiosity Kmeans Vacation 3.7% 66.5% 0.3% 29.8% Barrier Stall Backoff Aborting Bad_trans Good_trans non_trans 3.3 Prioqueue SortedList (S) (B) Vacation Vacation Stall Abort Non trans (B) (S) Vacation Vacation 3 Tx 98% Tx 4 Tx 5 long int for (i = 0; i < numoperation; i++) { 2 action = /* */ 3 switch (action) { 4 case MAKE_RESERVATION: { 5 BEGIN_TRANSACTION(0); 6 for(n = 0; n < numquery; n++){ 7 types[n] = /* */ 8 } 9 for (n = 0; n < numquery; n++) { 10 switch (types[n]) { 11 case RESERVATION_CAR: 12 /* */ 13 break; 14 case RESERVATION_FLIGHT: 15 /* */ 16 break; 17 case RESERVATION_ROOM: 18 /* */ 19 break; 20 } 21 } /* */ 23 COMMIT_TRANSACTION(0); 24 break; 25 } /* case */ 27 } 28 } 4 Vacation Tx 1 typedef struct reservation { 2 long id; 3 long numused; 4 long numfree; 5 long price; 6 } reservation_t; 5 1 #define N typedef struct random { 4 unsigned long (*rand) (unsigned long*, unsigned long*); 5 unsigned long mt[n]; 6 unsigned long mti; 7 } random_t; 6 Vacation Tx Tx Tx Vacation c 2018 Information Processing Society of Japan 4
5 6 HTM HTM Read/Write Tx Bloom [12] Bloom Cache 0 Core N Address Data R W C Conflict Address Buffer Read Signature Write Signature 7 Bloom 4.2 HTM 7 3 Conflict Bit C 1 Conflict Address Buffer C-Buffer Tx Read/Write Signature R/W-Signature Bloom Thread0 t1 Read/Write 8 t1-i Read C 8 t1-ii C c 2018 Information Processing Society of Japan 5
6 Ratio of cycles t1 t2 load A Thread 0 Tx.X NACK Req.B Thread 1 Tx.Y store B Cache 1 Address Data R W C 0x100-0x10C (t1-i) Check R/W bit Conflict Address Buffer (t1-ii) Check C bit (t3) Set C bit 0x (B) 既存のLogTM (S) 既存のLogTMに変数分のRead/Writeビットを追加したモデル (P) 提案モデル Non_trans Good_trans Bad_trans Aborting Backoff Stall Barrier t3 Commit Read Signature (t2) Register Line address Write Signature GEMS microbench SPLASH-2 STAMP t1 t2 t3 load A 9 Thread 0 Tx.X Commit ACK Req.B Thread 1 Tx.Y store B Cache 0 Address Data R W C 0x100-0x10C Conflict Address Buffer Read Signature Write (t1-iii) Signature Register address (t1-i) Set R bit (t1-ii, t2) Check C bit Thread1 NACK t2 C-Buffer 8 t2 Thread0 C-Buffer C C-Buffer t Thread0 Thread1 Tx 9 t0 Thread0 A load Thread1 ACK Read 9 t1-i C 9 t1-ii C R/W-Signature A 9 t1-iii Thread1 B Thread0 C 9 t2 10 R/W-Signature B Core0 R/W-Signature B B Thread0 Thread1 ACK t3 LogTM[5] MESI Write Write invalidate LogTM (B) LogTM (S) (B) Read/Write c 2018 Information Processing Society of Japan 6
7 (P) (B) (B) (S) 3 (P) (B) 36.5% 17.7% (P) 3 (S) Kmeans Vacation (S) SortedList (B) (S) (P) Bloom Bloom Bloom 1 Bloom [13] 6. HTM 17.7% 36.5% JSPS JP17H01711 JP17H01764 JP17K19971 [1] Herlihy, M. et al.: Transactional Memory: Architectural Support for Lock-Free Data Structures, Proc. 20th Int l Symp. on Computer Architecture (ISCA 93), pp (1993). [2] Knight, T.: An Architecture for Mostly Functional Languages, Proceedings of the 1986 ACM Conference on LISP and Functional Programming, pp (1986). [3] Hammond, L., Wong, V., Chen, M., Carlstrom, B. D., Davis, J. D., Hertzberg, B., Prabhu, M. K., Wijaya, H., Kozyrakis, C. and Olukotun, K.: Transactional Memory Coherence and Consistency, Proc. 31st Annual Int l Symp. Computer Architecture (ISCA 04), pp. 102 (2004). [4] Shavit, N. and Touitou, D.: Software Transactional Memory, Proc. 14th ACM Symposium on Principles of Distributed Computing, pp (1995). [5] Moore, K. E., Bobba, J., Moravan, M. J., Hill, M. D. and Wood, D. A.: LogTM: Log-based Transactional Memory, Proc. 12th Int l Symp. on High-Performance Computer Architecture (HPCA 06), pp (2006). [6] Magnusson, P. S., Christensson, M., Eskilson, J., Forsgren, D., Hållberg, G., Högberg, J., Larsson, F., Moestedt, A. and Werner, B.: Simics: A Full System Simulation Platform, Computer, Vol. 35, No. 2, pp (2002). [7] Martin, M. M. K., Sorin, D. J., Beckmann, B. M., Marty, M. R., Xu, M., Alameldeen, A. R., Moore, K. E., Hill, M. D. and Wood., D. A.: Multifacet s General Execution-driven Multiprocessor Simulator (GEMS) Toolset, ACM SIGARCH Computer Architecture News, Vol. 33, No. 4, pp (2005). [8] Sweazey, P. and Smith, A. J.: A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus, Proc. 13th Annual Int l. Symp. on Computer Architecture (ISCA 86), pp (1986). [9] Censier, L. M. and Feautrier, P.: A New Solution to Coherence Problems in Multicache Systems, IEEE Trans. on Computers, Vol. C-27, No. 12, pp (1978). [10] Woo, S. C., Ohara, M., Torrie, E., Singh, J. P. and Gupta, A.: The SPLASH-2 Programs: Characterization and Methodological Considerations, Proc. 22nd Annual Int l. Symp. on Computer Architecture (ISCA 95), pp (1995). [11] Minh, C. C., Chung, J., Kozyrakis, C. and Olukotun, K.: STAMP: Stanford Transactional Applications for Multi- Processing, Proc. IEEE Int l Symp. on Workload Characterization (IISWC 08) (2008). [12] Bloom, B. H.: Space/Time Trade-offs in Hash Coding with Allowable Errors, Commun. ACM, Vol. 13, No. 7, pp (online), DOI: / (1970). [13] Vol ARC-212, No. 17, pp (2014). c 2018 Information Processing Society of Japan 7
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1,a) 2 2 1. 1 College of Information Science, School of Informatics, University of Tsukuba 2 Faculty of Engineering, Information and Systems, University of Tsukuba a) oharada@iplab.cs.tsukuba.ac.jp 2.
A Feasibility Study of Direct-Mapping-Type Parallel Processing Method to Solve Linear Equations in Load Flow Calculations Hiroaki Inayoshi, Non-member
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IPSJ SIG Technical Report Vol.2013-ARC-206 No /8/1 Android Dominic Hillenbrand ODROID-X2 GPIO Android OSCAR WFI 500[us] GPIO GP
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SOA 1 1 1 1 (HNS) HNS SOA SOA 3 3 A Service-Oriented Platform for Feature Interaction Detection and Resolution in Home Network System Yuhei Yoshimura, 1 Takuya Inada Hiroshi Igaki 1, 1 and Masahide Nakamura
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Express5800/320Fa-L/320Fa-LR
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GPU Graphics Processing Units HPC High Performance Computing GPU GPGPU General-Purpose computation on GPU CPU GPU GPU *1 Intel Quad-Core Xeon E5472 3.0 GHz 2 6 MB L2 cache 1600 MHz FSB 80 GFlops 1 nvidia
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IPSJ SIG Technical Report Vol.2009-DPS-141 No.20 Vol.2009-GN-73 No.20 Vol.2009-EIP-46 No /11/27 1. MIERUKEN 1 2 MIERUKEN MIERUKEN MIERUKEN: Spe
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AUTOSAR 1 1, 2 2 2 AUTOSAR AUTOSAR 3 2 2 41% 29% An Extension of AUTOSAR Communication Layers for Multicore Systems Toshiyuki Ichiba, 1 Hiroaki Takada, 1, 2 Shinya Honda 2 and Ryo Kurachi 2 AUTOSAR, a
N Express5800/R320a-E4 N Express5800/R320a-M4 ユーザーズガイド
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Express5800/R320a-E4, Express5800/R320b-M4ユーザーズガイド
7 7 Phoenix BIOS 4.0 Release 6.0.XXXX : CPU=Pentium III Processor XXX MHz 0640K System RAM Passed 0127M Extended RAM Passed WARNING 0212: Keybord Controller Failed. : Press to resume, to setup
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Vol. 52 No. 1 257 268 (Jan. 2011) 1 2, 1 1 measurement. In this paper, a dynamic road map making system is proposed. The proposition system uses probe-cars which has an in-vehicle camera and a GPS receiver.
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IPSJ SIG Technical Report iphone iphone,,., OpenGl ES 2.0 GLSL(OpenGL Shading Language), iphone GPGPU(General-Purpose Computing on Graphics Proc
iphone 1 1 1 iphone,,., OpenGl ES 2.0 GLSL(OpenGL Shading Language), iphone GPGPU(General-Purpose Computing on Graphics Processing Unit)., AR Realtime Natural Feature Tracking Library for iphone Makoto
2006 [3] Scratch Squeak PEN [4] PenFlowchart 2 3 PenFlowchart 4 PenFlowchart PEN xdncl PEN [5] PEN xdncl DNCL 1 1 [6] 1 PEN Fig. 1 The PEN
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PenFlowchart 1,a) 2,b) 3,c) 2015 3 4 2015 5 12, 2015 9 5 PEN & PenFlowchart PEN Evaluation of the Effectiveness of Programming Education with Flowcharts Using PenFlowchart Wataru Nakanishi 1,a) Takeo Tatsumi
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Master's Thesis / 修 士 論 文 映 像 配 信 の 中 断 から 復 旧 までの 時 間 を 短 縮 するネットワーク 再 構 築 手 法 の 改 良 隅 田, 貴 久 三 重 大 学, 2011. 三 重 大 学 大 学 院 地 域 イノベーション 学 研 究 科 博 士 前 期 課 程 地 域 イノベーション 学 専 攻 http://hdl.handle.net/10076/12400
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WA WA iodrive P-WA [22] SN CAS CAS SN [10] fetch-and-add [22] TPC-C fetch-and-add TPC-C ARIES[14] WA WA WA ARIES WA Aether[7] Deuteronomy[11][10] [20]
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VHDL-AMS Department of Electrical Engineering, Doshisha University, Tatara, Kyotanabe, Kyoto, Japan TOYOTA Motor Corporation, Susono, Shizuok
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ASAKURA Nobuyuki, Japan Atomic Energy Research Institute, Naka, Ibaraki 311-0193, Japan e-mail: asakuran@fusion.naka.jaeri.go.jp The Plasma Boundary of Magnetic Fusion Devices Naka Fusion Research Establishment,
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1,a) 2,b) 2,c) 1. Web [1][2][3][4] [5] 1 2 a) ito@iplab.cs.tsukuba.ac.jp b) misue@cs.tsukuba.ac.jp c) jiro@cs.tsukuba.ac.jp [6] Lyra[5] ivisdesigner[6] [7] 2 Lyra ivisdesigner c 2012 Information Processing
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1, 2 3 1, 2 Web Fischer Social Creativity 1) Social Creativity CG Network Analysis of an Emergent Massively Collaborative Creation Community Masahiro Hamasaki, 1, 2 Hideaki Takeda 3 and Takuichi Nishimura
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7 7 障害箇所の切り分け 万一 障害が発生した場合は ESMPRO/ServerManagerを使って障害の発生箇所を確認し 障害がハー ドウェアによるものかソフトウェアによるものかを判断します 障害発生個所や内容の確認ができたら 故障した部品の交換やシステム復旧などの処置を行います 障害がハードウェア要因によるものかソフトウェア要因によるものかを判断するには E S M P R O / ServerManagerが便利です
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