I. Nios II Nios II 1 2 3 4 SOPC Builder Nios II Altera Corporation I 1
Nios II 1 4 Nios II Nios II / 1 2004 9 v1.1 Nios II 1.01 2004 5 v1.0 2 2004 12 v1.2 ctl5 2004 9 v1.1 Nios II 1.01 2004 5 v1.0 3 2004 9 v1.1 ctl5 break 2004 5 v1.0 4 2004 9 v1.1 Nios II 1.1 GUI 2004 5 v1.0 I 2 Altera Corporation
1. NII51001-1.0 Nios II Nios II Nios II RISC 32 32 32 32 32 32 64 128 IDE GNU C/C++ Eclipse IDE ISA 150 DMIPS CPU Nios II 1 Nios II Altera Corporation 1 1 2004 9
Nios II Nios II Nios II Nios II IDE Nios II IDE GNU C/C++ Eclipse IDE Nios II IDE Nios II Nios II 1-1 Nios II 1-1. Nios II JTAG SDRAM JTAG Nios II SDRAM ROM Avalon UART 1 2 LCD I/O LCD LED MAC/PHY SRAM CompactFlash 1 2 Altera Corporation 2004 9
Nios II FPGA SDRAM Nios II FPGA 5% Nios II Nios II FPGA Nios II Nios II Altera Corporation 1 3 2004 9
Nios II CPU FPGA FPGA FPGA Nios II 1 Nios II Nios II 1 4 Altera Corporation 2004 9
2 I/O SDRAM Nios II CPU ALU Nios II 2 FPGA Altera Corporation 1 5 2004 9
C SOPC Builder FPGA SOPC Builder GUI HDL SOPC Builder HDL Nios II 1 6 Altera Corporation 2004 9
2. NII51002-1.2 Nios II Nios II ISA ISA Nios II Nios II 2-1 2-1. Nios II Nios II JTAG JTAG r0r31 irq[ 31..0 ] ctl0ctl5 I/O Altera Corporation 2 1 2004 12
JTAG Nios II Nios II Nios II Nios II Nios II Nios II 3 JTAG 2 2 Altera Corporation 2004 12
17 Nios II Nios II 4 SOPC Builder Nios II 32 32 6 Nios II ALU ALU 1 2 ALU 2 1 2 1. Nios II ALU ALU ALU ==!= >= < ALU AND OR NOR XOR ALU 0 31 / ALU / ALU / 2 1 Altera Corporation 2 3 2004 12
mul multi mulxss mulxsu mulxuu div divu Nios II ALU Nios II Custom Instruction User Guide 1 Nios II 32 irq0 irq31 32 IRQ IRQ 2 4 Altera Corporation 2004 12
IRQ ienable PIE 3 PIE 1 irqn ienable n 1 I/O Nios II I/O Nios II Nios II I/O Nios II I/O 3 2-2 Nios II I/O Altera Corporation 2 5 2004 12
I/O 2-2. Nios II I/O Nios II M S Avalon M S Avalon M S Avalon Avalon Harvard Avalon Avalon Avalon Avalon Interface Specification Reference Manual Nios II I/O Nios II 2 6 Altera Corporation 2004 12
Nios II Nios II 32 Avalon 1 Nios II Avalon f MAX 32 Avalon Nios II 2 8 Nios II 32 Avalon 2 Altera Corporation 2 7 2004 12
I/O 4 Avalon 1 1 Nios II 1 / Nios II Avalon Nios II SDRAM Nios II Nios II 2 8 Altera Corporation 2004 12
/ / 1 2K 1 K Nios II ldio stio Avalon I/O Altera Corporation 2 9 2004 12
JTAG 31 17 Nios II 3 CPU JTAG JTAG PC PC JTAG FPGA JTAG FPGA JTAG 2 10 Altera Corporation 2004 12
Nios II JTAG Nios II JTAG Nios II IDE JTAG JTAG FPGA JTAG CPU / JTAG Nios II IDE Flash Programmer JTAG JTAG RAM RAM JTAG Altera Corporation 2 11 2004 12
JTAG JTAG JTAG 2 2 JTAG 2 2. (1) D I D D D D I 2 13 D 2 13 : (1) ID 2 12 Altera Corporation 2004 12
JTAG 2 3 Nios II JTAG 2 3. JTAG (1) 1 : (1) JTAG 2 JTAG A B A B JTAG 2 1 JTAG Altera Corporation 2 13 2004 12
JTAG JTAG JTAG Nios II First Silicon Solutions FS2 www.fs2.com JTAG JTAG 2 14 Altera Corporation 2004 12
1 100% Altera Corporation 2 15 2004 12
JTAG 2 16 Altera Corporation 2004 12
3. NII51003-1.2 Nios II 3 1 3 3 3 5 3 14 3 8 3 9 3 11 3 15 3 16 3 16 3 17 3 23 Nios II Nios II r0 r31 32 32 3-2 3 1 zero r0 0 zero ra r31 call ret C C++ r1 r23 r26 r28 19 et r24bt r25ea r29 ba r30 3 5 Altera Corporation 3 1 2004 12
3 1. Nios II r0 zero 0x00000000 r16 r1 at r17 r2 r18 r3 r19 r4 r20 r5 r21 r6 r22 r7 r23 r8 r24 et (1) r9 r25 bt (2) r10 r26 gp r11 r27 sp r12 r28 fp r13 r29 ea (1) r14 r30 ba (2) r15 r31 ra 3 1 (1) (2) JTAG 3 2 Altera Corporation 2004 12
ctl0 ctl5 6 32 rdctl wrctl 3 5 3 2 3 10 3-2 3 2. 31 2 1 0 ctl0 status U PIE ctl1 estatus EU EPIE ctl2 bstatus BU BPIE ctl3 ienable ctl4 ipending ctl5 cpuid status (ctl0) status Nios II 3 16 3 3 PIE U 2 3 3. PIE U PIE PIE 0 PIE 1ienable U 1 0 Altera Corporation 3 3 2004 12
estatus (ctl1) estatus status EPIE EU 2 3 3 PIE U estatus eret estatus status status 3 8 bstatus (ctl2) bstatus status EPIE BU 2 3 3 3 3 PIE U status bstatus bstatus status 3 7 ienable (ctl3) ienable ienable irp0 irp31 1 1 0 3 8 ipending (ctl4) ipending n 1 irqn ienable ipending 3 4 Altera Corporation 2004 12
cpuid (ctl5) cpuid cpuid cpuid 3 8 Nios II 3 OS OS bt r25 ba r30 bstatus ctl2 U 0 Altera Corporation 3 5 2004 12
et r24bt r25ea r29 ba r30 rdctl wrctl bret eret initd initi U 1 U 0 U 17 Nios II 3 6 Altera Corporation 2004 12
break JTAG U 0 3 14 3-1 3-1. U = = 0 bret U = = 0 eret bret U = = 1 eret eret estatus ctl1 status ctl0 ea r29 estatus ea eret Altera Corporation 3 7 2004 12
U 0 status estatus estatus eret 3 8 3 14 1. status ctl0 estatus ctl1 2. status U 3. status PIE 4. ea r29 5. 3 8 Altera Corporation 2004 12
Nios II 6 32 irq0 irq31 3 status ctl0 PIE 1 irqn ienable ctl3 n 1 PIE 0 ipending ctl4 IRQ IRQ 3-2 ipending ienable PIE Altera Corporation 3 9 2004 12
3-2. ienable ipending PIE 31 0 ienable irq[31..0] irq3... IENABLE2 irq2 IENABLE1 irq1 IENABLE0 irq0 31 0 ipending IPENDING3... IPENDING2 IPENDING1 IPENDING0... PIE ISR ISR PIE ienable ISR PIE estatus ctl1 ea r29 PIE 1 ISR ienable IRQ 3 13 3 10 Altera Corporation 2004 12
trap 3 24 Nios II Nios II 17 Nios II Nios II MMU 3-3 Altera Corporation 3 11 2004 12
3-3. (EPIE == 1)&(ipending!= 0)? ea-4? ea-4 div mul mulxuu? estatus ctl1 EPIE 1 ipending ctl4 ea 4 Nios II trap ea-4 3 24 3 12 Altera Corporation 2004 12
trap estatus ctl1 ea r29 eret et r24 eret 1. estatus ctl1 status ctl0 2. ea r29 ea ea ea4 Altera Corporation 3 13 2004 12
break JTAG JTAG Nios II break JTAG 1. status ctl0 bstatus ctl2 2. status U 3. status PIE 4. ba r30 5. bret bret status ba bt r25 bt 3 14 Altera Corporation 2004 12
Nios II 32 4 Nios II 31 17 Nios II 32 16 32 9 16 0 0x00 r0 Altera Corporation 3 15 2004 12
31 2 G 31 17 Nios II Nios II 3 16 2 Nios II 1. status 0x0 2. 3. 3 16 Altera Corporation 2004 12
status ctl0 zero r0 0x0 status ctl0 Nios II Nios II / Nios II Altera Corporation 3 17 2004 12
3 4 ldw stw ldwio stwio 3 4. ldw stw ldwio stwio ldw stw ldwio stwio ldw stw 32 / I/O ldwio stwio ldwio stwio 32 / ldwio stwio 3 5 3 5. ldb ldbu stb ldh ldhu sth ldbio ldbuio stbio ldhio ldhuio sthio ldb ldbu ldh ldhu ldb ldh 32 ldbu ldhu 32 stb sth I/O io / 3 18 Altera Corporation 2004 12
and or xor nor 3 6 3 6. and or xor nor andi ori xori andhi orhi xorhi add sub mul div divu addi subi muli mulxss mulxuu mulxsu 32 2 3 and or xor 16 32 and or xor 16 16 32 32 2 3 add sub mul 16 32x32 32 mul 64x64 128 Altera Corporation 3 19 2004 12
3 7 3 7. mov movhi movi movui movia mov movi 16 32 movui movhi 16 16 movia 2 1 1 0 C 3 8 3 8. ( / ) cmpeq == cmpne!= cmpge >= cmpgeu >= cmpgt > cmpgtu > cmple <= cmpleu <= cmplt < 3 20 Altera Corporation 2004 12
3 8. ( / ) cmpltu < cmpeqi cmpnei cmpgei cmpgeui cmpgti cmpgtui cmplei cmpleui cmplti cmpltui 16 32 3 9 3 9. rol ror roli sll slli sra srl srai srli rol roli roli ror roli ror C << >> sll slli srl srli sra srai slli srli srai Altera Corporation 3 21 2004 12
Nios II 3 10 3 10. call callr ret jmp br ra ra C ret call callr ret ra jmp jmp C switch 3 11 C ==!= < <= > >= 3 11. bge bgeu bgt bgtu ble bleu blt bltu beq bne 2 3 20 3 22 Altera Corporation 2004 12
3 12 3 12. trap eret break bret rdctl wrctl flushd flushi initd initi flushp sync trap eret call/ret trap status estatus ea eret estatus status ea break bret break bret status 1 custom 2 2 4 Nios II Custom Instruction User Guide C custom Altera Corporation 3 23 2004 12
Nios II nop mul muli mulxss mulxsu mulxuu div divu 3 11 3 24 Altera Corporation 2004 12
NII51004-1.2 4. SOPC Builder Nios II SOPC Builder Nios II Nios II Nios II Nios II Nios II SOPC Builder Nios II Nios II Hardware Development Tutorial Nios II Nios II SOPC Builder Altera Corporation 4 1 2004 12
Nios II Core Nios II Core Nios II Core Nios II Nios II Core 4-1 4-1. Nios II Nios II Core Nios II Core 3 Nios II Nios II/f Nios II/f Nios II/s Nios II/s Nios II/e Nios II/e Nios II/e 4 2 Altera Corporation 2004 12
SOPC Builder Nios II 4 2 4-1 Nios II Core Selector Guide 17 Nios II Nios II Nios II Core Nios II/s Nios II/f LE Hardware Multiply Stratix DSP ALU LE ALU Hardware Divide LE ALU Hardware Divide Altera Corporation 4 3 2004 12
JTAG Debug Module Hardware Multiply Hardware Divide Nios II JTAG Debug Module JTAG Debug Module Nios II JTAG Nios II JTAG 4 1 4 1. JTAG FPGA JTAG CPU / JTAG RAM 2 First Silicon Solutions FS2 4 4 Altera Corporation 2004 12
SOPC Builder Nios II 4-2 JTAG Debug Module 5 4-2. Nios II JTAG Debug Module 4 6 4 2 First Silicon Solutions FS2 FS2 Nios II www.fs2.com Altera Corporation 4 5 2004 12
JTAG Debug Module 4 2. JTAG Level 1 Level 2 Level 3 Level 4 (1) 0 300 400 LE 800 900 LE 2,400 2,700 LE 3,000 3,200 LE 0 2 M4K 2 M4K 4 M4K 4 M4K I/O (2) 0 0 0 0 20 JTAG 0 2 2 4 0 2 2 4 0 64K (3) 64K 0 128K (4) 4 2 (1) Level4 FS2 (2) FPGA JTAG (3) 16 FS2 (4) FS2 3 4 128 64K M4K RAM M4K RAM 128K 4 6 Altera Corporation 2004 12
SOPC Builder Nios II Custom Instructions Custom Instructions Nios II ALU 10 100 4-3 Custom Instructions 4-3. Nios II Custom Instructions Nios II Custom Instruction User Guide Altera Corporation 4 7 2004 12
Custom Instructions 4 8 Altera Corporation 2004 12