(SoC) 2004/6/11 Yukihiro Nakamura e-mail: nakamura@kuee.kyoto-u.ac.jp u.ac.jp
(VLSI) () VLSI
DIPS IBM370 CPU MH MB GB DIPS-11201975 VAIO LSI Sony VAIO CPU MH MB GB Pentium
() ()
V,S.,B Sun Micro Apple Microsoft
NTT NASDAQ() Cisco Systems, Inc. Intel Corporation Dell Computer Corporation WorldCom, Inc. Sun Microsystems, Inc. Oracle Corporation Microsoft Corporation JDS Uniphase Corporation Applied Materials, Inc. Network Appliance, Inc. IT
2000.7.24$1=108.7 2000 NTT () 10 General Electric Cisco Systems Intel Microsoft Exxon Mobil Wal-Mart Stores Citigroup Oracle IBM EMC IT
NTT 11 11 2000 2000 IT 19893 10 NEC () 20007 10 2000.7.2410:40 89.331
(SEMATECH) Logic Tr. / Chip 10M 1M 100K 10K 1K 100 10 1 Logic Tr./Chip Tr. /Staff-Mo 58% /Yr. Compound Complexity Growth rate 1980 1990 2000 2010 Year 21% /Yr. Compound Productivity Growth rate 100M 10M 1M 100K 10K 1K 100 10 Tr. / Staff-Month
DB DB / LSI LSI LSI LSI LSI LSI LSI LSI / / ( ) / / / LSI/MSI/SSI LSI/MSI/SSI / ( )
VLSI 10 7
Deep Submicron Technology SoC 10 7 SoCIT ScCIT()
SFLCPU 18 Data Address 8bit 8bit RR op IF1 EX RX op IF1 M RXE op IF1 M EX 2 2 3 INX, SEC, CLC, ROLA, COMA, INP LDAX, STAX ADCX, ANDX, SUBX RI op imm IF1 IF2 EX 3 LDAI, LDXI XM op adrs IF1 IF2 M 3 LDXM, STXM B op adrs IF1 IF2 B 3 BC, BZ, B
() ()DA(1981
Programming-like Design Method SFL( ) PARTHENON
stage fetch { } stage exec { state exec par{ SFL state fetch1 par { /* word */ op1 := memory.read( pc ).out_data ; pc := inc.inc( pc ).out ; alt{ idec.idec( memory.out_data ).out: goto fetch2 ; else :relay exec. task( ) ; } } state fetch2 par{ /* () */ op2 := memory.read( pc ).out_data ; pc := inc.inc( pc ).out ; goto fetch1 ; relay exec.task( ) ;
Global System Designer CAD IT Information Technology SoC System on-a-chip
SFL/PARTHENON SFL 8bit CPU)( ) (1) SFL (Structured Function description Language) (2) (8bit CPU) (3) SFL ( ) ASIC Mask Pattern netlist () () FPGA FPGA Mapper
SFL Verilog-HDL VHDL UDL/I
1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 SFL Verilog-HDL VHDL UDL/I NTT Cadence IFIP Gateway Synopsys IEEE PARTHENON
SFL SFL Verilog-HDL, VHDL UDL/I
SFL
ITSoC
SoC SpecC, SystemC, Superlog C/C++ IT Information Technology SoC System on-a-chip
PARTHENON s success PARTHENON 32 bit Risc Processor, FDDP Perfect Harmony between Behavioral Language and Logic Synthesis! Number of Instructions Pipelining Number of Gates Performance Pins Chip Size Process Design Effort Foundry 47(subset of DLX) 5-stage pipeline 13,933 gates More than 10 MIPS 172/223 8.76mm8.79mm 1.0m CMOS 44 person-days VLSI Technology Inc. 44 NTT Communication Science Laboratories
PARTHENON s success 155Mbps TCP/IP
PARTHENON s success MPEG Decoder LSI
PARTHENON s success MPEG2/PCI Card
MPEG2 Card
PARTHENON s success Apple CPU6502 () 19947
PARTHENON s success PARTHENON Vector Processor for DSP Systems Perfect Harmony between Behavioral Language and Logic Synthesis! Microcode Pipelining Number of Gates Performance Pins Chip Size Process Design Effort Foundry VLIW type 128bit(2types) 3-stage pipeline3 150Kgates 120 MFLOPS (40MHz) 223 14mm15mm 1.0m CMOS 30 person-months TOSHIBA Corp. NTT Transmission Systems Laboratories
SHD
()) SoC/VLSI /VLSI,
() 4
200012 EMS (Electronics Manufacturing Services) EMCS20014 Engineering, Manufacturing and Customer Services
ATT) 12500 (20023) NEC/WS/ (200110)
Fedex
()(2003) ()
EMS
(1) 49.7 (2)79.3 (3)25.1 (51.4)(20.6) (4)55.1 (22) (19.9) (5) 55.6 (6)
REJECT