Verilog HDL による回路設計記述

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えのほうねん
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1 Verilog HDL / 24

2 ( ) (RTL) (HDL) RTL HDL アルゴリズム動作合成論理合成論理回路配置配線ハードウェア記述言語シミュレーションレイアウト 2 / 24

3 HDL VHDL: IEEE Std Ada IEEE Std Verilog HDL: 1984 IEEE Std C SFL (NTT) UDL/I (JEITA) SpecC, SystemC, SystemVerilog: C, C++ HDL 3 / 24

4 Verilog HDL [1984] IEEE [1995] HDL [1990 ] IEEE [2001] ( Verilog-2001 ) C { } begin end : 4 / 24

5 : 4 adder4.v module adder4 ( input [3:0] a, b, input cin, output [3:0] sum, output cout ); a[3:0] b[3:0] cin {cout, sum} = a + b + cin sum[3:0] cout assign { cout, sum } = a + b + cin ; endmodule module 5 / 24

6 1 0, 1, x, z 4 x: ( ) z: signed ( ) (b,o,h,d) 4 b h0a3f x, z _ 8 bxx10 111x ( ) wire reg FF parameter integer 6 / 24

7 wire: wire data 1 / [n:m] ( ) wire [3:0] data 4 ( ) data 4 data[3:1] 3 reg: ( ) reg [3:0] data [0:255] ( ) data[5] 4 data[5][3:1] 3 wire reg reg input, output, inout wire ( ) output reg 7 / 24

8 C (+,-,*,/,%) (&,,^,~) (?:) / (&&,==,!=,>=, ) Verilog HDL {a, b} 1 &a, a ( ) wire assign function always 8 / 24

9 always always ( ( ) begin end ( ) initial 1 ( ) #n 9 / 24

10 function function [ ] ; endfunction assign always function decode2 4 function [3:0] decode2_4 ; input [1:0] a; begin case (a) 0: decode2_4 = 4 b0001 ; 1: decode2_4 = 4 b0010 ; 2: decode2_4 = 4 b0100 ; default : decode2_4 = 4 b1000 ; endcase end endfunction assign x = decode2_4 ( x_bin ); 10 / 24

11 function always for, while, repeat ( ) if if ( ) begin end else begin end case case (default ) ( if... else if... )? (= z ) don t care casez ( x don t care casex ) case ( ) 1: // 2: default : endcase 11 / 24

12 submodule instantiation wire [7:0] op1, op2, sum ; wire c0, c4, c8; adder4 a0 (.a( op1 [3:0]),.b( op2 [3:0]),. cin (c0),. sum ( sum [3:0]),. cout (c4)); adder4 a1 (.a( op1 [7:4]),.b( op2 [7:4]),. cin (c0),. sum ( sum [7:4]),. cout (c8)); wire reg 12 / 24

13 module structure module ( ); wire/reg ; assign always endmodule assign always wire reg 13 / 24

14 : 4 count4.v module count4 ( input reset, clock, output reg [3:0] data ); reset clock posedge clock or negedge reset ) begin if ( reset == 1 b0) begin data <= 4 b0000 ; end else begin data <= data + 1; end end endmodule reg always data[3:0] 14 / 24

15 always ( ) clock) ( reset==0 ) clock, negedge reset) always always comb ) 15 / 24

16 / (=) wire (<=) reg Blocking A = B; B = A; Nonblocking // A <= B; B <= A; // A B 16 / 24

17 always (function : ) posedge clock ) begin s = x + y + c; end x or y) begin s = x + y + c; end x or y or c) begin s = x + y + c; end begin if ( c ==0) s = x + y; end 17 / 24

18 HDL ( ) RTL : HDL : HDL テストベンチテスト対象テストパタンクロック生成入力波形生成出力を期待値と比較 18 / 24

19 timescale include #n initial 0 1 $monitor test count4.v t i m e s c a l e 1 ns / 1 ns i n c l u d e count4. v module t ; r e g r e s e t, c l o c k ; w i r e [ 3 : 0 ] data ; count4 c1 ( r e s e t, c l o c k, data ) ; a l w a y s b e g i n #10 c l o c k = c l o c k ; end i n i t i a l b e g i n $monitor ( %d %h %h %h, $time, r e s e t, c l o c k, data ) ; r e s e t = 1 ; c l o c k = 0 ; #35 r e s e t = 0 ; #5 r e s e t = 1 ; #200 r e s e t = 0 ; #140 r e s e t = 1 ; #1000 $ f i n i s h ; end endmodule 19 / 24

20 FPGA FPGA ( ) reg reg [3:0] count = 4 b0001; initial reg [3:0] count ; initial begin count <= 4 b0001 ; 20 / 24

21 1/3 RTL wire/reg wire/reg (assign always ) 21 / 24

22 2/3 if else case default 0 signed unsigned unsigned bit unsigned signed unsigned 22 / 24

23 3/3 RTL function 0/1 23 / 24

24 ( ) <ktakagi@i.kyoto-u.ac.jp> 24 / 24

VelilogHDL 回路を「言語」で記述する

VelilogHDL 回路を「言語」で記述する 2. ソースを書く数値表現数値表現形式 : ss'fnn...n ss は, 定数のビット幅を 10 進数で表します f は, 基数を表します b が 2 進,o が 8 進,d が 10 進,h が 16 進 nn...n は, 定数値を表します各基数で許される値を書くこ Verilog ビット幅基数 2 進表現 1'b0 1 2 進 0 4'b0100 4 2 進 0100 4'd4 4