2. EPC4 EPC8 & EPC16 CF52002-2.2 EPC4 EPC8 EPC16 Stratix Cyclone APEX II APEX 20K APEX 20K APEX 20KC APEX 20KE Mercury ACEX 1K FLEX 10KFLEX 10KE FLEX 10KA 4 8 16 / EPC16 EPC4 8 Stratix FPP DCLK 8 FPGA n n = 1 2 4 8 2 ms 100 ms POR 100 MHz 10 MHz 33 MHz 50 MHz 66 MHz Altera Corporation 2 1
100 (PQFP) 88 Ultra FineLine BGA 100 PQFP 3.3 V I/O IEEE std. 1532 ISP Jam STAPL Standard Test and Programming Language ISP JTAG Joint Test Action Group ninit_conf JTAG FPGA ninit_conf ncs OE FPGA FPGA FPGA 2 1 FPGA FPGA PCN0506: Addition of Intel Flash Memory As Source For EPC4, EPC8 & EPC16 Enhanced Configuration Devices Using Intel Flash Memory Based EPC4, EPC8, and EPC16 2 2 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 EPC 3 2 1 EPC 2 1. EPC16 EPC8 Intel (1) Sharp Intel (1) Sharp Intel (1) EPC4 Micron 2 1 (1) PCN0506: Addition of Intel Flash Memory As Source for EPC4, EPC8 & EPC16 Enhanced Configuration Devices EPC4 EPC16 EPC8 3.3 V I/O 2-1 3 FPGA ISP JTAG Nios FPGA ISP Altera Corporation 2 3 Volume 2
2-1. JTAG/ISP Interface Enhanced Configuration Device Flash Shared Flash Interface Controller FPGA Shared Flash Interface (PS) 8 PS FPP 8 FPGA FPGA 8 PGM[2..0] 8 1 2 4 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 Stratix Stratix Stratix Using Remote System Configuration with Stratix & Stratix GX Devices (DCLK) ISP (PORSEL) FPGA FPGA DATA[] POR 0x8000512 32 10 MHz nstatus CONF_DONE FPGA FPGA nstatus High CONF_DONE Low DCLK DATA[] POR PGM[2..0] FPGA Altera Corporation 2 5 Volume 2
FPGA n = 1 2 4 8 n DATA[n] DCLK 4 n = 1 PS n = 2 4 8 2 4 8 PS FPGA DATA 8 DCLK FPGA FPP (n) DATA[n] DATA[] Low FPGA FPGA DCLK DCLK 90 ns 10 MHz 160 Mbps 16 DQ[] 10 MHz FPGA 100 MHz Stratix FPP 800 Mbps 8 DATA[] 100 MHz 160 Mbps Stratix 2 2 320 Mbps 2 6 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 64DCLK FPGA CONF_DONE CONF_DONE CONF_DONE OE Low nstatus Low FPGA CRC (Cyclic Redundancy Check) FPGA nstatus Low FPGA Auto-Restart Configuration After Error FPGA nstatus FPGA FPGA DCLK Low DATA[] High FPP PS FPGA FPGA Altera Corporation 2 7 Volume 2
2 2 FPGA 2 2. FPGA DATA[] DATA[] FPGA DCLK DCLK DCLK FPGA DATA[] ninit_conf nconfig INIT_CONF JTAG FPGA INIT_CONF JTAG ninit_conf nconfig nconfig V CC OE nstatus POR Low OE Low ncs CONF_DONE FPGA 2 8 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 Stratix APEX II FPP FPGA DATA[7..0] DATA[7..0] DCLK 1 Stratix APEX II FPGA DCLK 2-2 FPP ) MSEL FPGA 2-2. FPP V CC (1) V CC (1) Enhanced Configuration Device (6) n N.C. MSEL nceo Stratix Series or APEX II Device DCLK DATA[7..0] nstatus CONF_DONE nconfig nce (3) (3) GND WE#C WE#F RP#C RP#F DCLK DATA[7..0] A[20..0] OE (3) RY/BY# ncs(3) CE# ninit_conf (2) OE# (1) V CC DQ[15..0] WP# BYTE# (5) TM1 VCCW PORSEL PGM[2..0] V CC (1) (4) (4) N.C. N.C. N.C. N.C. N.C. TMO EXCLK (4) GND C-A0 (5) C-A1 (5) C-A15 (5) C-A16 (5) A0-F A1-F A15-F A16-F Altera Corporation 2 9 Volume 2
2-2 (1) V CC (2) ninit_conf ninit_conf/nconfig ninit_conf ninit_conf nconfig V CC (3) OE ncs Quartus II Disable ncs and OE pull-ups on configuration device (4) PORSEL PGM[] EXCLK 2 8 (5) 100 PQFP C-A0 F-A0 C-A1 F-A1 C-A15 F-A15 C-A16 F-A16 BYTE# V CC 100 PQFP 88 Ultra FineLine BGA C-RP# F-RP# C-WE# F-WE# TM1 V CC TM0 GND WP# V CC (6) FPP FPGA MSEL[] FPGA FPP FPGA Stratix / APEX II FPGA FPGA nceo 2 FPGA nce 2 FPGA CONF_DONE FPGA 1 nstatus FPGA / FPP FPGA 2 10 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 Stratix Cyclone APEX II APEX 20KC APEX 20KE APEX 20K FLEX 10K PS FPP FPGA DCLK 1 (DATA[0]) DATA[7..1] Low FPGA PS DATA[0] FPGA DATA0 DATA[7..1] FPP PS FPGA PS FPGA FPGA DATA[n-1..0] n= 1 2 4 8 n DATA[] FPGA Quartus II 1 8 3 4 PS DATA FPGA FPGA DATA DATA[3] 5 6 7 8 PS 2-3 FPGA PS MSEL FPGA Altera Corporation 2 11 Volume 2
2-3. PS FPGA n=8 V CC (1) V CC (1) Enhanced Configuration Device (6) n N.C. MSEL nceo FPGA0 DCLK DATA0 nstatus CONF_DONE nconfig nce (3) (3) WE#C RP#C DCLK DATA0 DATA1 OE (3) ncs (3) WE#F RP#F A[20..0] RY/BY# CE# OE# DQ[15..0] N.C. N.C. N.C. N.C. N.C. (6) n N.C. MSEL nceo GND FPGA1 DCLK DATA0 nstatus CONF_DONE nconfig nce GND (1) V CC ninit_conf (2) DATA 7 WP# BYTE# (5) TM1 VCCW PORSEL PGM[2..0] V CC (1) (4) (4) (6) n N.C. MSEL nceo FPGA7 DCLK DATA0 nstatus CONF_DONE nconfig nce GND GND TMO C-A0 (5) C-A1 (5) C-A15 (5) C-A16 (5) EXCLK A0-F A1-F A15-F A16-F (4) 2-3 (1) V CC (2) ninit_conf ninit_conf/nconfig ninit_conf ninit_conf nconfigv CC (3) OE ncs Quartus II Disable ncs and OE pull-ups on configuration device (4) PORSEL PGM[] EXCLK 2 8 (5) 100 PQFP C-A0 F-A0 C-A1 F-A1 C-A15 F-A15 C-A16 F-A16 BYTE# V CC 100 PQFP 88 Ultra FineLine BGA C-RP# F-RP# C-WE# F-WE# TM1 V CC TM0 GND WP# V CC (6) FPGA MSEL[] PS FPGA 2 12 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 2 3 PS 2 3. PS n = (1) 1 DATA0 DATA[7..1] Low 2 DATA[1..0] DATA[7..2] Low 4 DATA[3..0] DATA[7..4] Low 8 DATA[7..0] - 2 3 (1) DATA FPGA FPGA FPGA Nios Stratix Stratix Using Remote System Configuration with Stratix & Stratix GX Devices Altera Corporation 2 13 Volume 2
FPGA JTAG POR 2 14 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 FPGA/ FPGA nconfig Low nstatus-oe Low Volume 2 Micron EPC4 www.micron.com Micron Flash Memory MT28F400B3 Data Sheet Sharp EPC16 www.sharpsma.com Sharp LHF16J06 Data Sheet Flash Memory Used in EPC16 Devices Intel Advanced Boot Block Flash Memory (B3) 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Datasheet www.intel.com 2-4 FPP Altera Corporation 2 15 Volume 2
2-4. FPP (1) V CC V CC Enhanced Configuration Device PLD or Processor n N.C. MSEL nceo Stratix Series or APEX II Device DCLK DATA[7..0] nstatus CONF_DONE nconfig nce V CC WE#C WE#F RP#C RP#F DCLK DATA[7..0] A[20..0] (2) OE RY/BY# (5) ncs CE# ninit_conf OE# DQ[15..0] V CC WE# RP# A[20..0] RY/BY# CE# OE# DQ[15..0] GND WP# BYTE# (3) TM1 VCCW PORSEL PGM[2..0] (4) (4) TMO EXCLK (4) GND C-A0 (3) C-A1 (3) C-A15 (3) C-A16 (3) A0-F A1-F A15-F A16-F 2-4 (1) EPC8 (2) EPC16 A20 EPC8 A20 A19 EPC4 A20 A19 A18 (3) 100 PQFP C-A0 F-A0 C-A1 F-A1 C-A15 F-A15 C-A16 F-A16 BYTE # V CC 100 PQFP 88 Ultra FineLine BGA C-RP# F- RP# C-WE# F-WE# TM1 V CC TM0 GND WP# V CC (4) PORSEL PGM[] EXCLK 2 8 (5) RY/BY# Sharp EPC8 EPC16 2 16 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 FPGA 8 FPGA 2 Stratix Stratix FPGA Stratix Using Remote System Configuration with Stratix & Stratix GX Devices 3 PGM[2..0] OE High PGM[2..0] nconfig FPGA 0 PGM[2] (MSB) PGM[2..0] PGM[2..0] GND 000 Altera Corporation 2 17 Volume 2
PGM[] - FPGA 3 2 FPGA 2 SRAM.sof 6 SOF PS FPP PS Quartus II Volume 2 FPGA Quartus II EPC4 EPC8 EPC16 7 15 30 M 2 18 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 FPGA 8 FPGA FPP / 66 MHz APEX II FPGA 8 66 MHz = 528 Mbps 10 MHz 90 ns 16 10 MHz = 160 Mbps 50% 16 30 30 10 MHz = 300 Mbps Compression ModeQuartus II Configuration Device Options Stratix II FPGA Cyclone Stratix II FPGA Cyclone Stratix II FPGA Cyclone FPGA FPGA RAM / Altera Corporation 2 19 Volume 2
Stratix 1.9 47% 2 4 Stratix 2 4. Stratix (1) 98% 64% 1.9 2.3 % 47% 57% 2 4 (1) DCLK EXCLK 2 1 N DCLK N 1 16 1.5 2.5 50% 50% 2-5 2 20 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 2-5. Configuration Device Clock Divider Unit External Clock (Up to 100 MHz) 10 MHz 33 MHz 50 MHz 66 MHz Divide by N DCLK Internal Oscillator DCLK FPGA DCLK FPGA DCLK FPGA 4 2 5 10 MHz 33 MHz 50 MHz 66 MHz 2 5. (MHz) (MHz) (MHz) 10 6.4 8.0 10.0 33 21.0 26.5 33.0 50 32.0 40.0 50.0 66 42.0 53.0 66.0 Altera Corporation 2 21 Volume 2
(N) Quartus II Device Settings Convert Programming Files Configuration Device Options (EXCLK) 1 10 MHz Volume 2 ISP JTAG JTAG FPGA 100,000 JTAG IEEE Std. 1149.1 JTAG ISP IEEE Std. 1532 2.0 JTAG ISP 10 MHz JTAG TCK 2 22 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 JTAG ISP JTAG JTAG (PENDCFG) FPGA nconfig ninit_conf FPGA JTAG ISP FPGA/ ninit_conf JTAG ninit_conf FPGA Programmer options Options Initiate configuration after programming Quartus II 16 FPGA (UART Ethernet PCI ) / Micron EPC4 www.micron.com Micron Flash Memory MT28F400B3 Data Sheet Sharp EPC16 www.sharpsma.com Sharp LHF16J06 Data Sheet Flash Memory Used in EPC16 Devices Intel Advanced Boot Block Flash Memory (B3) 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Datasheet www.intel.com Altera Corporation 2 23 Volume 2
JTAG ISP FPGA nconfiglow nstatus-oe Low FPGA nconfig Low 2 6 2 8 JTAG 2 6. (1/2) DATA[7..0] DATA DCLK DATA DCLK FPGA DCLK DCLK FPGA DATA FPGA DCLK ncs ncs FPGA FPGA CONF_DONE FPGA nconfig ncs OE Low Disable ncs and OE pull-ups on configuration device Quartus II / 2 24 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 2 6. (2/2) ninit_conf OE ninit_conf JTAG FPGA nconfig ninit_conf ninit_conf nconfig V CC POR Low 2 ms 100 ms OE POR OE Low OE FPGA nstatus OE FPGA nstatus-oe High Disable ncs and OE pull-ups on configuration device Quartus II / Altera Corporation 2 25 Volume 2
2 7. (1/3) A[20..0] 100 PQFP 4 A0 A1 A15 A16 C-A[] F-A[] 88 Ultra FineLine BGA EPC16 A20 EPC8 A20 A19 EPC4 A20 A19 A18 DQ[15..0] DQ[15..0] DQ[15..0] CE# Low High 2 26 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 2 7. (2/3) RP# (1) Low High Low C-RP# F-RP# RP# OE# Low WE# (1) Low WE# C-WE# F-WE# WE# WP# V CC / V CC Quartus II V CC VCCW 3.3 V V CC Altera Corporation 2 27 Volume 2
2 7. (3/3) RY/BY# RY/BY# Sharp EPC8 EPC16 (2) BYTE# 100 PQFP 16 V CC 2 7 (1) 12 V 12 V 2 2 PCB C-WE# F-WE# (2) PCN0506: Addition of Intel Flash Memory As Source For EPC4, EPC8 & EPC16 Enhanced Configuration Devices Using Intel Flash Memory Based EPC4, EPC8 and EPC16 2 8. JTAG (1/2) TDI JTAG JTAG V CC TDO JTAG JTAG TCK JTAG JTAG GND TMS JTAG JTAG V CC 2 28 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 2 8. JTAG (2/2) PGM[2..0] 3 8 1 FPGA POF Quartus II PGM[2] MSB 0 PGM[2..0]=000 EXCLK DCLK High Low PORSEL 2 ms 100 ms POR PORSEL Low POR 100 ms PORSEL High POR 2 ms TM0 GND TM1 V CC POR POR V CC POR POR POR OE POR OE Low POR JTAG ISP POR POR 100 ms POR 2 ms PORSEL POR High 2 ms Low 100 ms Altera Corporation 2 29 Volume 2
POR V CC V CC V CC FPGA nstatus Low FPGA CRC FPGA nconfig OE FPGA CONF_DONE Low POR FPGA V CCINT CONF_DONE Low OE High FPGA EEPC POR CONF_DONE High POR OE High OE ncs CONF_DONE High DATA DCLK PORFPGA POR 2 POR PORSEL High 2 ms PORSEL Low 100 ms FPGA 100 ms 2 30 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 FPGA nconfig Low Quartus II EPC4 EPC8 EPC16 POF Stratix Cyclone APEX II APEX20K Mercury ACEX 1K FLEX 10K FPGA SOF 1 4 JTAG ISP FPGA JTAG INIT_CONF 2 9FPGA ISP IEEE Std. 1532 IEEE Std.1532 ISP 2 9. JTAG (1/3) (1) JTAG OPCODE SAMPLE/PRELOAD 00 0101 0101 EXTEST 00 0000 0000 Altera Corporation 2 31 Volume 2
2 9. JTAG (2/3) (1) JTAG OPCODE BYPASS 11 1111 1111 TDI TDO 1 BST IDCODE 00 0101 1001 IDCODE TDI TDO IDCODE TDO IDCODE 0100A0DDh USERCODE 00 0111 1001 USERCODE TDI TDO USERCODE TDO 32 USERCODE INIT_CONF 00 0110 0001 FPGA nconfig ninit_conf Low FPGA JTAG Run-Test/Idle ninit_conf Low ninit_conf nconfig JTAG Run-Test/Idle High nconfig High FPGA FPGA ISP Programmer options Options Initiate configuration after programming Quartus II (POF JAM JBC) 2 32 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 2 9. JTAG (3/3) (1) JTAG OPCODE PENDCFG 00 0110 0101 JTAG ISP ninit_conf Low FPGA/ FPGA/ nconfig FPGA/ ninit_conf FPGA INIT_CONF JTAG ninit_conf 2 9 (1) 10 174 JTAG BDSL (POF) Quartus II Convert Programming Files Intel HEX.hexout Quartus II (APU) 2 10 2 10. (1/2) EPC16 88 Ultra FineLine BGA PLMUEPC-88 100 PQFP PLMQEPC-100 Altera Corporation 2 33 Volume 2
IEEE Std. 1149.1 (JTAG) 2 10. (2/2) EPC8 100 PQFP PLMQEPC-100 EPC4 100 PQFP PLMQEPC-100 IEEE Std. 1149.1 (JTAG) IEEE Std.1149.1-1990 JTAG BST JTAG 2-6 JTAG 2-6. JTAG TMS TDI t JCP t JCH t JCL tjpsu t JPH TCK t JPZX t JPCO t JPXZ TDO Signal to be Captured Signal to be Driven t JSZX t JSSU t JSH t JSCO t JSXZ 2 11 2 11. JTAG (1/2) t JCP TCK 100 ns t JCH TCK High 50 ns t JCL TCK Low 50 ns 2 34 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 2 11. JTAG (2/2) t JPSU JTAG 20 ns t JPH JTAG 45 ns t JPCO JTAG Clock-to-Output 25 ns t JPZX JTAG 25 ns t JPXZ JTAG 25 ns t JSSU 20 ns t JSH 45 ns t JSCO Clock-to-Output 25 ns t JSZX t JSXZ 25 ns 25 ns 2-7 2-7. ninit_conf or VCC/nCONFIG t LOE OE/nSTATUS ncs/conf_done DCLK DATA Driven High t CE bit/byte 1 t HC t LC bit/byte bit/byte 2 n (1) (2) User I/O t OE Tri-State Tri-State User Mode INIT_DONE 2-7 (1) DCLK Low (2) DATA[] High Altera Corporation 2 35 Volume 2
2 12 www.altera.co.jp Micron EPC4 Micron MT28F400B3 Data Sheet Flash Memory Used in EPC4 Devices Sharp EPC16 Sharp LHF16J06 Data Sheet Flash Memory Used in EPC16 Devices Intel EPC4 EPC16 Intel Flash 28F016B3 2 12. (1/2) f DCLK DCLK 40% 66.7 MHz t DCLK DCLK 15 ns t HC DCLK High 40% 6 ns t LC DCLK Low 40% 6 ns t CE OE DCLK 40 ns t OE OE DATA 40 ns t OH DCLK DATA (1) ns t CF (2) OE DCLK 277 ns t DF (2) OE DATA 277 ns t RE (3) DCLK OE 60 ns t LOE OE 60 ns f ECLK EXCLK 40% 100 MHz t ECLK EXCLK 10 ns t ECLKH EXCLKHigh 40% 4 ns 2 36 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 2 12. (2/2) t ECLKL EXCLKLow 40% 4 ns t ECLKR EXCLK 100 MHz 3 ns t ECLKF EXCLK 100 MHz 3 ns t POR (4) POR 2 ms 1 2 3 ms 100 ms 70 100 120 ms 2 12 (1) t OH t OH = 0.5 (DCLK ) - 2.5 ns (2) FPGA CRC (3) CONF_DONE (4) FPGA V CCINT 2 ms POR 1 ms 100 ms POR 70 ms 2 13 2 17 DC 2 13. V CC GND -0.2 4.6 V V I DC GND -0.5 3.6 V I MAX DC V CC 100 ma I OUT DC -25 25 ma P D 360 mw T STG -65 150 C T AMB -65 135 C T J 135 C Altera Corporation 2 37 Volume 2
2 14. V CC 3.3V 3.0 3.6 V V I GND 0.3 V CC + 0.3 V V O 0 V CC V T A 0 70 C 40 85 C T R 20 ns T F 20 ns 2 15. DC V CC 3.0 3.3 3.6 V V IH High 2.0 V CC + 0.3 V V IL Low 0.8 V V OH 3.3 V TTL High I OH = 4 ma 2.4 V 3.3 V COMS High I OH = 0.1 ma V CC 0.2 V V OL Low TTL I OL = 4 ma DC 0.45 V Low CMOS I OL = 0.1 ma DC 0.2 V I I V I = V CC I OZ V O = V CC R CONF OE ncs ninit CONF 10 10 µa 10 10 µa 6 kω 2 38 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 2 16. I CC I CC0 50 150 µa I CC1 V CC 60 90 ma I CCW V CCW (1) (1) 2 16 (1) V CCW www.altera.co.jp 2 17. CIN 10 pf COUT 10 pf EPC16 88 Ultra FineLine BGA 100 PQFP 0.8 mm Ultra FineLine BGA PCB EPC8 EPC4 100 PQFP 100 PQFP 2-8 88 Ultra FineLine BGA PCB Gerber Altera Corporation 2 39 Volume 2
2-8. 88 Ultra FineLine BGA PCB (1) NC VCC A20 A11 A15 A14 A13 A12 GND DCLK DATA7 NC OE C-WE# (2) A16 A8 A10 A9 DQ15 PGM0 DQ14 DQ7 DATA5 DATA6 TCK F-WE# (2) RY/BY# (4) ninit CONF PGM1 DQ13 DQ6 DQ4 DQ5 DATA4 TDI GND (5) F-RP# (2) TM1 VCC DQ12 C-RP# (2) VCC VCC DATA3 TDO WP# (3) VCCW A19 DQ11 VCC DQ10 DQ2 DQ3 DATA2 TMS NC NC PGM2 PORSEL DQ9 DQ8 DQ0 DQ1 DATA1 VCC ncs A18 A17 A7 A6 A3 A2 A1 VCC GND DATA0 NC GND EXCLK A5 A4 A0 CE# GND OE# TM0 GND NC 2-8 (1) WP# WE# RP# (2) F-RP# F-WE# C-RP# C-WE# C-WE# F-WE# PCB F-RP# C-RP# PCB (3) WP# High (3.3 V) Quartus II (4) RY/BY# Sharp (5) D3 Intel EPC16 NC 2 40 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 100 PQFP Sharp EPC16 EPC8 100 PQFP Micron EPC4 Intel EPC16 EPC8 EPC4 2-9 100 PQFP PCB Altera Corporation 2 41 Volume 2
2-9. 100 PQFP PCB (1) (2) 0.65-mm Pad Pitch 0.325 mm 19.3 mm 0.410 mm 25.3 mm 2.4 mm 0.5 1.5 1.0 2.0 mm 2-9 (1) 0.5 mm (2) 0.3 mm 2 42 Altera Corporation Volume 2
EPC4 EPC8 & EPC16 www.altera.co.jp 2 18 EPC4 EPC8 EPC16 2 18. EPC4 100 PQFP EPC4QC100 EPC4 100 PQFP EPC4QI100 EPC8 100 PQFP EPC8QC100 EPC8 100 PQFP EPC8QI100 EPC16 100 PQFP EPC16QC100 EPC16 100 PQFP EPC16QI100 EPC16 88 UBGA EPC16UC88 Altera Corporation 2 43 Volume 2
2 44 Altera Corporation Volume 2