SH7734 R01AN0667JJ0100 Rev.1.00 SH7734 SH7734 SH7734 R01AN0665JJ SH7734 SH7734 SH7734 R01AN0665JJ SH7734 R01AN0667JJ0100 Rev.1.00 Page 1 of 55
SH7734 1.... 4 1.1... 4 1.2... 4 1.3... 5 1.3.1 ROM... 5 1.3.2... 6 1.3.3... 6 1.3.4... 7 2.... 8 3.... 8 4.... 9 4.1... 9 5.... 10 5.1... 10 5.2... 11 6.... 12 6.1... 12 6.2... 12 6.2.1... 12 6.2.2... 13 7. RSPI... 14 7.1... 14 7.1.1... 14 7.1.2... 15 7.1.3 SPI... 15 7.2... 16 7.3... 17 7.4... 19 7.5... 20 7.6... 23 8.... 26 8.1... 26 8.1.1... 26 8.2... 28 8.3... 29 8.4 appinfo... 30 9.... 32 9.1... 32 9.1.1... 32 9.1.2... 33 9.2... 34 9.3... 35 9.4... 37 9.5... 38 9.6... 41 9.7... 45 R01AN0667JJ0100 Rev.1.00 Page 2 of 55
SH7734 10.... 46 10.1... 46 10.1.1... 46 10.1.2... 47 10.1.3... 48 10.1.4... 49 10.2 PC BREAKPOINT... 51 10.3 Quad-SPI... 52 10.3.1... 52 10.3.2 Quad-SPI... 52 10.3.3 Quad-SPI... 54 11.... 55 12.... 55 R01AN0667JJ0100 Rev.1.00 Page 3 of 55
SH7734 1. RSPI Quad-SPI 10.3 1.1 1.1 RSPI Quad-SPI HPB-DMAC Single Single/Dual/Quad-SPI HPB Peripheral RSPI or Quad-SPI DDR2/3-SDRAM DMA 1.2 1.2 1.2 ROM IL CPU ROM DDR2/3-SDRAM 16K R01AN0667JJ0100 Rev.1.00 Page 4 of 55
SH7734 1.3 ROM 1.3.1 ROM LSI ROM RSPI IL 1.1 ROM ROM Quad-SPI 1.1 ROM R01AN0667JJ0100 Rev.1.00 Page 5 of 55
SH7734 1.3.2 RSPI DDR2/3-SDRAM 1.2 7 RSPI SH7734 ROM ROM RSPI (8) 16KB H'E520 0000 H'E520 3FFF (6) IL 16KB (7) (9) DDR2/3-SDRAM DDR2/3-SDRAM (10) 1.2 Quad-SPI 10.3 1.3.3 SH7734 SH7734 R01AN0665JJPC 8 R01AN0667JJ0100 Rev.1.00 Page 6 of 55
SH7734 1.3.4 IL DDR2/3-SDRAM OL IL DDR2-SDRAM 1.3 9 1.3 R01AN0667JJ0100 Rev.1.00 Page 7 of 55
SH7734 2. 2.1 SH7734 R8A77343 EXTAL : 33.3333MHz CPU clki400mhz SHwy clks200mhz SHwy clks1100mhz DDR MCK0/MCK0#/MCK1/MCK1#200MHz clkb50mhz clkp50mhz IO supply power 3.3V Core supply power 1.25V High-performance Embedded Workshop (Version 4.09.00.007) C C/C++ Compiler Package for SuperH Family (9.4.0.0) -cpu=sh4a -endian=little -include="$(projdir) inc" -object="$(configdir) $(FILELEAF).obj" -debug -gbr=auto -chgincpath -errorpath -global_volatile=0 -opt_range=all -infinite_loop=0 -del_vacant_loop=0 -struct_alloc=1 -nologo MD19=0,MD14=0,MD18=0,MD17=1,MD16=1 Ver 1.00 SH7734 R0P7734C00000RZ 29 MMU 128Mbit On-board QSPI Flash ROM N25Q128A13TSF40F ( Numonyx ) High-Speed Read H 0B H 0B 3. SH7734 SH7734 R01AN0665JJ R01AN0667JJ0100 Rev.1.00 Page 8 of 55
SH7734 4. RSPI Quad-SPI SH7734 R01UH0233JJ 4.1 PRESET#=L SH7734 R01UH0233JJ SH7734 PRESET#=H 16K IL IL R01AN0667JJ0100 Rev.1.00 Page 9 of 55
SH7734 5. 5.1 5.1 QSPI Flash ROM RSPI Quad-SPI Quad-SPI Quad-SPI 5.1 RSPI SH7734 R0P7734C00000RZ SH7734 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V QSPI Flash ROM N25Q128A13TSF40F 128Mbit GP-1-28/RSPI_RSPCK_A//QSPCLK_A C GP-1-29/RSPI_SSL#_A/QSSL_A S# GP-1-5/RSPI_MOSI_A/QMO/QIO0_A DQ0 MD19 MD14 GP-1-6/RSPI_MISO_A/QMI/QIO1_A DQ1 MD18 GP-1-30/QIO2_A W#/Vpp/DQ2 3.3V MD17 GP-1-4/QIO3_A HOLD#/DQ3 3.3V MD16 5.1 SH7734 R0P7734C00000RZ QSPI Flash ROM N25Q128A13TSF40F Single/Dual/Quad-SPI DQ0 DQ1 RSPI Quad-SPI DQ2 DQ3 Quad-SPI R01AN0667JJ0100 Rev.1.00 Page 10 of 55
SH7734 5.2 5.1 RSPI 5.2 Quad-SPI 5.1 RSPI RSPI_SSL#_A 1 RSPI_RSPCK_A 1 RSPI_MOSI_A 1 RSPI_MISO_A 1 1 5.2 Quad-SPI QSSL#_A 2 QSPCLK_A 2 QMO/QIO0_A 3 / 0 2 4 QMI/QIO1_A 3 / 1 2 4 QIO2_A 2 2 4 QIO3_A 3 2 4 2 Quad-SPI 3 Single-SPI QMO/QMI Dual/Quad-SPI QIO0/QIO1 4 CMD QMO QIO0_A QIO1_A QIO2_A QIO3_A R01AN0667JJ0100 Rev.1.00 Page 11 of 55
SH7734 6. 6.1 6.1 3 6.1 6.1 sh7734_sflash_loader_prog 7 RSPI sh7734_sflash_app sh7734_sflash_downloader [sh7734_sflash_downloader] [sh7734_sflash_loader_prog] 8 9 6.2 6.2.1 (1) 789 SH7734 SH7734 R01AN0665JJ / (2) DDR2/3-SDRAM DDR2-SDRAM DDR2-SDRAM R01AN0667JJ0100 Rev.1.00 Page 12 of 55
SH7734 6.2.2 (1) 6.2 6.2 appinfo appinfo DDR2-SDRAM 7.6 appinfo C,D appinfo R01AN0667JJ0100 Rev.1.00 Page 13 of 55
SH7734 7. RSPI 7.1 DDR2-SDRAM 7.1.1 7.1 7.1 1. H'E520 0000 H'E520 3FFF 2. RSTHandler H'E520 0000 3. P,C,B PINTHandler PIntPRG VECTTBL INTTBL RSTHandler 4. H'E520 3C00 H'E520 3FFF 7.1 RSPI R01AN0667JJ0100 Rev.1.00 Page 14 of 55
SH7734 7.1.2 7.1 SH7734 SH7734 R01AN0665JJ 7.1 H E520 0000 RSTHandler IL PResetPRG P_DBSC3 DBSC3 PnonCACHE P$PSEC PINTHandler / PIntPRG P C C$BSEC C$DSEC D ( ) VECTTBL INTTBL B R H E520 3C00 IL S 7.1.3 SPI 7.2RSPI SPI 7.2 RSPI SPI SPI SPI 3 CPOL=1, CPHA=1 12.5MHz R01AN0667JJ0100 Rev.1.00 Page 15 of 55
SH7734 7.2 7.3RSPI 7.3 RSPI sh7734_main_lp.c RSPI dbsct_lp.c SH7734 R01AN0665JJ dbsct.c RSPI r_rspi_lp.c RSPI r_wdt_lp.c WDT WDT r_rspi_lp.h RSPI r_wdt_lp.h WDT vhandler_lp.src SH7734 R01AN0665JJ vhandler.src RSTHandlerTLB VBR+H 400 VBR+H 100 TLB VBR+H 400 XXX_lp.c R01AN0667JJ0100 Rev.1.00 Page 16 of 55
SH7734 7.3 7.4RSPI 7.4 RSPI SF_PAGE_SIZE 256 r_rspi_lp.h 1 256 B * 1 SF_SECTOR_SIZE H 10000 r_rspi_lp.h 1 64 KB) * 1 SFLASHCMD_CHIP_ERASE H C7 r_rspi_lp.c Bulk Erase * 1 SFLASHCMD_SECTOR_ER ASE H D8 r_rspi_lp.c Sector Erase * 1 SFLASHCMD_BYTE_PROG RAM H 02 r_rspi_lp.c Page Program * 1 SFLASHCMD_BYTE_READ H 0B r_rspi_lp.c Read Data Bytes at Higher Speed * 1 SFLASHCMD_BYTE_READ_ LOW H 03 r_rspi_lp.c Read Data Bytes * 1 SFLASHCMD_WRITE_ENAB LE SFLASHCMD_WRITE_DISA BLE SFLASHCMD_READ_STAT US SFLASHCMD_WRITE_STAT US H 06 r_rspi_lp.c Write Enable * 1 H 04 r_rspi_lp.c Write Disable * 1 H 05 r_rspi_lp.c Read Status Register * 1 H 01 r_rspi_lp.c Write Status Register * 1 D_SFLASH_MOD_SEL_SET H 01000000 r_rspi_lp.c MOD_SEL GroupA RSPI D_SFLASH_IPSR2_SET_INI T D_SFLASH_IPSR2_SET_SF LASH D_SFLASH_GPSR1_SET_S FLASH H 007E07E0 r_rspi_lp.c IPSR2 RSPI_RSPCK_A,RSPI_SSL#_A,RSPI_MOSI_A,RS PI_MISO_A H 00120120 r_rspi_lp.c IPSR2 RSPI_RSPCK_A,RSPI_SSL#_A,RSPI_MOSI_A,RS PI_MISO_A H 30000060 r_rspi_lp.c GPSR1 RSPI_RSPCK_A,RSPI_SSL#_A,RSPI_MOSI_A,RS PI_MISO_A GPIO D_SFLASH_MSTPCR1_SET H 00000800 r_rspi_lp.c MSTPCR1 HPB-DMAC R01AN0667JJ0100 Rev.1.00 Page 17 of 55
SH7734 D_SFLASH_DMAC_DPTR27 _INIT D_SFLASH_DMAC_DCR27_ INIT_LITTLE D_SFLASH_DMAC_DCMDR 27_START D_SFLASH_DMAC_HSRST R_SET_RESET H 00000200 r_rspi_lp.c DPTR27 RSPI HPB-DMAC H 06A02100 r_rspi_lp.c DCR27 H 00000001 r_rspi_lp.c DCMDR27 HPB-DMAC H 00000001 r_rspi_lp.c HSRSTR HPB-DMAC SF_USE_DMAC r_rspi_lp.c #ifdef CPU HPB-DMAC HPB-DMAC RSPI HPB-DMAC D_WDT_WDTBST_INIT H 55000000 r_wdt_lp.c WDTBST D_WDT_WDTBST H 5500C350 r_wdt_lp.c WDTBST 1ms clkp=50mhz D_WDT_WDTST_INIT H 5A000000 r_wdt_lp.c WDTST D_WDT_WDTST H 5A0003E8 r_wdt_lp.c WDTST WDTBST 1ms 1000 1s D_WDT_WDTCSR_START H A50000C0 r_wdt_lp.c WDTCSR D_WDT_WDTCSR_STOP H A5000000 r_wdt_lp.c WDTCSR APROG_TOP_SFLASH H 00004000 sh7734_main_lp.c APPINFO_TOP APPINFO_END APROG_TOP_SFLA SH APROG_TOP_SFLA SH + 4 sh7734_main_lp.c sh7734_main_lp.c *1 R01AN0667JJ0100 Rev.1.00 Page 18 of 55
SH7734 7.4 7.5RSPI 7.5 RSPI main get_appinfo app_prog_transfer jmp_app_prog R_WDT_Start R_WDT_RegisterInit1 R_WDT_RegisterInit2 R_RSPI_SFInitSerialFlash R_RSPI_SFByteRead R_RSPI_SFByteReadLong RSPI appinfo RSPI RSPI 1 RSPI 4 R01AN0667JJ0100 Rev.1.00 Page 19 of 55
SH7734 7.5 main RSPI r_rspi_lp.h void main(void) DDR2-SDRAM LED4 get_appinfo appinfo r_rspi_lp.h static void get_appinfo(uint32_t *app_top_addr, uint32_t *app_end_addr) appinfo appinfo 7.6 uint32_t *app_top_addr uint32_t *app_end_addr DDR2-SDRAM DDR2-SDRAM app_prog_transfer r_rspi_lp.h static void app_prog_transfer(const uint32_t app_top_addr, const uint32_t app_end_addr) uint32_t app_top_addr uint32_t app_end_addr DDR2-SDRAM DDR2-SDRAM R01AN0667JJ0100 Rev.1.00 Page 20 of 55
SH7734 jmp_app_prog r_rspi_lp.h void jmp_app_prog (uint32_t app_top_addr) uint32_t app_top_addr R_WDT_Start r_wdt_lp.h void R_WDT_Start(void) 1s 10ms TMU R_WDT_RegisterInit1 r_wdt_lp.h void R_WDT_RegisterInit1(void) R_WDT_RegisterInit2 2 r_wdt_lp.h void R_WDT_RegisterInit2(void) R_RSPI_SFInitSerialFlash RSPI r_rspi_lp.h void R_RSPI_SFInitSerialFlash(void) RSPI RSPI R01AN0667JJ0100 Rev.1.00 Page 21 of 55
SH7734 R_RSPI_SFByteRead RSPI 1 r_rspi_lp.h void R_RSPI_SFByteRead(const uint32_t addr, uint8_t *buf, const uint32_t size) 1 SPCMD SPB[0:3] 8 uint32_t addr uint8_t *buf uint32_t size 1 R_RSPI_SFByteReadLong RSPI 4 r_rspi_lp.h void R_RSPI_SFByteReadLong(const uint32_t addr, uint32_t *buf, const uint32_t size) 4 SPCMD SPB[0:3] 32 size 1 4 16 16 uint32_t addr uint8_t *buf uint32_t size 1 R01AN0667JJ0100 Rev.1.00 Page 22 of 55
SH7734 7.6 7.2RSPI 7.2 RSPI R01AN0667JJ0100 Rev.1.00 Page 23 of 55
SH7734 (1) SH7734 SH7734 CPG DBSC3 FPSCR VBR SR SH7734 SH7734 SH7734 R01AN0665JJ (2) LED4 LED4 (3) 1s 10ms TMU TMU (4) appinfo DDR2-SDRAM appinfo 7.6 H'0000 4000 H'0000 4007 7.7 H'0000 4008 H'0000 400B 7.6 appinfo DAPPINFO H'0000 4000 H 0C000000 4 H'0000 4004 H 0C000000 4 7.7 VECTTBL H'0000 4008 PowerON_Reset() 4 7.3appinfo appinfo 8.4 R01AN0667JJ0100 Rev.1.00 Page 24 of 55
SH7734 7.3 (5) DDR2-SDRAM CPU DDR2-SDRAM HPB-DMAC (6) LED4 LED5 LED4 LED5 (7) 7.7 PowerON_Reset() 8.1.1 R01AN0667JJ0100 Rev.1.00 Page 25 of 55
SH7734 8. 8.1 appinfo 8.1.1 SH7734 SH7734 R01AN0665JJ 8.1 8.1 H 0C00 0000 DAPPINFO appinfo * 3 DDR2-SDRAM * 1 H 0C00 0008 DDR2-SDRAM * 1 VECTTBL * 4 * 7 INTTBL * 5 * 7 PResetPRG PINTHandler * 5 / * 6 PIntPRG * 5 * 6 P$PSEC P C C$BSEC C$DSEC D * 5 ( ) PnonCACHE * 5 * 8 H 0F00 0000 B DDR2-SDRAM R * 5 * 2 H 0FFF F9F0 DDR2-SDRAM S * 2 H 8FFF FDF0 DDR2-SDRAM * 2 H E501 0000 OL H E520 0000 IL SP_S TLB INTTBL_OL * 5 * 7 PINTHandler_IL * 5 / * 6 PIntPRG_IL * 5 * 6 PnonCACHE_IL * 5 * 8 R01AN0667JJ0100 Rev.1.00 Page 26 of 55
SH7734 *1 *2 *3 *4 *5 *6 *7 *8 DDR2-SDRAM 8.4 appinfo VECTTBL PowerON_Reset() DAPPINFO VECTTBL High-performance Embedded Workshop ROM RAM 8.2 InitSct() 8.2 ROM* RAM IL IL OL OL PnonCACHE IL PnonCACHE_IL 8.2 ROM RAM ROM * RAM D R INTTBL INTTBL_OL PIntPRG PIntPRG_IL PINTHandler PINTHandler_IL PnonCACHE PnonCACHE_IL SH7734 SH7734 R01AN0665JJ NOR ROM DDR2-SDRAM/IL /OL RAM DDR2-SDRAM IL ROM * DDR2-SDRAM RAM IL /OL R01AN0667JJ0100 Rev.1.00 Page 27 of 55
SH7734 8.2 8.3 8.3 sh7734_main.c SH7734 R01AN0665JJ dbsct.c SH7734 R01AN0665JJ vhandler.src SH7734 R01AN0665JJ R01AN0667JJ0100 Rev.1.00 Page 28 of 55
SH7734 8.3 SH7734 SH7734 R01AN0665JJ PC 8.1 resetprg.c / PowerON_Reset sh7734_main.c / main PowerON_Reset 1 VBR PC SCIF3 2 ( _INIT_IOLIB ) SR SCIF3 115200bps 1 main PC "SH7734 Serial Flash Boot Sample Program. Ver.1.00.00 Copyright (C) 2012 Renesas Electronics Corp. All Rights Reserved" (1),(2) 1)(2) 8.1 R01AN0667JJ0100 Rev.1.00 Page 29 of 55
SH7734 (1) PowerON_Reset PowerON_Reset _RESET_Vectors 8.4 8.4 vecttbl.src VECTTBL _RESET_Vectors PowerON_Reset (2) dbsct.c InitSct SH7734 SH7734 R01AN0665JJ InitSct DDR2-SDRAM main DDR2-SDRAM 8.4 appinfo 8.5appinfo sectop secend DAPPINFO app_top app_end 8.5 appinfo appinfo.c appinfo void *app_top sectop("dappinfo") void *app_end secend("pnoncache ") 1 DAPPINFO 16K 8.2appinfo R01AN0667JJ0100 Rev.1.00 Page 30 of 55
SH7734 8.2 appinfo R01AN0667JJ0100 Rev.1.00 Page 31 of 55
SH7734 9. 9.1 9.1.1 OL IL DDR2-SDRAM 9.1 IL H'E520 0000 H'E520 3FFF H'0000 0000 *.abs OL H'E500 E000 H'0000 3FFF H'0000 4000 *.abs H'E501 1FFF *.abs DDR2-SDRAM H'0C00 0000 9.1 1 R01AN0667JJ0100 Rev.1.00 Page 32 of 55
SH7734 H'0000 0000 H'0000 3FFF H'0000 4000 9.2 IL H'E520 0000 *.abs OL H'E520 3FFF H'E500 E000 H'0000 0000 H'0000 3FFF H'0000 4000 *.abs H'E501 1FFF *.abs DDR2-SDRAM H'0C00 0000 9.2 2 OL IL DDR2-SDRAM DDR2-SDRAM 9.1.2 9.1 SH7734 SH7734 R01AN0665JJ 9.1 H E500 E000 PResetPRG OL PnonCACHE P_DBSC3 DBSC3 P$PSEC P C$BSEC C$DSEC C D ( ) B R H E501 1C00 OL S R01AN0667JJ0100 Rev.1.00 Page 33 of 55
SH7734 9.2 9.2 9.2 sh7734_main_dl.c dbsct_dl.c SH7734 R01AN0665JJ dbsct.c r_rspi_dl.c RSPI 7.3 RSPI resetprg_dl.c r_rspi_dl.h RSPI 7.3 RSPI XXX_dl.c R01AN0667JJ0100 Rev.1.00 Page 34 of 55
SH7734 9.3 9.3 7.3 RSPI 9.3 SF_REQ_PROTECT 0 r_rspi_dl.h SF_REQ_UNPROTECT 1 r_rspi_dl.h UNPROTECT_WR_STA TUS H 00 r_rspi_dl.c * 1 PROTECT_WR_STATUS H 5C r_rspi_dl.c * 1 SF_SECTOR_SIZE H 10000 sh7734_main_dl.c 1 64 KB) * 1 SECTOR_NUM 256 sh7734_main_dl.c * 1 DEVICE_SIZE SECTOR_SIZE SECTOR_NUM sh7734_main_dl.c L_PROG_SIZE H 4000 sh7734_main_dl.c L_PROG_SRC H E520 0000 sh7734_main_dl.c IL IL L_PROG_DST 0 sh7734_main_dl.c SH7734 APROG_TOP_RAM H AC00 0000 sh7734_main_dl.c P2 MMU APROG_TOP_SFLASH H 4000 sh7734_main_dl.c R01AN0667JJ0100 Rev.1.00 Page 35 of 55
SH7734 APPINFO_TOP APROG_TOP_RAM sh7734_main_dl.c DDR2-SDRAM APPINFO_END APROG_TOP_RAM + 4 sh7734_main_dl.c DDR2-SDRAM *1 R01AN0667JJ0100 Rev.1.00 Page 36 of 55
SH7734 9.4 9.4 7.4 RSPI 9.4 main write_prog_data init_erase_flag is_erased_sector set_erase_flag halt error R_RSPI_SFProtectCtrl R_RSPI_SFSectorErase R_RSPI_SFByteProgram / Error / RSPI 1 R01AN0667JJ0100 Rev.1.00 Page 37 of 55
SH7734 9.5 7.5 RSPI main r_rspi_dl.h void main(void) LED4 ROM IL DDR2-SDRAM write_prog_data / r_rspi_dl.h static int32_t write_prog_data(uint8_t *program_data, const uint32_t sflash_addr, const uint32_t size) / Verify uint8_t *program_data const uint32_t sflash_addr const uint32_t size 1 0 0 init_erase_flag static void init_erase_flag(void) R01AN0667JJ0100 Rev.1.00 Page 38 of 55
SH7734 is_erased_sector static volatile uint8_t is_erased_sector(const uint32_t sector_no) uint32_t sector_no 1 0 set_erase_flag static void set_erase_flag(const uint32_t sector_no) uint32_t sector_no halt static void halt(void) error Error static void error(void) Error R_RSPI_SFProtectCtrl / r_rspi_dl.h void R_RSPI_SFProtectCtrl(const enum sf_req req) / enum sf_req req UNPROTECT_WR_STATUS PROTECT_WR_STATUS R01AN0667JJ0100 Rev.1.00 Page 39 of 55
SH7734 R_RSPI_SFSectorErase r_rspi_dl.h void R_RSPI_SFSectorErase(const uint32_t sector_no) uint32_t sector_no R_RSPI_SFByteProgram RSPI 1 r_rspi_dl.h void R_RSPI_SFByteProgram(const uint32_t addr, const uint8_t *buf, const uint32_t size) 1 SPCMD SPB[0:3] 8 uint32_t addr uint8_t *buf uint32_t size 1 R01AN0667JJ0100 Rev.1.00 Page 40 of 55
SH7734 9.6 9.3 OL Start downloader_sf resetprg_dl.c (R15) 1 2 SH7734 DBSC3SR 3 main sh7734_main_dl.c main LED4 4 RSPI 5 6 7 No Yes 8 No Yes 9 LED4 10 error halt 1 7 9.3 R01AN0667JJ0100 Rev.1.00 Page 41 of 55
SH7734 9.4 write_prog_data() R01AN0667JJ0100 Rev.1.00 Page 42 of 55
SH7734 (1) R15 H'E501 2000 OL 9.5#pragma entry #pragma entry downloader_sf (sp=0xe5012000) 9.5 (2) SR BL=1 (3) SH7734 DBSC3 SR SH7734 SH7734 SH7734 R01AN0665JJ (4) LED4 LED4 (5) RSPI RSPI (6) Write Status Register R01AN0667JJ0100 Rev.1.00 Page 43 of 55
SH7734 (7) IL H'E520 0000 H'E520 3FFF H'0000 0000 H'0000 3FFF 9.5 9.5 IL H'E520 0000 H'0000 0000 H'4000 1 (8) DDR2-SDRAM H'0000 4000 9.6 9.6 DDR2-SDRAM appinfo downloader sh7734_main.c #define APROG_TOP_RAM H'0000 4000 appinfo 1. 2. 3. 1 (9) IL DDR2-SDRAM (10) LED4 LED4 R01AN0667JJ0100 Rev.1.00 Page 44 of 55
SH7734 9.7 9.7RSPI 9.7 High-Speed Read H'0B Write Enable H'06 Write Disable H'04 Read Status Register H'05 Write Status Register H'01 Secter Erase (64Kbytes) H'D8 64KB Page Program H'02 1 R01AN0667JJ0100 Rev.1.00 Page 45 of 55
SH7734 10. 10.1 [sh7734_sflash_app] 10.1.1 High-performance Embedded Workshop E10A-USB High-performance Embedded Workshop [] > R01AN0667JJ0100 Rev.1.00 Page 46 of 55
SH7734 10.1.2 IL OL DDR2-SDRAM High-performance Embedded Workshop CPU SH7734 WDT MMU PFC DBSC3 DDR2-SDRAM IL IL IL 16k IL () RAM halt error IL OL DDR2-SDRAM halt error halt error 10.1 R01AN0667JJ0100 Rev.1.00 Page 47 of 55
SH7734 10.1.3 10.2 [sh7734_sflash_app] [sh7734_sflash_app] 10.2 10.2 10.2 [sh7734_sflash_app] (1) [ ] [ ] High-performance Embedded Workshop [] >[ ] High-performance Embedded Workshop (2) [] [] High-performance Embedded Workshop [] >[ ] [ ] [] [ ] [ ] High-performance Embedded Workshop R01AN0667JJ0100 Rev.1.00 Page 48 of 55
SH7734 10.1.4 [sh7734_sflash_app] 1. [sh7734_sflash_app] C: WorkSpace 2. [sh7734_sflash_app].hws High-performance Embedded Workshop 3. High-performance Embedded Workshop [ ] >[ ] 4. High-performance Embedded Workshop [] >[] 5. High-performance Embedded Workshop [] >[ ] 10.3[ ] 6. [ ][] [downloader.hdc] 10.3 [ ][] 7. [downloader.hdc] RAM 10.4 halt error 8. R01AN0667JJ0100 Rev.1.00 Page 49 of 55
SH7734 _halt 10.4 High-performance Embedded Workshop _error R01AN0667JJ0100 Rev.1.00 Page 50 of 55
SH7734 10.2 PC BREAKPOINT PC BREAKPOINT PC PC PC 1 PC R01AN0667JJ0100 Rev.1.00 Page 51 of 55
SH7734 10.3 Quad-SPI Quad-SPI 10.3.1 Quad-SPI 10.1 3 10.1 sh7734_qsflash_loader_prog Quad-SPI sh7734_sflash_app sh7734_sflash_downloader Quad-SPI RSPI RSPI Quad-SPI 10.3.2 Quad-SPI (1) RSPI Quad-SPI (2) RSPI Quad-SPI 1.3.2 (3) 1 RSPI 10.5 8 Quad-SPI Quad-SPI 2 Quad-SPI 4 10.5 RSPI R01AN0667JJ0100 Rev.1.00 Page 52 of 55
SH7734 10.6 Quad-SPI Quad-SPI (4) IL RSPI 7.1.1 (5) SPI 10.2 Quad-SPI SPI SPI SPI 3 CPOL=1, CPHA=1 12.5MHz (6) RSPI 10.3 Quad-SPI sh7734_main_lp.c Quad-SPI r_dmac_lp.c Quad-SPI HPB-DMAC RSPI r_rspi_lp.c r_rqspi_lp.c Quad-SPI r_rqspi_qserial_flas h_lp.c r_rqspi_lp.h r_rqspi_qserial_flas h_lp.h Quad-SPI Quad-SPI Quad-SPI RSPI r_rspi_lp.c IF R01AN0667JJ0100 Rev.1.00 Page 53 of 55
SH7734 (7) RSPI sh7734_qsflash_loader_prog (8) RSPI Quad-SPI 7.6 10.3.3 Quad-SPI High-performance Embedded Workshop Session DefaultSession qsflashsession sh7734_qsflash_loader_prog.abs 10.1 10.7 Quad-SPI [sh7734_sflash_app] R01AN0667JJ0100 Rev.1.00 Page 54 of 55
SH7734 11. 12. SH7734 Rev.1.00 SuperH C/C++ V.9.04 Rev.1.00 http://japan.renesas.com http://japan.renesas.com/contact/ R01AN0667JJ0100 Rev.1.00 Page 55 of 55
SH7734 Rev. 1.00 A-1
1. CMOS LSILSI 2. LSI 3. 4. 5. A-1
1. 2. 3. 4. 5. OA AV 6. 7. 8. RoHS 9. 10. 11. 1. 2. http://www.renesas.com 100-00042-6-2 (03)5201-5307 http://japan.renesas.com/contact/ 2012 Renesas Electronics Corporation. All rights reserved. Colophon 2.0