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CMOS 0.35um CMOS, 3V CMOS 2
RF CMOS RF CMOS RF CMOS RFCMOS (ADC Fabless 3
RF CMOS 1990 Abidi (UCLA): Fabless RF CMOS CMOS 90% 4
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f T [GHz] 450 400 350 300 250 200 150 Technology loadmap L[nm] f T [GHz] 80 70 60 50 40 30 100 20 2004 2006 2008 2010 2012 2014 Gate length [nm] Technology loadmap year year CMOS Vdd [V] 1.4 Vdd 1.3 1.2 1.1 1 0.9 2004 2006 2008 2010 2012 2014 (Vdd), 6
SNR LSI 7
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Controller 9
1 Ts = 2 / s 10
2 Ts = 2 / s 11
- - CMOS CMOS 12
CMOS CMOS CMOS 4 13
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RF CMOS Nauta OTA) RF P Vinp Vin P N 0 Vout Vinn N P N P N P N Nauta OTA P N P N Von Vop 16
MOS 17
- - CMOS 18
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CMOS 20
- - Voltage 1/fs fs Time 1/2fs 2fs Time 21
- - Down-sampling Vin RF signal Baseband signal Sampling LPF LPF Vout 22
- - Frequency conversion Band selection 23
V1 clk clk C clk clk V2 C R MOS R R = T / C T: clk clk 24
TIUCLA 25
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3b ADC 3b DAC 27
LPF b ADC b DAC LPF PDM () 28
OSR=28 OSR=210 OSR=216 OSRON,OFF OSR: Sampling 29
Low-IF RF Zero-IF DC1/f RF Low-IF AD 30
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DAC I Iin Qin + Analog Input + - - H(z) Complex Banpass Filter E i ADC I ADC Q E q Iout Digital Output Qout DAC Q I out + jq H 1+ H out (I in = + jq in ) + 1 1+ H (E i + je q ) 32
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CMOS TDC 1988 VLSI Circuit Symp All Digital PLL Bogdan Staszewski ( Digital Radio Processor MOS 36
ref(t) T D Q D Q D Q in(t) D0 D1 D2 ref D0=1 D1=1 D2=1 D3=0 D4=0 Encoder Dout in CMOS 37
ADC 1 ADC 38
ADC Signal Level Signal Comparator Output Reference Clock Tout1 Tout2 Tout3 Time Time 39
40 ADC t = T t A t V ref π 2 cos ) ( = A t A T t in n ) ( arccos ) ( 2 cos t A T t A in = π Ain Vref
VDD)
0.6V 160ps t 1 t 2 t 3 t 4 t 5 t 6 160ps 160ps 160ps 160ps 160ps 160ps q 1 =1 q 2 =1 q 3 =0 q 4 =0 q 5 =0 q 6 =0
43 t 1 t 2 t 3 t 4 t 5 1.0V 100ps 100ps 100ps 100ps 100ps 100ps 100ps q 1 =1 q 2 =1 q 3 =1 q 4 =1 q 5 =0 q 6 =0 t 6
CLKin R A B TDC Dout Cmeasure CLKin A B T TDC TRCmeasure
CLK TDC (NTU, Harvard Univ.) A TDC Dout B A A B B TDC
All Digital PLL FreqData CKref TDC Phase error DCO CKout 46
PWM PWM ON CLK PWM. 47
10bit1023 48
A0B3 A1B21-2 A2B1 21-22 2 A3B0 31-32 3 A1B3 1 4 A2B2 21-2 1+ A3B1 31-22 1+2 A4B0 41-32 1+3 A2B3 21 14 A3B2 31-2 21+ A4B1 41-22 21+2 A5B0 51-32 21+3 49
A0,B3. A2,B1. 2 A3,B. 1 2 3 50
Digital Input e1 e2 e3 e4 en 1 2 3 4 N + 1 + L+ N 1 + 1 2 + 3 1 2 1 0001 0010 0011 51
0010 M U X M U X M U 1 2 3 4 X M U X N M U X e1 e2 e3 e4 en 12 24 1N 12 24 1N 52
RC (ISI) 53
PWM Twente VDD GND PE 1bit PWM 1bit ISI 54
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ElectroMagnetic Interference EMS EMI EMC EMS EMI Electro Magnetic Compatibility 57
EMI EMI () f ( ) f 58
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RFout 60
UCSD Larson RFout 61
MADCM ADC ADC 62
ADC1 ADC2 dc 0.2V 1ch dc 0.2V 2ch DCDC DCDC 63
ADC χ(0)χ(1)χ(2)χ(3)χ(4) CLK0 ADC0 ADC1 X 0 (f) X 1 (f) 1 4Ts 2 4Ts 3 4Ts 4 4Ts CLK1 ADC2 X 2 (f) CLK2 ADC3 X 3 (f) CLK3
ADC X 0 (f) χ(0)χ(1)χ(2)χ(3)χ(4) 1 4Ts 2 4Ts 3 4Ts 4 4Ts f X 1 (f) f χ(0) f s =1/T s χ(4) X 2 (f) f 1 4Ts 2 4Ts 3 4Ts 4 4Ts f X 3 (f) X(f)= X 0 (f)+ X 1 (f)+ X 2 (f)+ X 3 (f) f = χ (0) + χ(4) 65
ADC X 0 (f) X 1 (f) χ(0) χ(1) χ(2) χ(3) χ(4) 1 4Ts 2 4Ts 3 4Ts 4 f 4Ts f Spurious components χ(0) χ(4) X 2 (f) X 3 (f) f 66 1 4Ts 2 4Ts 3 4Ts 4 4Ts X(f)= X 0 (f)+ X 1 (f)+ X 2 (f)+ X 3 (f) f λ 0χ (0) + λ 1χ (1) + λ 2χ (2) + λ 3χ (3) + λ 4χ (4) f
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AD 68
DAC 69
23.5 23.5 Vin 4 1 2 8 Vin 16 Vin16 Vin< Vin>20 Vin>22 Vin>23 24 1 2 = 8 16 4 = 23 70
k d(k) : +1 or -1 2 Dout=2 4 +d(1)2 3 +d(2)2 2 +d(3)2 1 +d(4)+d(5)0.5-0.5 256 2 Dout=2 4 +d(1) 4 +d(2) 3 +d(3) 2 +d(4) 1 +d(5)+d(6)0.5-0.5 5 1<<2 γ = 2 6 71
72 5 0.5 0.5 1 1 1 4 0111 5 0.5 0.5 1 1 1 4 1101 2 5 0.5 0.5 1 2 4 :101 2 5 = + + + = = + + + = = + + = Dout Dout Dout 2
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x x Rx Tx IC 75
ADPLL Rx, Tx Rx, Tx 76
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UC Santa Barbara Prof. Chen 78
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- - - 80