- 5ns - f CNT 25MHz - 800~6,400 36~288 5V ISP - 0,000 / - / 36V8-90 8 - IEEE 49. JTAG 24mA 3.3V 5V PCI -5-7 -0 CMOS 5V FastFLASH XC9500 XC9500CPLD 0,000 / IEEE49. JTAG XC9500 36 288 800 6,400 2 XC9500 XC9500 PC JTAG 0,000 / 3.3V 5V 24mA XC9500 FastCONNECT TM FB IOB IOB FB 36 8 FastCONNECT FB FB FB 2 8 IOB Version 2.0 Page
XC9500 ISP CPLD JTAG Port 3 JTAG Controller In-System Programming Controller 8 36 Function Block Macrocells to 8 /GCK /GSR /GTS 3 2 or 4 Blocks FastCONNECT Switch Matrix 8 8 8 36 36 36 Function Block 2 Macrocells to 8 Function Block 3 Macrocells to 8 Function Block N Macrocells to 8 X5877 : XC9500 : XC9500 Macrocells 36 Usable Gates 800 Registers 36 t PD (ns) t SU (ns) t CO (ns) f CNT (MHz) f SYSTEM (MHz) XC9536 XC9572 XC9508 XC9544 XC9526 XC95288 5 4.5 4.5 00 00 f CNT = 6 72,600 72 7.5 5.5 5.5 25 83 08 2,400 08 7.5 5.5 5.5 25 83 f SYSTEM = FB 44 3,200 44 7.5 5.5 5.5 25 83 26 4,800 26 0 6.5 6.5 67 288 6,400 288 5 8.0 8.0 95 56 2 Version 2.0 Page 2
2: JTAG XC9536 XC9572 XC9508 XC9544 XC9526 XC95288 44-Pin PLCC 34 34 44-Pin VQFP 34 84-Pin PLCC 69 69 00-Pin TQFP 72 8 00-Pin PQFP 72 8 8 60-Pin PQFP 08 33 33 208-Pin HQFP 66 68 352-Pin BGA 66 92 2 FB 8 FB / FB 8 FastCONNECT 8 IOB FB " " 36 72 / AND 90 90 FB XC9536 FB FB AND FB Macrocell From FastCONNECT Switch Matrix 36 Programmable AND-Array Product Term s 8 8 OUT To FastCONNECT Switch Matrix 8 PTOE To Blocks Macrocell 8 3 Global Set/Reset Global Clocks X5878 2: XC9500 Version 2.0 3 Page 3
XC9500 ISP CPLD XC9500 3 FB AND5 OR XOR / 5 D T 0 36 Global Set/Reset Global Clocks 3 Additional Product Terms (from other macrocells) Set 0 S D/T Q To FastCONNECT Switch Matrix Product Term Clock Reset R OE OUT PTOE To Blocks Additional Product Terms (from other macrocells) 3: XC9500 X5879 4 Version 2.0 Page 4
/ 4 3 GCK GSR Set Macrocell Clock Reset S D/T R /GSR Global Set/Reset /GCK Global Clock /GCK2 Global Clock 2 /GCK3 Global Clock 3 X5880 4: / Version 2.0 5 Page 5
XC9500 ISP CPLD 5 5 5 OR 5 FB FB 6 tpta 5 Macrocell Logic With 5 P-Terms Macrocell Logic X5894 5: X5895 6: 5 6 Version 2.0 Page 6
FB 7 2*t PTA 8*t PTA 90 Macrocell Logic With 2 s Macrocell Logic With 8 s X5896 7: Version 2.0 7 Page 7
XC9500 ISP CPLD 8 From Upper Macrocell To Upper Macrocell Set Global Set/Reset 0 Global Clocks Clock S D/T R Q Reset Global Set/Reset OE 8: From Lower Macrocell To Lower Macrocell X588 8 Version 2.0 Page 8
FastCONNECT 9 FB IOB FB FastCONNECT FB 36 FB FastCONNECT AND FB FB FB FastCONNECT Switch Matrix Function Block (36) 8 Block D/T Q Function Block Block (36) 8 D/T Q Wired-AND Capability X5882 9: FastCONNECT Version 2.0 9 Page 9
XC9500 ISP CPLD IOB IOB 0 5V CMOS 5V TTL 3.3V 5V VCCINT VCCIO OE "" "0" 4 44 2 80 4 GTS To other Macrocells V CCINT Block To FastCONNECT Switch Matrix Macrocell Pull-up Resistor OUT (Inversion in AND-array) OE PTOE User- Programmable Ground 0 Slew Rate Control /GTS Global OE /GTS2 Global OE 2 /GTS3 Global OE 3 Available in XC9580, XC9526 and XC95288 /GTS3 Global OE 4 X5899 0: ersion 2.0 Page 0
tslew IOB 0K 24mA VCCIO 5V 3.3V 5V TTL 3.3V 2 XC9500 5V 3.3V 5V XC9500 XC9500 FastCONNECT PC Output Voltage Output Voltage Standard Slew-Rated Limited Slew-Rated Limited t SLEW t SLEW.5 V.5 V Standard Time 0 0 (a) (b) Time X5900 : a b 5 V CMOS 5 V 5 V CMOS 5 V 3.3 V 5 V 5 V V CCINT V CCIO V CCINT V CCIO 5 V TTL or 5 V TTL 5 V TTL or 3.3 V 3.6 V IN XC9500 CPLD OUT ~ 4 V 3.6 V IN XC9500 CPLD OUT 3.3 V 3.3 V or 3.3 V or 3.3 V GND 3.3 V GND (a) (b) X590 2: a 5V b 3.3V/5V XC9500 Version 2.0 Page
XC9500 ISP CPLD XC9500 4 JTAG 3 JTAG JTAG JTAG High Low XC9500 HW30 XC9500F XC9536F XC9572F XC9508F XC9500 JEDEC XC9500F XC9500 JTAG XC9500F HW30 XC9500F 44 VQFP 84 PLCC 00 PQFP 60 PQFP XC9500CPLD 0,000 / XC9500 IEEE 49. JTAG EXTEST SAMPLE/PRELOAD BYPASS USERCODE INTEST IDCODE HIGHZ ISP 49. ISPEN FERASE FPGM FVFY ISPEX 5 XC9500 / 3 4 JTAG 3: Write Security Default Set Default Read Allowed Program/Erase Allowed Read Allowed Program/Erase Inhibited Read Security Set Read Inhibited Program/Erase Allowed Read Inhibited Program/Erase Inhibited X5905 2 Version 2.0 Page 2
V CC GND (a) (b) X5902 3: a PC b XC9500 tlp XC9500 4 4 0 5 5 7 8 2 5 XC9500 Version 2.0 3 Page 3
XC9500 ISP CPLD Combinatorial Logic t SU Combinatorial Logic D/T Q t CO Propagation Delay = t PD (a) Setup Time = t SU Clock to Out Time = t CO (b) t PSU Combinatorial Logic D/T Q P-Term Clock Path Combinatorial Logic D/T Q t PCO Setup Time = t PSU Clock to Out Time = t PCO (c) Internal System Cycle Time = t SYSTEM (d) All resources within FB using local Feedback Combinatorial Logic D/T Q Internal Cycle Time = t CNT (e) 4: t F t LF t IN t LOGILP t LOGI S*t PTA D/T t PDI Q t OUT t SLEW t GCK t PTCK t PTSR > t SUI t COI t HI t AOI t RAI SR t EN t GSR t PTTS t GTS 5: XC9500 XC9500 VCCINT 3.8V JTAG IOB 0K 5 00 s 9536 9544 00 s 9526 200 s 95288 300 s 6 IOB JTAG JTAG 4 Version 2.0 Page 4
XC9500 CPLD Alliance ABEL VHDL HDL JEDEC JEDEC XC9500 JTAG JTAG CMOS Flash XC9500 CPLD FastFLASH 0,000 / 3.8 V (Typ) V CCINT No Power Quiescent State User Operation Quiescent State No Power Initialization of User Registers X5904 6: 4: Description Parameter Macrocell Output Slew-Limited Low-Power Setting Setting Propagation Delay t PD + t PTA * S +tlp + t SLEW Global Clock Setup Time t SU + t PTA * S +tlp Global Clock-to-output t CO + t SLEW Clock Setup t PSU + t PTA * S +tlp Time Clock-to-output t PCO + t SLEW Internal System Cycle Period t SYSTEM + t PTA * S + t LP. S = 5: XC9500 Device Circuitry Quiescent State Erased Device Operation Valid User Operation IOB Pull-up Resistors Enabled Enabled Disabled Device Outputs Disabled Disabled As Configured Device Inputs and Clocks Disabled Disabled As Configured Function Block Disabled Disabled As Configured JTAG Controller Disabled Enabled Enabled Version 2.0 5 Page 5
XC9500 ISP CPLD 6 Version 2.0 Page 6