Design at a higher level

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2 Meropa FAST

4 HLS, Mapping, Timing, HDL, GUI, Chip design Cadence, Synopsys, Sente, Triquest Ericsson, LSI Logic

5 1980 RTL RTL gates Applicability of design methodologies given constant size of design teams and schedules 500k BL 100k RTL 30k schematic 5k 70 s 80 s 90 s 00 s year

6 K 5-10K K 50+K RAM

7 RTL FSM RTL

8 RTL RTL

9 FAST = Flexible Architecture Synthesis Technology Speed RTL 2 5 Predictability Speed & Predictability

12 (Fast and Predictable)

13 I/O FSM

14 Wait until start_in if valid(addr) busy save 2-1/2 words into memory else wrong addr wait until ready_in not busy

15 RTL ready_in&start_in&valid Case (state) s0 : if (valid(addr)) mem1; else ns = s0; s1 : mem2; ns = s2; s2 : if (ready_in&start_in&valid) mem1; ns = s1; else if (!ready_in) ns = s4; else if (ready_in&start&!valid) ns = s3; else ns = s0; s3 :...!valid/error s3!ready_in s0 s4 valid/mem1 valid/ mem1 s1 mem2 s2!ready_in ready_in &start_in &valid/ mem1

16 FAST forever begin : infin while (!start_in) `clk //s0 if (valid(addr)) begin start <= 0; storage[i] = data[31:0]; storage[i+1] = data[63:32]; I = I + 2; `clk //s1 `clk //s2 end else begin error <= 1; `clk //s3 end while (!ready_in) clk //s4 start <= 1; end!valid/error s3!ready_in ready_in&start_in&valid s0 s4 valid/mem1 valid/ mem1 s1 mem2 s2!ready_in ready_in &start_in &valid/ mem1

17 ? RTL 1/10 RTL 20 Speed & Predictability

18 FAST latency, area, RAM throughput, clock Behavioral Verilog lbr FAST area Alternative architectures Gate-level Verilog RTL Verilog simulation clockperiod Throughput / latency logic synthesis area, clockperiod Gate-level Verilog Layout

19 RTL VS FAST RTL I/O FSM

20 RTL RTL 2 FSM

21 Meropa FAST FSM FAST

22 FAST

23 FAST FSM

24 while (!crc(bitsi,compute_crc)) begin : clk or negedge rst); if (!rsthi) disable always_block; not_rdy <= 1; attempts = attempts + 1; end; if (attempts <= upper_limit) newsynd = crc(bitsi,compute_new_synd); else cumm_failures = cumm_failures + 1; 13ns `clk cumm_res <= cumm_failures; 7 <= 9 crc + crc mux ns

25 while (!crc(bitsi,compute_crc)) begin : clk or negedge rst); if (!rsthi) disable always_block; not_rdy <= 1; attempts = attempts + 1; end; if (attempts <= upper_limit) newsynd = crc(bitsi,compute_new_synd); else cumm_failures = cumm_failures + 1; 20ns `clk cumm_res <= cumm_failures; 7 <= mux mux mux 1.5 mux 9 crc ns

26 FAST RTL RTL

27 adder, alu, multiplier, subtractor multiplexers */+ +/+, +/-...

29 FAST Verilog 5 ( Verilog) 1 RTL RTL Speed & Predictability

30 FAST Speed & Predictability

31 always begin : rst_loop reg [7:0] va, vb, vc, vd; 750 ro <= 0; io <= 0; `clk forever begin : inifin 500 va = ai; `clk 250 vb = ai; `clk vc = ai; `clk vd = ai; for (i-0; i <= ltncy; i=i+1): begin scale clk end //for ro <= va*vc - vb*vd; io <= va*vd + vb*vc; `clk end//infin end//always CLK CLK 0 2*, 1+/- 1 1*, 1+, 1 ALU 2 1*,1+/- 3 1*,1+/- 4 1 ALU * including script creation

32 always begin : rst_loop reg [7:0] va, vb, vc, vd; reg [5:0] TBL [127:0] ro <= 0; io <= 0; `clk forever begin : inifin while (!start) `clk if (valid_lkp) va1 = TBL[ptr1]; val2 = TBL[ptr2]; incs = val1[8:3] - val2[8:3] if (incs == 1) for (I=0;I<=7;I=I+1) begin do <= main[val1 + I]; end end else... vc; `clk end//infin end//always FAST port RAM 2 port RAM mem1 mem2 sub1 mem mem1 sub1 mem3 mem port RAM combinational out mem1 mem2 sub1 mem3 Speed & Predictability

33 FSM RTL

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untitled Verilog HDL Verilog HDL VerilogHDL veriloghdl / CPLD , 1bit 2 MUX 5 D,E) always) module MUX(out, a, b, sel); output out; input a, b, sel; A) IF module MUX(out, a, b, sel); output out; input a, b, sel;