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1 ASIC, LIBRARY&TOOLS ASIC PCI 1998/12/18 (Revision 1.6)

2 Revision 1.6 PCI Revision 1.2 Revision BusError. 2. AD, nc BE, PAR, ADenb, C BEenb, PARenb.,,,. Revision 1.3 Revision PCI RST# input nrst. 2. Ready, iaccess. 3. ReadMem, ReadMemLine, ReadConfig, ReadMemReq, ReadMemLineReq, ReadConfigReq 2, Be. 4.. pci.h PCI.h HostBridge bridge 5.,.,,. 6. ReadConfigReq, WriteConfigReq., PCI,. 7.,., ReadConfig, WriteConfig.,., bridge PCI ( 3 (2) PCIb), PCI (, PCIb )., PCI,, ( 3 ) PCI , PCI,,. 9. IDSEL, FRAME# 1,., IDSEL,. Revision 1.4 Revision bidirect Adr, Be, Data, AD, nc BE, PAR input AdrIn, output AdrOut., bidirect. s/t/s t/s,. 2. ReadConfigReq, WriteConfigReq. ReadMemReq,. Revision 1.5 Revision nreq output nreqout, instrout REQenb., REQ#, RST# PCI. Copyright c : NTT (nagami@exa.onlab.ntt.co.jp) 2

3 PCI Revision iaccess PCI PCI A 15 B 16 C SFL (PCI.h) 21 3

4 Revision 1.6 PCI, ASIC, LIBRARY&TOOLS ASIC, PCI. PCI, PCI Revision 2.1,. PCI., PCI, [3, 4, 6, 9 12].,, PCI, PCI ( 1). PCI,,.,,,., PCI,.,, ( iaccess ), PCI, PCI,.,. 1 3 (1). dlx DLX [2] CPU,. CPU, iaccess., system1 SFL,., SECONDS SECONDS., 3 (2). CPU, PCI PCI. PCIbus,,., bridge PCIb., CPU iaccess, PCI PCI ( ipci ), PCI. bridge, PCI. system2., PCI SFL. 3, 2 PCI ( ), 1., 2 PCI., PCI, system1 system2. 1 PCIb ( ), 4

5 PCI Revision 1.6 PCI.,, PCIb. 3 (1), (2), system1, system2,., PCI, CPU PCI, system1, system2., PCI [7] SFL PCI, PCI.h ( )., 4.,.,, SECONDS.,, n ( : PCIrdy, nframeout)., PCI,. 2.2, AD, FRAME#,, 3 (*, PCI #. n ). input n*in,. output n*out,. instrout *enb: instr arg *enb(n*out),., output n*out., FRAME# input nframein, output nframeout, instrout FRAMEenb, instr arg FRAMEenb(nFRAMEout)., 2., PCI /, SFL. FRAME#. 5

6 Revision 1.6 PCI module PCI {... FRAMEenb(0b0); /* */... FRAMEenb(0b1); /* */... nframeout = 0b0; /* N.G. */... R := nframein; /* */ },, 3 PCIbus, PCI *enb, PCIbus n*in iaccess, PCI, iaccess. instrout Ready,, 1( High).,, ReadMem, ReadMemLine, WriteMem, ReadIO, WriteIO, ReadConfig, WriteConfig. instrout Reset. instrout BusError. PCI, input AdrIn<32>, output AdrOut<32> iaccess ( I/O ). AdrIn PCI (iaccess ) AdrOut iaccess. input BeIn<4>, output BeOut<4>,. BeIn PCI (iaccess ) BeOut iaccess. (Be(In, Out)<3> Data(In, Out)<31:24>) (Be(In, Out)<2> Data(In, Out)<23:16>) (Be(In, Out)<1> Data(In, Out)<15:8>) (Be(In, Out)<0> Data(In, Out)<7:0>) 6

7 PCI Revision 1.6, Be(In, Out) 1,. input DataIn<32>, output DataOut<32>. DataIn iaccess DataOut iaccess. instrin ReadMem(AdrIn, BeIn) iaccess, 1. ( 2 00)., ReadDone, DataOut., AccessError. instrin ReadMemLine(AdrIn, BeIn) iaccess, 1., ( PCI ),. AdrIn,,., AdrIn, AdrIn + 1,..., ( ), ( ),..., AdrIn -1,., ReadDone, DataOut., ReadMemLine, ( ) ReadDone., AccessError. instrin WriteMem(AdrIn, BeIn, DataIn) iaccess, 1. ( 2 00),,. WriteDone,., AccessError. instrin ReadIO(AdrIn, BeIn) iaccess, 1 I/O. AdrIn, I/O I/O. BeIn, AdrIn, AdrIn<1:0>, BeIn 1., AdrIn 4, AdrIn 2 00, BeIn 1., ReadDone DataOut., BeIn 0., AccessError. instrin WriteIO(AdrIn, BeIn, DataIn) iaccess, 1 I/O. AdrIn, I/O I/O, BeIn, DataIn. 7

8 Revision 1.6 PCI AdrIn<1:0> BeIn<3:0> : 0, 1 1: I/O BeIn AdrIn, BeIn, ReadIO. WriteDone, AccessError. instrin ReadConfig(AdrIn, BeIn), PCI. AdrIn,., ReadDone, DataOut., AccessError.,,. 1. n (0 n 20) IDSEL, AD (11 + n). ADout, AdrIn. 2. IDSEL, 2., 1 ADout. instrin WriteConfig(AdrIn, BeIn, DataIn), PCI. AdrIn,. WriteDone, AccessError.,, ReadConfig. instrout ReadDone(DataOut) ReadMem, ReadMemLine, ReadIO, ReadConfig,. DataOut. instrout WriteDone() WriteMem, WriteIO, WriteConfig,. instrout AccessError() ReadMem, ReadMemLine, ReadIO, ReadConfig, WriteMem, WriteIO, WriteConfig,. 8

9 PCI Revision 1.6 instrout ReadMemReq(AdrOut, BeOut) iaccess. AdrOut,. iaccess, ReadReqDone DataIn., ReqError. instrout ReadMemLineReq(AdrOut, BeOut) iaccess, 1. Adr,,.., ReadReqDone, 1 DataIn., ReqError. instrout WriteMemReq(AdrOut, BeOut, DataOut) iaccess,. AdrOut. BeOut, DataOut WriteMem., WriteReqDone, ReqError. instrout ReadIOReq(AdrOut, BeOut) iaccess I/O. AdrOut I/O. BeOut, ReadIO., ReadReqDone DataIn., ReqError. instrout WriteIOReq(AdrOut, BeOut, DataOut) iaccess, I/O. AdrOut I/O. BeOut, DataOut WriteIO., WriteReqDone, ReqError. instrin ReadReqDone(DataIn) ReadMemReq, ReadMemLineReq, ReadIOReq,. DataIn. instrin WriteReqDone(). WriteMemReq, WriteIOReq, instrin ReqError() ReadMemReq, ReadMemLineReq, ReadIOReq, WriteMemReq, WriteIOReq,. iaccess, 5, 6, 7., =4.,,,., 1, 1,. 9

10 Revision 1.6 PCI, AccessError, ReqError, AccessError, ReqError,. 1., ReadMem, ReadMemLine, WriteMem, ReadIO, WriteIO, ReadConfig, WriteConfig,.., iaccess,., iaccess iaccess PCI, PCI.,, 3., PCI, SERR#. input nrst<32> PCI nrst#. input ADin<32>, output ADout<32>, instrout ADenb(ADout) PCI AD#. PCI,,,. ADout, ADenb. input nc BEin<4>, output nc BEout<4>, instrout C BEenb(nC BEout) PCI C/BE#.,. nc BEout, C BEenb. input PARin, output PARout, instrout PARenb(PARout) PCI PAR., ADout, ADout<32>, nc BE<4> 36,, 1 PARout. PARout, PARenb. input nframein, output nframeout, instrout FRAMEenb PCI FRAME#..,. input nirdyin, output nirdyout, instrout IRDYenb PCI IRDY#.. input ntrdyin, output ntrdyout, instrout TRDYenb PCI TRDY#.. input nstopin, output nstopout, instrout STOPenb PCI STOP#.,. 10

11 PCI Revision 1.6 instrin IDSEL PCI IDSEL.. input ndevselin, output ndevselout, instrout DEVSELenb PCI DEVSEL#.,. output nreqout, instrout REQenb. PCI REQ#., output ngnt PCI GNT#.,. input nperrin, output nperrout, instrout PERRenb PCI PERR#. AD, nc BE. instrout SERRenb PCI SERR#.. 3 PCI PCI, PCI,. 3.1 PCI, C/BE# I/O 0010 I/O , ( ),,. ( ),.. AD, PAR 11

12 Revision 1.6 PCI.., (ADin<1:0> 0b00) (ADin<1:0> 0b01). 3.2,,,,,, 3.3 REQ#, GNT#, SDONE, SBO#, INTA#, INTB#, INTC#, INTD#, PERR#., SERR#, PCI

13 PCI Revision IDSEL system2 SFL, IDSEL, AD.,,, IDSEL. (ReadConfig, WriteConfig ). 3.9 PCI, 256.,,.,,.,,. 4,. 1. PCI SFL PCI SFL PCI.sfl (ReadConfig, WriteConfig ), SFL PCIb SFL PCIb.sfl.. 3. system1, system2, PCI [8] Web. PCI.sfl ( PCIb.sfl ),. PCI.sfl. system1 system2,,, system1 system2 (,,, [7] ). 2,, ASIC, LIBRARY&TOOLS 13

14 Revision 1.6 PCI 4.,,., 3.,. 5 ASIC, LIBRARY&TOOLS, ( ) FAX ,, URL, ASIC, LIBRARY&TOOLS.,,. [1] Parthenon web. [2] David A. Patterson, John L. Hennessy,,, ( ) BP, 1, ISBN [3] Tom Shanley and Don Anderson. PCI System Architecture. PC System Architecture. Addison Wesley, third edition, ISBN [4] Edward Solari and George Willse. PCI Hardware and Software. Annabooks, third edition, ISBN , [5]. [5] Edward Solari, GeorgeWillse( ), Norman Rasmussen, Brad Hosler, WilliamSamaras( ), ( ) ( ). PCI &. ( ), 3, ISBN [6]. PCI ( 15 )., [7]. PCI. (PARTHENON Web [1] ), [8]. PCI. (PARTHENON Web [1] ), [9]. PCI, No. 7 in OpenDesign. CQ, ISBN [10],,,,,,. PCI/CompactPCI. Interface, pp , [11]. PCI ( )., [12],,,,,,,.! PCI &. Interface, pp ,

15 PCI Revision 1.6 A,,. 1 =8, 1 =2, 1 =2. CPU, memory, PCI, PCI., iaccess PCI., PCI, PCI, PCI. iaccess, iaccess iaccess, iaccess, iaccess iaccess. ( ) PCI,. {, I/O, }, {, I/O, } PCI, I/O., I/O., PCI, I/O., I/O. I/O, I/O,.,., PCI,,

16 Revision 1.6 PCI..,,, B PCI device function PCI handling to be designed PCI device function iaccess PCI to be designed library PCI protocol PCI protocol 1: PCI PCI FRAMEenb nframeout FRAME# nframein 2: 16

17 PCI Revision 1.6 system 1 dlxc (1) dlx cache memory iaccess iaccess local bus system 2 bridge dlxc dlx cache (2) memory iaccess PCIb iaccess PCI iaccess PCI ipci ipci ipci PCIbus Arbiter 3: 17

18 Revision 1.6 PCI SERRenb * * * bit width data uni. bi. direction type control FRAME# IRDY# TRDY# STOP# DEVSEL# Slave Access Master Access nframein nframeout FRAMEenb nirdyin nirdyout IRDYenb ntrdyin ntrdyout TRDYenb nstopin nstopout STOPenb IDSEL ndevselin ndevselout DEVSELenb ReadMem WriteMem ReadIO WriteIO ReadConfig WriteConfig ReadDone WriteDone AccessError ReadMemReq ReadMemLineReq WriteMemReq ReadIOReq WriteIOReq ReadReqDone WriteReqDone ReqErrror ReadMemLine IDSEL iaccess ipci DataIn DataOut 4 4 BeOut BeIn AdrIn AdrOut AD C/BE# PAR PARenb PARout PARin C_BEenb nc_beout nc_bein ADenb ADout ADin nrst RST# Ready Reset BusError SERR# PERR# GNT# nreqout REQenb REQ# ngnt nperrin nperrout PERRenb 4: 18

19 PCI Revision 1.6 Read Access clock Read* AdrIn BeIn ReadDone DataOut Read*Req iaccess master iaccess slave AdrOut BeOut ReadReqDone DataIn 5: iaccess : 19

20 Revision 1.6 PCI Write Access clock Write* AdrIn BeIn DataIn WriteDone Write**Req iaccess master iaccess slave AdrOut BeOut DataOut WriteReqDone 6: iaccess : Read Line Access clock ReadLine AdrIn ReadDone DataOut ReadLineReq iaccess master iaccess slave AdrOut ReadReqDone DataIn 7: iaccess : 20

21 PCI Revision 1.6 C SFL (PCI.h) 1 2 declare PCI { /* $Source: /home/nagami/src/master/dlx/pci.h,v $ 3 4 ** $Author: nagami $ ** $Name: $ 5 6 ** $Date: 1998/11/23 05:15:41 $ ** $Revision: 1.4 $ 7 8 ** $State: Exp $ */ 9 10 /**********************************++**********************************/ /* Access Interface */ /**********************************++**********************************/ /* Control signals */ instrout Ready; instrout Reset; instrout BusError; /* Data access signals */ input AdrIn<32>; output AdrOut<32>; 19 input BeIn<4>; output BeOut<4>; input DataIn<32>; output DataOut<32>; instrin ReadMem; instrin ReadMemLine; instrin WriteMem; instrin ReadIO; instrin WriteIO; instrin ReadConfig; instrin WriteConfig; instrout ReadDone; instrout WriteDone; instrout AccessError; instrout ReadMemReq; instrout ReadMemLineReq; instrout WriteMemReq; instrout ReadIOReq; instrout WriteIOReq; instrin ReadReqDone; instrin WriteReqDone; instrin ReqError; /**********************************++**********************************/ /* PCI interface */ /**********************************++**********************************/ /* System pins */ input nrst; /* Address and data pins */ input ADin<32>; output ADout<32>; instrout ADenb; input nc_bein<4>; output nc_beout<4>; instrout C_BEenb; input PARin; output PARout; instrout PARenb; /* Interface control pins */ input nframein; output nframeout; instrout FRAMEenb; input nirdyin; input ntrdyin; output nirdyout; output ntrdyout; instrout IRDYenb; instrout TRDYenb; input nstopin; instrin IDSEL; output nstopout; instrout STOPenb; input ndevselin; output ndevselout; output nreqout; instrout DEVSELenb; instrout REQenb; input ngnt; input nperrin; output nperrout; instrout PERRenb; 62 instrout SERRenb; 21

22 Revision 1.6 PCI /**********************************++**********************************/ /* Instruct Arguments */ /**********************************++**********************************/ instr_arg ReadMem (AdrIn, BeIn); instr_arg ReadMemLine(AdrIn, BeIn); instr_arg WriteMem instr_arg ReadIO (AdrIn, BeIn, DataIn); (AdrIn, BeIn); instr_arg WriteIO (AdrIn, BeIn, DataIn); instr_arg ReadConfig (AdrIn, BeIn); instr_arg WriteConfig(AdrIn, BeIn, DataIn); instr_arg ReadReqDone(DataIn); instr_arg WriteReqDone(); instr_arg ReqError(); instr_arg IDSEL(); /* In your PCI module, you should declare these instr_arg s. */ /* instr_arg Ready(); instr_arg Reset(); instr_arg BusError(); instr_arg ReadDone(DataOut); instr_arg WriteDone(); instr_arg AccessError(); instr_arg ReadMemReq (AdrOut, BeOut); instr_arg ReadMemLineReq(AdrOut, BeOut); instr_arg WriteMemReq instr_arg ReadIOReq (AdrOut, BeOut, DataOut); (AdrOut, BeOut); instr_arg WriteIOReq (AdrOut, BeOut, DataOut); instr_arg ADenb instr_arg C_BEenb (ADout); (nc_beout); instr_arg PARenb (PARout); instr_arg FRAMEenb (nframeout); instr_arg IRDYenb instr_arg TRDYenb (nirdyout); (ntrdyout); instr_arg STOPenb (nstopout); instr_arg DEVSELenb(nDEVSELout); instr_arg REQenb instr_arg PERRenb (nreqout); (nperrout); instr_arg SERRenb */ (); 107 } 22

TECH_I Vol.25 改訂新版PCIデバイス設計入門

TECH_I Vol.25 改訂新版PCIデバイス設計入門 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity n is port( ); end entity n; architecture RTL of nis begin when : process begin end process :process begin end process